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Code: 12D68101

M. Tech I Semester Regular Examinations, April/May 2013

ANALOG & DIGITAL IC DESIGN
(Common to VLSIES, ESVLSI & VLSIESD)
Time: 3 hours Max. Marks: 60
Answer any FIVE questions.
All questions carry equal marks.
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1 Draw the high frequency equivalent circuit of MOS transfer and explain its operation under
three operating regions.

2 (a) Draw and explain simple CMOS current mirror.

(b) In the cascade current mirror, where Iin=100 A and each transistor has w/L= 90 /(1.4 ).
Given that n cox = 92 2 , = 0.8 v and = [8000 ()] () . Find rout for the
current mirror. Iout
Iin

Q3
Q1


Q4 rout
Q2

L D
3
(a)
(b)
Write a short note on:
High output impedence current mirror.
Bipolar gain stages. O R
4
(a)
Explain:
Digital decimation filter.

U W
T
(b) Continuous time filters.

5 (a) Explain dynamic characteristics of CMOS inverter.

6
(b)

(a)
N
Consider a CMOS inverter circuit with the following parameters VDD = 3.3 V, VTo,n = 0.6 V,

J
VTo,p = -0.7 v, Kn = 200 2 , Kp = = 800 2 . Calculate the noise margin of the circuit.

Explain the following CMOS based design rules:

2 double metal, double poly CMOS rules.
(b) 1.2 double metal, single poly CMOS rules.

7 (a) Draw the mask layout for an 81 nMOS inverter circuit. Both the input and output points
should be on the polysilicon area.
(b) Derive expression for:
(i) Sheet resistance.
(ii) Area capacitance of layers.

8 Explain any two of the following:

(a) Pipeline multiplier array.
(b) Modified Booths algorithm.
(C) Carry look ahead adders.

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