1588v2 PTP Boundary Clocks

Conformance Testing
Time Error measurements

ITU-T recommendation G.8273.2 describes absolute time error

measurements for Telecom Boundary Clocks (T-BC) and gives an
example test bed for such measurements. This note examines the key
factors to consider.
Contents

Introduction.....................................................................................................................................................3
Why are T-BCs required? .............................................................................................................................. 3
What is a T-BC? ............................................................................................................................................ 3
Why test?..................................................................................................................................................... 3
Performance requirements ..............................................................................................................................4
ITU-T recommendations ............................................................................................................................... 4
What is Time Error of a T-BC? ....................................................................................................................... 4
Why is the Time Error of a T-BC Important? .................................................................................................. 4
G.8273 test bed............................................................................................................................................ 6
Calnex Integration ...........................................................................................................................................6
Accuracy ...................................................................................................................................................... 6
Usability ....................................................................................................................................................... 7
Time Error Tool ............................................................................................................................................ 7
Tests for a G.8273.2 T-BC .................................................................................................................................8
Conclusion .......................................................................................................................................................9

Executive Summary

LTE-A and TDD-LTE networks need accurate Phase sync, which can be delivered
via the IP/Ethernet Packet Core and Backhaul network using 1588v2 PTP.

The ITU-T has mandated that in order to do this, devices called Telecom Boundary
Clocks (T-BCs) or Telecom Transparent Clocks (T-TCs) should be used. This
document will focus on T-BCs.

A T-BC can be integrated into a Router/Switch or it can be an external device

these have performance limits equating to just 50 nanoseconds.

The major challenge to test & verify to 50 nanoseconds is that test equipment and
test beds have too much error and uncertainty.

Calnex has addressed this challenge with its Paragon-X product, which delivers:
o Integration a one-box solution guarantees maximum accuracy &
repeatability as well as minimum uncertainty & error
o Expertise Calnex is the industry-leader in 1588v2 and Sync testing.
This approach will become the de-facto performance test
o Readiness to ensure that the T-BCs are ready for field trials and
deployment
Introduction

Why are T-BCs required?

Wide-scale trials and deployments of FDD-LTE networks have taken place. FDD-LTE has a limit on how much
bandwidth it can provide users due to the limited availability of frequency spectrum. It is expected that mobile
operators will have to deploy LTE-A and/or TDD-LTE to meet the true bandwidth demands for 4G mobile.

LTE-A and TDD-LTE are different because the basestations need accurate Phase sync in addition to Frequency
sync. GPS can deliver this but it cannot be used at all basestations. As such, operators are looking to deliver
Phase sync using 1588v2 (PTP) via their IP/Ethernet Core and Backhaul networks.

The challenge is that most IP/Ethernet networks today have too much Packet Delay Variation (PDV) and
Asymmetry to deliver accurate Phase. For PTP to deliver the required Phase accuracy (1.5s for some radio
technologies), devices called Telecoms Boundary Clocks (T-BCs) have to be used in the network. In fact, they
are compulsory to build networks compliant to G.8275.1, the first ITU-T Telecom profile for Time/Phase.

What is a T-BC?
A T-BC is a 1588v2 PTP device that recovers and re-generates the clock. The diagram below shows how the BC
effectively reduces network PDV, thereby helping the end Slave-clock recover Phase more accurately. In the
first instance there are more devices between the Master and Slave so more PDV and Asymmetry. In the 2nd
instance, there is effectively one set of equipment and links between each Master and Slave because the T-
BCs each have a Slave and Master.

Fig.1 - Networks without (Top) and with (Bottom) T-BCs

T-BCs can be hardware- integrated into an existing Router/Switch or it can be an external device (sometimes
called an Edge Grandmaster). If built into the Router, the PTP packets are terminated and re-generated by the
Router. If it is an external BC, the PTP packets are passed to the external device for clock recovery & re-
generation then back to the Router/Switch.

Why test?
A T-BC has performance requirements dictated by what a network needs. This is explained in the next section.
Therefore, to prove compliance to the spec requirements, the T-BCs performance needs to be measured. The
standard measurement for this is called the T-BC Time Error. Also testing different Boundary Clocks allows an
operator to compare the performance of different equipment and different options (T-BCs integrated into
Router/Switch) or External T-BC.

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 1588v2 PTP Boundary Clocks Conformance Testing

Performance requirements

ITU-T recommendations
ITU-T G.8273.2 will specify Timing Characteristics of Telecom Boundary Clocks.The standard is progressing
towards ratification and there is acceptance that the constant Time Error (cTE) is going to be 50ns for a T-BC.
This will present a major challenge to equipment suppliers and an even bigger challenge to test equipment
suppliers who should be aiming for a 10x better performance goal for measurement.

Fig. 2 ITU-T Standards Related to Frequency and Phase delivery using PTP (July 2013)

What is Time Error of a T-BC?

The Time Error of a T-BC is the difference between a local clock (at T-BC egress) and a reference clock (usually
the reference to the Grandmaster). In essence it is the measure of the accuracy or quality of a T-BC.

Why is the Time Error of a T-BC Important?

If the mobile basestations needs Phase sync to 1.5s, this means the network (from the Grandmasters
reference to the basestation) has a Time Error budget (or a limit) of 1.5s. This is represented in G.8271.1 and
is shown in Fig.3, which breaks the budget down for each part of the network, based on the use of full on-path
support i.e. T-BCs at every node.

This network Time Error budget has fixed and time-varying components. The fixed component is called
Constant Time Error (cTE) and comes from Link asymmetries and Node (T-GM, T-BC, T-TSC) asymmetries. The
time-varying component is called Dynamic Time Error (dTE) and comes primarily from Packet Delay Variation
(PDV) caused by router queues, etc. The tests in this document describe how to measure the Constant Time
Error and Dynamic Time Error of a T-BC.

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 1588v2 PTP Boundary Clocks Conformance Testing

Critically, the allocated Constant Time Error component for a chain of T-BCs and a Slave according to G.8271.1
is 550ns. Up to ten T-BCs are allowed, meaning each T-BC would be allowed to contribute a maximum of 50ns
constant Time Error. In the case where a T-BC can only deliver, say 100ns, then the number of nodes allowed
would then reduce to five. So it is vital to measure and verify the cTE of a T-BC and to do this accurately.

In the context of these Time Error budgets, the accuracy to which the T-BC can be tested is critical. In other
words, the primary requirement for the test equipment & the test setup is to minimise error.

Figure 3 - Network budgets for Time error

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 1588v2 PTP Boundary Clocks Conformance Testing

G.8273 test bed

The T-BC function is defined in ITU-T G.8273.2 for use in the transfer of phase. G.8273.2 also outlines the test
bed below to measure Time Error (defined in ITU-T G.810).

Fig. 4 ITU-T G.8273.2 test bed to measure T-BC

The central issue in using the above test bed to measure a limit of 50ns is characterization, control and
repeatability of the delays associated with all of the reference and signal paths.

Using external equipment as part of the test bed and interconnecting it all can create a test environment with
excessive error. Added to this are the usability and repeatability of the test system. Grandmaster clocks and
real slaves are not designed to be part of a test bed and the whole thing can take weeks just to set up.

To run the above test set up with reliable test results is a major challenge. At best, the system may provide
results but there is limited confidence that the 50ns T-BC limit is truly being verified..

Calnex Integration

Accuracy
In Calnexs view, the required accuracies can only be achieved by integrating the significant elements of the
test bed into one test instrument. Only then can all internal delays be accounted, with measurement planes
aligned to enable accurate measurements
for reliable G.8273.2 compliance testing.

A significant part of Equipment &

Cabling (delay) uncertainty removed
Accuracy & repeatability achieved
G.8732.2 compliance assured

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 1588v2 PTP Boundary Clocks Conformance Testing

Usability
Integration brings major benefits for
usability. The Calnex Paragon-X offers
an optional, integrated emulation of a
PTP Master and Slave. This is easy to set
up as shown in the user interface on the
left. These functions are entirely
additional to the existing packet
impairment and packet
timing/recovered clock capture
functions providing a ONE-BOX
solution to measure PTP.

Time Error Tool

Comprehensive ITU-T defined Time Error analysis is provided by the built in Time Error tool. Results for both
forward and reverse directions along with both constant and dynamic Time Error mean that Boundary Clocks
can be fully characterised quickly, accurately and easily.

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 1588v2 PTP Boundary Clocks Conformance Testing

Tests for a G.8273.2 T-BC

Output Limit,
Test Objective Test method 1
PTP and 1pps

a) Apply stable time reference to DUT PTP input. cTE 50ns

Time Error Generation 2
With stable input references, measure the b) Repeat with/without a stable SyncE reference supplied to
dTE G.8262 wander
(noise generation: inherent noise produced by the internal clock. DUT. Generation MTIE/TDEV
G.8273.2, Section 7.1) 3
masks.port.
c) Repeat with/without congestion traffic on DUT output

PTP to PTP:
5
a) Apply sine wave PDV of 300ns amplitude to
Measures how time error on the input is the PTP input at 0.01 and 1Hz. >12dB attenuation at 1Hz,
transferred to the output. b) Repeat with/without stable SyncE reference relative to 0.01Hz
supplied to DUT. cTE input cTE + 50ns
Time Error Transfer Normally used as a check on the filter c) Repeat with/without a 750ns constant time
bandwidth of the clock. For a G.8273.2 clock, error applied to the PTP input.
6
(G.8273.2, Section 7.3) this is nominally 0.1Hz.
4

SyncE to PTP:
The test must also verify that any constant a) Apply stable time reference to the PTP input. Limit TBD.
time error on the input is not amplified.
b) Apply sine wave wander to the SyncE input of DUT at
0.01Hz and 1Hz, amplitude 2sec and 0.25sec
8
respectfully.

PTP only:
7
a) Apply sine wave PDV of 300ns amplitude to the PTP input
at 0.01 and 1Hz.
b) Repeat with/without stable SyncE reference
supplied to DUT.
c) Repeat with/without a 750ns constant time
Measures whether the clock can maintain the error applied to the PTP input.
8

network limits at the output with maximum

noise input at the input. SyncE only:
cTEDUT.
Apply stable time reference to the PTP input of the input cTE + 50ns
Time Error Tolerance 9
The test must be carried out with noise on Apply sine wave wander of 2us, 0.01 Hz to the SyncE input. dTE + noise
dTE input
(G.8273.2, Section 7.2) both the PTP and SyncE inputs. gen spec.
Combined:
Tests should also be repeated in the presence a) Apply sine wave PDV to the PTP input and
of a constant time error. sine wave wander to the SyncE input
simultaneously.
b) Apply sine wave PDV to the PTP input and
frequency offset of 16ppb to the SyncE input
simultaneously.
c) Repeat with/without a 750ns constant time
10
error applied to the PTP input.

a) Change clock class and prove best clock

Transients and selected.
Holdover Phase Transient 400ns
Measure the transient caused by a switch b) Mark clock DNU and prove alternate clock
(G.8273.2, Section 7.4, between PTP masters selected. (G.8271.1 budget, Table
plus Annex B, Appendix VI.1)
1) c) Repeat with/without stable SyncE
reference.

1
It is assumed that the 1pps should track the PTP output closely, and hence the same limits are used for both throughout this table. It is
important to test both to verify the 1pps is an accurate reflection of the PTP performance.
2
The use of SyncE is optional; therefore tests should be repeated without a SyncE input to verify that the local oscillator is capable of
meeting the specifications.
3
With no current standards definition, used G.8262 (SyncE) wander generation limit here, because the BC is likely to contain a similar
local oscillator.
4
Discussions in ITU-T have suggested this could vary between 0.1 and 0.05Hz.
5
300ns derived from G.8271.1 budget (Table VI.1): 100ns PRTC, plus 200ns random/SyncE
6
750ns derived from G.8271.1 budget (Table VI.1): 50ns/BC, plus 250ns link asymmetry.
7
300ns derived from G.8271.1 budget (Table VI.1): 100ns PRTC, plus 200ns random/SyncE
8
750ns derived from G.8271.1 budget (Table VI.1): 50ns/BC, plus 250ns link asymmetry.
9
Max sine wave wander that fits below the G.8261 Option 1 mask
10
750ns comes from G.8271.1 budget (Table VI.1): 50ns/BC, plus 250ns link asymmetry.

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 1588v2 PTP Boundary Clocks Conformance Testing

Conclusion
Boundary Clocks (T-BCs) are an essential part of successful roll-out of LTE-A and TDD-LTE. These have to be
tested to a very stringent limit of 50 nanoseconds.

In order to achieve the required accuracies, it is essential to consider the test setup. It is the Calnex view that
for Time Error measurement, it is necessary to integrate as much of the test bed as possible. Only then can the
accuracies be achieved to meet the new G.8273.2 compliance limits.

Such integration is also vital in other network devices such as Transparent Clocks (T-TCs).

Innovation by Calnex enables todays testing requirements to be made easily and reliably, saving on critical
test times, and ensuring reliable results.

For more detail including an accompanying video highlighting the market leading integration test
methodology, please visit www.calnexsol.com.

Calnex Solutions Ltd

Herkimer House
Linlithgow EH49 7SF
United Kingdom
tel: +44 (0) 1506 671 416
email: info@calnexsol.com

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