Performa for submission of proposal under

INDUSTRY-ACADEMIA FACULTY DEVELOPMENT PROGRAMME

DETAILS OF THE ACADEMIC PARTNER

Name of the institute
Address of the Institution
Title of the Program
Program intended for
Name of the Program
Coordinator
Designation
Department
Research Area and
Specializations
No. of Publications/Patents
Teaching Experience
Industrial Experience, If any
Broad Area of the Proposal
Duration of the Program
Sessions per day
Proposed dates for the
program(Provide 3 different
dates)
Total number of participants
anticipated
Signature of the Program
Coordinator
JSS Academy Technical Education
Uttarahalli-Kengeri Main Road,
Srinivasapura, Bangalore-60.
Email: info@jssateb.ac.in
Telephone:- 28602565,2575,3425,3702
Fax:- 080-28603706
Internet of Things(IoT)
To Enhance Recent Technical Skills in Staff Members
Dr. B. G. Shivaleelavathi
Professor
Electronics & Communication Engineering Dept.,
Power Electronics & Drives.
16 publications
28 Years
--
Real Time Embedded Systems
4 days
4 Sessions per day
5th, 6th, 7th and 8th Dec 2016
26th, 27th, 28th, and 29th Dec 2016
16th, 17th, 18th and 19th Jan 2017
50 Nos.
(Dr. B. G. Shivalelavathi)

DETAILS OF THE INDUSTRIAL PARTNER

Name(s) of the Industry FOUNDATION FOR INNOVATION AND

COLLABORATIVE EDUCATION(FICE)-Intel

Address F-2, LXY Aura, 99D, KHB Colony, 5th Block, Koramangala,
Bangalore-560095
 Email: info@fice.in
Telephone: (080) 41751855/56
Fax:-
Website Address Website: http://www.fice.in
Name(s) of the Contact Person Pradeep. G
9980136933

Designation Associate Vice President

FICE- Intel Program.

Technical Expertise Embedded systems and IoT

Financial Commitment, if any -----
Role of the Industrial Partner(s) To drive latest technology and concepts to academicians
Attach copy of letters received from participating industry showing intent finance commencement
etc.
Specific Field of the Proposal:

1) Real Time Embedded Systems and IoT for Real time applications.
2) Designing complex signal processing applications using Intel Gelileo processor
Brief Summary of the Proposal:

This FDP is an initiative program enabling the teaching faculty towards enhancing the
effectiveness of their teaching - learning process on the latest technology, bringing in the practical
application perspective and practices in teaching/ learning pertaining to the present technology.

Through this program we bring experts from the relevant domain who share their experience and
impart the practical hands-on to the participants starting from the first principles in order to bridge
the concepts of the practices.

The faculty after attending the 4 days FDP will train students, help them develop prototypes and
nurture the same to project. The students may consider this as their final year innovative project.

FICE has worked with Intel Corporation and faculty at the Indian Institute of Science, Bengaluru.
We believe that the faculty will be immensely benefited by availing the opportunity to attend the
FDP.

In the proposal, we are providing hands on training on Intel Galileo which as higher capabilities.
Galileo can be the platform for working projects on Internet of Things (IoT).

The proposal talks about 4 days of lecture series and rigorous hands-on training for faculty
followed by certification from Intel and FICE.

Objectives:

1)To bridge the Gap between industry and academia.

2)To build the relevant technical skills in faculty in the Latest Technology.

3) Nurture the students to work on the present technology industrial standards.

Project Impact-Expected outcome:

To impart the IoT skills to faculty so that they can:

Create large pool of highly skilled people, mostly developers and engineers, to work on
IoT.

These developers will create the ecosystem that will produce and sustain the Internet of
Things which can then be used by people for better lives (work on projects for
agriculture/smart city/smart village/smart cars/smart homes).

Level of activity (Regional/National/International) and target audience:

National Level:
Target audience:- Faculty from various Engineering Colleges, Research Scholars, Industry
Professionals, .

Concepts expected to evolve for Project Proposal Development

1. Concepts of Communication on Real Time Embedded systems.

2. Hardware concepts for Real Time Embedded systems implementation.
3. Concepts of Signal processing.
4. Concepts of developing software modules for Real Time Applications.
5. Project based learning.

Programme details
Date Time Activity Venue Infrastructural
requirements
and availability
Day 1: 9:00am Key note address:
To Lecture 1, Lecture 2: Seminar Seating
5th, Dec 2016
5:30pm Seminar hall: hall 1 arrangement for
26th, Dec 2016 Research 75 persons,
Lecture 3, 4: lab/ VLSI 50 computers,
16thJan 2017
Demonstration in Lab LCD projector.
Lab/hands on in lab

Demonstration in lab
Day 2: 9:00am Lecture 5, Lectur6 Library Seating
To 3:Seminar hall Seminar arrangement for
6thDec 2016
5:30pm hall 75 persons,
27th, Dec 2016 Lecture 7, 8: Research 50 computers,
Demonstration in lab/ VLSI LCD projector
17thJan 2017
Lab/hands on in lab Lab

Day 3 9:00am Industry visit to

To Wipro/Cisco/FICE/BOS Bangalore Transport will
5:30pm CH/ARM/General be arranged by
Electric institute.
Day 4: 9:00am Lecture 9, Lecture 10 Library Seating
To Seminar hall Seminar arrangement for
7th Dec 2016
5:30pm hall 75 persons,
28th Dec 2016 Lecture 11, 12: Research 50 computers,
Demonstration in lab/ VLSI LCD projector
18th Janc 2017
Lab/hands on in lab, Lab
Valedictory function
Resource Persons expected to participate
Name Designation Organization Activity
Pradeed .G Associate Vice INTEL-FICE Inauguration Keynote address
President Program
Raghav Ankur National Manager- INTEL-FICE Lecture 1: Embedded Linux and Intel
Technical Program Galileo- project case studies, platforms and
various IOT applications

Suryender Sharma Asst. Manager- INTEL-FICE Lecture 2 (Lab): Setting up the Galileo
Tech support Program Board and the Arduino environment

Raghav Ankur, National Manager- INTEL-FICE Lecture 3: Accessing Linux terminal using
Technical Program virtual serial/Ethernet interface like
PUTTY/Tera term (commands, utilities and
shell )

Raghav Ankur, National Manager- INTEL-FICE Lecture 4: Programming using Arduino API
Technical Program and its role in building embedded
applications

Suryender Sharma Asst. Manager- INTEL-FICE Lecture 5 (Lab): Interfacing various

Tech support Program Digital/Analog Sensors (GPIO, PWM,
Analog)

Raghav Ankur, National Manager- INTEL-FICE Lecture 6: Serial communication protocol

Technical Program (UART/I2C)

Suryender Sharma Asst. Manager- INTEL-FICE Lecture 7 (Lab):Case Study: Data logging
Tech support Program using SD library

Suryender Sharma Asst. Manager- INTEL-FICE Lecture 8 (Lab): Programming GSM-GPRS

Tech support Program Shields and related case studies

Suryender Sharma Asst. Manager- INTEL-FICE Lecture 9 (Lab):Building IoT SD card

Tech support Program image and related components.

Setting up Networking (*Ethernet

and *Wi-Fi).

Raghav Ankur, National Manager- INTEL-FICE Lecture 10 (Lab): Embedded Linux based
Technical Program Networking application demonstration using
POSIX based API

Raghav Ankur, National Manager- INTEL-FICE Lecture 11: 3-Tier architecture of IoT
Technical Program applications and related protocols

Raghav Ankur, National Manager- INTEL-FICE Lecture 12(Lab)Building IoT applications:

Technical Program
Thingspeak cloud management framework
for data logging and data visualization
Similar event organized by the Institute earlier, if any.

Title of Subject Date Level Name of Grants received

the from external by funding
activity to (Regional/National/ body agency (Rs.)
International) involved, if
(latest any
first)

Workshop Advanced 5 days National Tenet Rs.1,38,000/-

on GNU Communication 27th Technetronics finance approved
Radio and June to and from JSSMVP.
Software 1st Academic
defined July Organization
Radio 2016

Workshop Communication 3days National Texas Rs. 71,657/-

on Signal, Instruments
Image 22nd to Reva ITM Funded by the
24th National Organization-JSS
processin
June Instruments Mahavidhyapeeta,
g & SDR
2015 Tech Labs Mysore.
using Lab
View

FDP on VLSI Design 3 days National Corporate Rs. 71,657/-

Advance trainers from
VLSI 16th to Cadence Funded by the
18th Design Organization-JSS
Design
July Systems Mahavidhyapeeta,
Using
Cadence 2014 Mysore.
Tool
Suite

FDP on Embedded 02 National Resource Funded by the

Low Systems Days Persons from Organization-JSS
power Texas Mahavidhyapeeta,
4th & Instruments.
Embedde Mysore.
5th TI university
d system Programs.
using March
Cranes
MSP430 2013
International
limited.

Budget Estimates
 Budget Contribution External
Anticipated
Head of Expenditure by Organizing Sponsorship
Expenditure s
Institute
(Industry)
Travel and Honorarium for Resource 60,000/- ------
Persons

TA & Accommodation (outstation) and 1,00,000/- 30,000/- ------

Food for Participants

FDP preparation and arrangements 40,000/- ----- ------

Miscellaneous 30,000/- ------ -------

Total 2,30,000/- 30,000/- ------

Details of previous grants awarded to the Institute under different schemes of VGST in the
last three years.

Schem Name of the Amount Sanctioned Funds Utilization Certificate

e coordinator sanctioned letter details Utilization details/Reason for non-
position as submission of Utilization
on today Certificate

VTU- Dr. Rathna, Rs. 2 lakhs VTU/A7/2011- 2 lakhs UC submitted

VGST Professor. 12/8161,
5 days Dr. Mahesh, dtd.8/10/2011 Ref:JSSATEB/Chemistry/
Assoc. 2012-13/592
FDP
Professor. VTU/Aca/2011-
2012/A-9/9459. Dated:27/06/2012
Dtd.17/11/2011

CISEE Dr. Mahesh, 30lakhs VGST/CISEE/ 01/01/2015 1. UC submitted ref.

Assoc. Prof. GRD-326/2014- JSSATEB/VGST-
(3 and Head, 15 Rs. 10 CISEE/Chemistry/201
years) Chemistry lakhs 5-2016/1814,
Dept., Dated released dated. 6/01/2016.
JSSATEB 01/1/2015 2. Revised UC submitted
ref.
JSSATE/Chemistry/V
GST-CISEE/2016-
17/823.
Dated.26/07/2016
By signing this certificate, I/We undertake to
 Abide by all the rules/regulations regarding utilization of amount that may be granted to the
institute.
Submit detailed reports about grant utilization.
Submit utilization certificate duly authenticated by CA at the time of submitting the report.
Return full/partial unutilized grant amount to KSTePS account.

Note:
Faculty Development Programme should be organized within 6 months after receiving the grant in
collaboration with industries. The maximum budget allowed for each FDP is Rs.2.00 lakhs from
VGST.

(Dr. B. G. Shivaleelavthi) (Dr. Mrutyunjaya V. Latte)

Name And Signature Of Name And Signature Of The Principal
The Programme Coordinator

Place: Bengaluru

Date:

ANNEXURE IV(a)
SCHEDULE OF FACULTY DEVELOPMENT PROGRAMME FOR
ENGINEERING COLLEGE (FDP-ENGG) DURING THE FY: 2016-`17
Title of the proposed program under FDP: Internet Of Things (IOT)
Venue: Seminar Hall1, Academic Block 1/Library Seminar Hall Academic Block2
Day 1: 5th, Dec 2016 / 26th, Dec 2016 / 16thJan 2017
TIME PROGRAMME

9.00 am 10.00 am Inauguration

10.00 am 11.30 am Lecture 1: Embedded Linux and Intel Galileo- project

case studies, platforms and various IOT applications

by Raghav Ankur, National Manager-Technical INTEL-

FICE Program

11.30 am 11.45 am Tea/Coffee Break

11.45 am 01.15 pm Lecture 2 :

Setting up the Galileo Board and the Arduino

environment.

by Suryender Sharma, Asst. Manager- Tech support

INTEL-FICE Program

1.15 pm -2.15 pm Lunch Break

2.15 pm 3.45 pm Lecture 3(lab):

Accessing Linux terminal using virtual serial/Ethernet

interface like PUTTY/Tera term (commands, utilities
and shell )

by Raghav Ankur, National Manager-Technical INTEL-

FICE Program

3.45 pm 4.00 pm Tea/Coffee Break

4.00 pm 5.30 pm Lecture 4 :

Programming using Arduino API and its role in building

embedded applications

by Raghav Ankur, National Manager-Technical INTEL-

FICE Program
Day 2: 6thDec 2016 / 27th, Dec 2016 / 17th Jan 2017

TIME PROGRAMME

10.00 am 11.30 am Lecture 5:

Interfacing various Digital/Analog Sensors (GPIO,

PWM, Analog)

by Suryender Sharma, Asst. Manager- Tech support

INTEL-FICE Program

11.30 am 11.45 am Tea/Coffee Break

11.45 am 1.15 pm Lecture 6:

Serial communication protocol (UART/I2C)

by Raghav Ankur, National Manager-Technical

INTEL-FICE Program

1.15 pm -2.15 pm Lunch Break

2.15 pm 3.45 pm Lecture 7 (Lab):

Case Study:Data logging using SD library

by Raghav Ankur, National Manager-Technical

INTEL-FICE Program

3.45 pm 4.00 pm Tea/Coffee Break

4.00 pm 5.30 pm Lecture 8 (Lab): Programming GSM-GPRS Shields

and related case studies

by Suryender Sharma, Asst. Manager- Tech support

INTEL-FICE Program

Day 3:, 7th Dec 2016 / 8th, Dec 2016 / 18th Jan 2017

Name(s) of proposed Industries / R & D Institutions to be visited:

TIME PROGRAMME

Intel-FICE industry visit program.

9.00 am 5.30 pm The timings of lecture, lunch break etc., can be arranged based
on the convenience of the collaborating/ organizing Industries
/Institutions.
Day 4: 8th Dec 2016 / 29th Dec 2016 / 19th Jan 2017

TIME PROGRAMME

9.30 am 11.00 am Lecture 9:

Building IoT SD card image and related

components.
Setting up Networking (*Ethernet and *Wi-
Fi).
by Suryender Sharma, Asst. Manager- Tech support
INTEL-FICE Program

11.00 am 11.15 am Tea/Coffee Break

11.15 am 12.45 pm Lecture 10: Embedded Linux based Networking

application demonstration using POSIX based API

by Raghav Ankur, National Manager-Technical

INTEL-FICE Program

12.45 pm 1.30 pm Lunch Break

1.30 pm 3.00 pm Lecture 11(Lab): 3-Tier architecture of IoT applications

and related protocols

by Raghav Ankur, National Manager-Technical

INTEL-FICE Program

3.00 pm 4.30 pm Lecture 12(Lab)Building IoT applications:

Thingspeak cloud management framework for data

logging and data visualization

by Raghav Ankur, National Manager-Technical

INTEL-FICE Program

4.30 pm 5.30 pm Valedictory Function & High Tea

ANNEXURE IV(b)
 VGST FDP - ENGG: 2016-17
ESTIMATE OF EXPENDITURE

Sl. Amount
Particular/Head
No. in Rs.

1 Travelling Allowance for outstation participants including 25,000/-

to and fro and internal/local transport

2 Food and Accommodation (wherever applicable) for participants 46,000/-

3 Travel, Honorarium & Food [Honorarium Rs. 2500 per talk (1 hours)] 60,000/-

4 Folders, Pens, Work books, Stationary, Badge, Brochures, Certificate, Resource 10,000/-
Material for 50 Persons @Rs. 200 per person

5 Inauguration, Valedictory function: Banner, Invitation, Publicity, Media, Courier, 20,000/-

Postal, Telephone, Documentation & Coordination Expenses.

6 Contingency fund 10,000/-

7 Local transport to Industrial Visit & Coordination 15,000/-

8 Honorarium to support Staff @ Rs. 500/day for 3 persons for 4 days (500x3x4 6,000/-
days)

9 Honorarium for the Chief Co-ordinator of FDP 8,000/-

2,00,000/-
TOTAL AMOUNT ALLOCATED FOR ORGANIZING 4 DAYS FDP

PS:
(1)Minimum participants shall be 50, out of which 40 shall be from other colleges.
(2)Only 10% of re-appropriation in the Estimated Expenditure under each head is allowed by
VGST for organizing FDP.
(3)Air fare for Resource persons is not allowed from VGST grants. However, this can be
arranged through grants from Parent organization or External agencies.
(4)Institutions and Industrial support is encouraged besides VGST grants.
 ANNEXURE V

Applicant Declaration Letter

1 VGST PROGRAMME VGST FDP - ENGG: 2016-17

2 Period of the One Year Two Years Three Years

VGST Programme

4 COLLEGE/ Institution JSS Academy of Technical Education,

Address
JSS Campus, Uttarahalli-Kengeri Road.

Bangalore 560060

5 DEPARTMENT Electronics and Communication Engineering

6 TOPIC/ TITLE Internet of Things-IoT

7 Applicants Name Dr. B. G. Shivaleelavathi

details Designation Professor

Contact 9986651890
number

I am aware of all instructions and directions indicated in Guidelines, Terms and Conditions
(GTC) present in the Concept Proposals of VGST.
If my proposal is selected by VGST, I undertake to utilize the VGST grant by strictly adhering to
the GTC of VGST.
If my proposal is selected by VGST and in case of my transfer/ retirement/ deputation/
termination from this Grantee Institution, I shall obtain NOC from VGST office by suggesting
another responsible faculty member as Programme Co-ordinator (PC), who belongs to the
grantee Dept. of this College/ Institution (Not applicable to SMYSR scheme).
If my proposal is selected by VGST, I shall procure the equipment within the allowed cost as
approved by VGST in the Budget Estimate (Both Non-Recurring & Recurring) within the
stipulated period by following due guidelines of KTTP Act.
If my proposal is selected by VGST, I shall obtain the VGST approval of the Budget Estimate
(both Non-recurring & Recurring) before utilizing the VGST grant.
If my proposal is selected by VGST, I will not procure any equipment which is not approved by
 VGST. If such procurement of Equipment/Item is made without the VGSTs approval, the
Programme Co-ordinator/College Management/ Grantee Institution will bear the cost of the
equipment/Item.
I shall not seek for further changes in the Original Budget Estimate (Both Non-Recurring &
Recurring) (as indicated in my Original Proposal) submitted by me to VGST.

____________________________

Name and Signature of

Passport Size
photograph of Applicant (with seal)
Applicant

Date: Place: