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Solar Energy 97 (2013) 155167
www.elsevier.com/locate/solener

An eective passive islanding detection method for PV single-phase

grid-connected inverter
Ku Nurul Edhura Ku Ahmad , Nasrudin Abd Rahim, Jeyraj Selvaraj, Ahmad Rivai,
Krismadinata Chaniago
UM Power Energy Dedicated Advanced Centre (UMPEDAC), Level 4, Wisma R&D University of Malaya, Jalan Lembah Pantai, 59990 Kuala
Lumpur, Malaysia

Received 4 December 2012; received in revised form 31 July 2013; accepted 12 August 2013
Available online 12 September 2013

Communicated by: Associate Editor Nicola Romeo

Abstract

This paper presented a low cost and eective passive islanding detection method for single-phase photovoltaic grid-connected invert-
ers. An analog circuit for over/under voltage protection is developed to ensure fast detection and no delay to system. An under/over
frequency circuit is also developed, for accurate and fast frequency detection with minimal external components. A new algorithm is
developed in a low-cost PIC18F4550. An improved disconnection time in the proposed method compared with that in the previously
developed method is an attractive solution for single phase grid connected inverters. The low cost, eective and minimal external com-
ponent count are the advantages. A prototype is developed and tested to demonstrate the performance and feasibility of the proposed
method. The experiment results veried that the proposed islanding detection method able to detect islanding operation eectively under
various load types, inverter output powers and quality factors.
2013 Elsevier Ltd. All rights reserved.

Keywords: Passive islanding; Distributed generation; Inverter

1. Introduction
Development for renewable energy sources produce low
pollution compared to the fossil fuels and nuclear genera-
tion system (Yu et al., 2008). The new paradigm of distrib-
uted generation (DG) thus gains technical importance and
creates business opportunities (Chowdhury et al., 2009). In
principle distribution generation is a small scale generation
unit that need to be installed to the load and also connected
to the grid for selling or buying energy purposes. One of
the most important criteria that need to be considered is
the islanding issue (Yu et al., 2010). The islanding
condition as specied in Recommended Practice for Utility
Interface of Photovoltaic (PV) Systems (2000), occurs when
Corresponding author. Tel.: +60 3 22463246; fax: +60 3 22463257.
E-mail address: edhura@gmail.com (K.N.E.K. Ahmad).
a portion of utility system that contains both load and dis-
tributed resources remains energized while it is isolated
from the remainder of the utility system. Such an undesir-
able event could potentially occur due to the circuit
tripping, accidental disconnection of the utility due to
equipment failure, human error, temporary disconnection
(for maintenance services) or uncommon network recong-
uration (Chowdhury et al., 2009; Yu et al., 2010). Integrat-
ing DG into utility is a major challenge to researchers. DG
could still be supplying local load demand while network is
already isolated from the main system. Existing methods
are still lacking, hence successful detection of islanding is
an ongoing challenge.
Two factors must be highlighted to better understand
the islanding phenomenon. The rst one is the available
standards that have been established for the grid connected
system. These standards addressed the issue of islanding as

0038-092X/$ - see front matter 2013 Elsevier Ltd. All rights reserved.
http://dx.doi.org/10.1016/j.solener.2013.08.011
156 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167

Nomenclature

PV photovoltaic APS active phase shift

DG distributed generation SFS Sandia frequency shift
NDZ none detection zone AFD active frequency drift
PCC point of common coupling RPEED reactive power export error detection
Qf quality factor PLCC power line carrier communication
LPS load parameter space T transmitter
PMS power mismatch space R receiver
In,a negative sequence current SPD signal produced by disconnect
OV/UV over and under voltage SCADA supervisory control and data acquisition
OF/UF over and under frequency Vpcc voltage at point of common coupling
PJD phase jump detection RMS root mean square
ROCOP rate of change of power output LED light-emitting diode
ROCOF rate of change of frequency IGBT insulated gate bipolar transistor
SMS sliding mode frequency shift DFT digital Fourier transformation
PWM pulse width modulation V grid voltage
MPPT maximum power point tracking f grid frequency
R resistor C capacitance
L inductance Qf quality factor

well as procedure for testing and qualifying DG system
(Chiang et al., 2010). The second feature is associated with
the so called Non-detection zone (NDZ) which can be
dened as the zone for which an islanding detection
method would fail to operate in time. NDZ is an evaluating
criterion of islanding detection methods. In principle, islan-
ding detection monitors changes in inverter output param-
eter or other system parameters that indicate islanding.
There are two types of anti islanding methods which are
the local and remote methods. The local methods can be
divided into passive and active. Passive islanding detection
detects changes in electrical parameters to determine the
occurrence of islanding (Chiang et al., 2010). The advanta-
ges of these passive techniques are their easy implementa-
tion (no additional controller), no degradation of PV
inverter power quality, and their inexpensiveness. The pri-
mary drawbacks are a relatively large NDZ and ineective-
ness in multi-PV inverter systems (Syamsuddin et al.,
2009). The most commonly used passive technique for
islanding detection are under/over voltage and under/over
frequency (OV/UV & OF/UF), phase jump detection
(PJD), voltage harmonic monitoring, current harmonic
monitoring, rate of change of power output (ROCOP)
and rate of change of frequency (ROCOF) Yu et al.,
2010; Llaria et al., 2011; De Mango et al., 2006; Freitas
et al., 2005; Redfern et al., 1993. Active techniques inject
a small disturbance at the PV inverter output to detect
islanding. The main advantage of these techniques is their
relatively smaller NDZ than that of passive methods. Their
main drawbacks are the possibly deteriorated output
power quality causing instability to the PV inverter and
normally require additional controllers which increased
the complexity of the method (Syamsuddin et al., 2009).
Active techniques developed include impedance measure-
ment (IM), sliding mode frequency shift (SMS) or active
phase shift (APS), sandia frequency shift (SFS) or active
frequency drift with positive feedback, and reactive power
export error detection (RPEED) Chowdhury et al., 2009;
Mohamad et al., 2011; Lopes and Huili, 2006. AFD
method varies the output current frequency through posi-
tive feedback. This method will inject a current with
slightly distorted in frequency into the PCC. Upon grid dis-
connection, the phase error between the PCC voltage and
the inverter current will be detected by the inverter, which
then tries to compensate by increasing the frequency of the
injected current until it exceeds the OF/UF limits. How-
ever, the performance of this conventional AFD method
is inecient and researchers are facing diculty in choos-
ing the suitable chopping fraction (cf) value to meet the
limit of harmonics. Hence, a novel AFD method (Jung
and Yu, 2007) with a periodic chopping fraction that devi-
ates from the frequency in an instant way from nominal
was proposed. Remote islanding detection techniques are
based on communication between utilities and PV inverter
units (Syamsuddin et al., 2009). This technique do not have
the NDZ, do not degrade PV inverter power quality, are
eective in multi-PV-inverter systems, but are expensive
to implement (especially in small systems), and have a com-
plicated communication technique for multi-PV inverter
systems. Common techniques that are communication-
based include power line carrier communication (PLCC),
signal produced by disconnect (SPD), and supervisory con-
trol and data acquisition (SCADA). In application, each
method has advantages and drawbacks. Among popular
reference standards for islanding are IEEE 929-2000, IEC
62116, IEE 1547, VDE 0126-1-1, and AS 4777.3-2005.
 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167 157

Table 1
Existing anti-islanding standards.
Quality factor, Qf Required islanding Normal frequency range, Normal voltage range,
detection time, t f (nominal frequency f0) V (% of nominal voltage V0)
IEC 62116 1 t<2s f 0  1:5 Hz 6 f and 85% 6 V 6 115%
f 6 f 0 1:5 Hz
IEEE 1547 1 t<2s 59:3 Hz 6 f 6 60:5 Hz 88% 6 V 6 110%
IEEE 929-2000 2.5 t<2s 59:3 Hz 6 f 6 60:5 Hz 88% 6 V 6 110%
Japanese standard 0 (+rotating Passive: t < 0.5 s active: Setting value Setting value
machinery) 0:5 s < t < 1 s
Korean standard 1 t < 0.5 s 59:3 Hz 6 f 6 60:5 Hz 88% 6 V 6 110%
VDE 0126-1-1 2 t < 0.2 s 47:5 Hz 6 f 6 50:2 Hz 80% 6 V 6 115%
AS4777.3-2005 1 t<2s Setting value Setting value

Table 1 shows all the standards having their own quality
factor (Q) value, the required islanding disconnection time,
and range of operational frequency and voltage (Yu et al.,
2010). According to IEEE929-2000 standard the quality
factor Q is equals to;
Q tanarccosinepf
The selected Q = 2.5 is equals to a power factor of 0.37.
As the power factor increases, Q decreases. Thus according
to IEEE929-2000, the test requirement that sets Q = 2.5
equals lines with uncorrected power factors from 0.37 to
unity and seems to cover all reasonable distribution line
congurations (Recommended Practice for Utility Inter-
face of Photovoltaic (PV) Systems, 2000). Meanwhile, Jap-
anese standard are proposing Q = 0 based on adding
rotating machinery while islanding test is being conducted
(Yu et al., 2010). Other than quality factor, disconnection
time is also important. The German VDE0126-1-1 stan-
dard has the strictest disconnection time limit which is less
than 0.2 s. Normal frequency and voltage range also are
crucial to determining islanding detection capability.
Australian standard AS4777.3-2005 requires nominal
frequency and voltage range to be set by manufacturer.
Steps to obtaining tripping values are: (1) determination
of under/over voltage and under/over frequency values
through gradual increase or decrease of voltage and
frequency until the device tested (the inverter) disconnects
from the variable ac supply, and (2) reading of the
over/under voltage or over/under frequency values at
which disconnection occurred. A criteria of acceptance
for over/under voltage is that the value at step (2) should
equal an under-voltage set point of 5 V; for frequency,
the value should equal an under-frequency set point of
1 0.1 Hz.
The primary objective of this paper is to propose a new
low cost and eective passive method for islanding detec-
tion of single-phase grid-connected PV inverter and to
compare between the proposed algorithm and existing
algorithm.
2. Research methodology
2.1. PV inverter system connected to grid
Fig. 1 is the block diagram of a typical single-phase grid-
connected PV inverter; here, it has PV arrays, DCDC
boost converter connected to two capacitors in series
(and functioning as maximum power point (MPP) tracker),
four switching devices connected in full bridge congura-
tion (S1S4) and presented as ideal switches, and a lter
inductor (Lf) ltering the current injected into the grid.
The power produced by the system is transferred directly
to the grid. Since grid voltage is uncontrollable, the sim-
plest way of controlling system operation is by controlling

Fig. 1. Single-phase grid-connected PV inverter.

158 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167

Fig. 2. The grid-connected PV inverter system with PIC 18F4550 microcontroller.

15V

R3
R1

LED
+
C1 R2 To Port
Grid RD6
- R1
Op
R1 Amp1
2W06 LM311

15V

R3

R1 LED
+
To Port
RD7
- R1
Op
Amp2
LM311

Fig. 3. Under/over voltage circuit.

the current owing into the grid. The injected current must
be sinusoidal and have low harmonic distortion (Rahim
et al., 2011; Rahim and Selvaraj, 2010).

2.2. Overall block diagram of the grid-connected PV inverter

with the proposed method +

Fig. 2 is the block diagram of the grid-connected PV

inverter system with PIC 18F4550 microcontroller for
islanding detection integrated with the main controller
for the inverter system. In this paper, the proposed low cost
and eective passive method is developed using microcon- Fig. 4. Zero-crossing detector circuit for under/over frequency detection.
troller PIC 18F4550. The controller handles the proposed
passive islanding of under/over voltage and under/over fre-
quency detection before the signals are sent to the main voltage circuit and send the signals as input to PIC18F4550
controller of the single-phase grid-connected inverter. The for under/over voltage detection. For under/over fre-
proposed method takes the grid voltage to the under/over quency, the proposed method detects zero crossing
 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167 159

Table 2
Parameters of the single-phase grid-connected PV inverter prototype.
Parameter Value
D1 RHRP30120 VRR = 1200 V, I = 30 A
S1S4 IGBT IRG4PH50UD VCE = 1200, Ic = 24 A
Filter inductor (Lf) 5 mH
Switching frequency 20 kHz

The islanding detection algorithm output from PIC

18F4550 is input to the main inverter controller through
GPI0A11, the input then used as a signal to turn o the
relay, disconnecting the inverter from the grid (see Figs. 3
Fig. 5. Falling edge of a square wave signal with the triggered interrupt. and 4).

2.3. The proposed under-voltage and over-voltage circuit

detection pulses and sends the signal as interrupt input to
PIC18F4550. These signals are used as conditional PIC 18F4550 was designed to read analog signals
detection in the islanding detection algorithm developed. between 0 V and 5 V, hence the under/over voltage circuit

Fig. 6. Flowchart of islanding detection.

160 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167

Table 3 Table 4
Load parameters of the simulation and experiment at Q = 2.5, and Load parameters of the simulation and experiment at Q = 1, 2, 2.5, and
P = 1 kW. P = 1 kW.
Types R (O) L C Quality factor R (O) L (mH) C (lF)
Pure resistor load 57.6 1 57.6 183.35 55.26
Resistorinductor load 57.6 73.33 mH 2 57.6 91.67 110.52
Resistorcapacitor load 57.6 138.13 lF 2.5 57.6 73.33 138.13
Resistorinductor-capacitor load 57.6 73.33 mH 138.13 lF

was designed to not exceed that range. In this work, a 240

6 V transformer was connected to the utility source. A rec-
tier transforms the lower AC voltage into DC. Through
the addition of resistor R2 parallel with capacitor C1, this
circuit can convert a high voltage signal into a very stable
low DC voltage signal. The stable DC signal then act as
input to the under-voltage circuit which used the OpAmp1.
A 10 kO potentiometer is used as tuner for reference volt-
age Vref1. The DC voltage and reference voltage Vref1 are
compared, with OpAmp1 acting as comparator. OpAmp1
output is fed to RD6 as input signal to the microcontroller.
The same concept is applied to the over voltage circuit,
except that the location of the reference voltage is now at
the positive side of OpAmp2 and the stable DC voltage
now connects to the negative input of OpAmp2. This cir-
cuit was developed for accurate and fast detection of
under/over voltage without continuous calculation of the
grid voltage RMS as in the past method. Not only does
detection become very fast, there is no added delay.
2.4. The proposed under-frequency and over-frequency
circuit
This circuit is to ensure accurate and fast frequency
detection with minimal external components. Resistor R1
forces the voltage down. Resistor pair R2 is a voltage divi-
der, producing 2.5 V as reference voltage to Op Amp
LM311. The circuit output connects to RB0. Capacitor
C1 connects to the Op Amp output to act as noise lter
that gives the possibility to prevent noise in a simple and
cost eective way. It improves triggering of the interrupt
by reducing the noise in the low-voltage square-wave sig-
nals. As the square-wave signal is in phase with the grid
voltage, the falling edge will indicate very accurately where
the zero crossing is. This square wave signal will be the
input to interrupt routine INT0, making possible the
design of a zero-crossing-detection routine in an interrupt
routine and automatically making the detection fully inter-
rupt-driven. Fig. 5 shows a square-wave input signal and
the triggered interrupt.
2.5. Islanding algorithm
Fig. 6 shows the control algorithm of the proposed pas-
sive islanding detection, applied in PIC18F4550, which
processes the algorithm through C programming language.
PIC18F4550 collects analog inputs data from the under/
over voltage circuit through RD7 and RD6. There is a lter
in the programming algorithm to meet AS 4777.3-2005

Voltage sensor
PM6000
Current sensor
LAN Area
LeCroy
Oscilloscope

PC for PV Array Simulator PC for PM6000

R C L Inverter PV Array
Simulator
Programmable
AC source
GPIB and serial USB

(a)

Computer
PM6000

Oscilloscope
under and over
voltage circuit

under and over

frequency circuit

Inverter
RLC load

(b)
Fig. 7. (a) Islanding test and (b) the laboratory test equipment with the proposed passive islanding detection method.
 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167 161

Fig. 8. Simulation model of the islanding test circuit.

standard reconnection time. For frequency calculation, a
simple zero-crossing circuit is utilized. The square wave
produced by the zero-crossing detector has the same fre-
quency as the grid. By feeding the produced signal into
the RB0 of the PIC18F4550, the microcontroller is pro-
grammed to be a very accurate zero-crossing detector with
an interrupt-driven code.
Fig. 7 shows the PV grid-connected inverter hardware
prototype controller interface with the islanding detection,
implemented on PIC 18F4550 to validate the performance
of the proposed passive islanding detection algorithm.
Table 2 lists the prototype parameters of the single phase
grid-connected PV inverter. The hardware was tested under
various load conditions. Equipment such as PV array

Vgrid Vgrid
400 400
200 200
0 0
-200 -200
-400 -400
Vpcc Vpcc
400 400
200 200
0 0
-200 -200
-400 -400
Iinv*10 Iinv*10
100 100
50 50
0 0
-50 -50
-100 -100
0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2
Time (s) Time (s)

(a) (b)
Vgrid
400
200
0
-200
-400
Vpcc
400
200
0
-200
-400
Iinv*10
100
50
0
-50
-100
0 0.2 0.4 0.6 0.8 1 1.2
Time (s)
(c)
Fig. 9. Simulation result for islanding detection, at (a) Q = 1, (b) Q = 2, and (c) Q = 2.5.
162 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167

simulator, resistor-inductor-capacitor (RLC) load, pro-
grammable AC source, PM6000, and LeCroy Oscilloscope
were used. The test was conducted from 500 W to 2 kW
power output. In the following experiments, the grid-con-
nected inverter was controlled to generate balanced real
power with the load. Various load types were used to verify
the proposed islanding detection method. Table 3 lists the
load parameters of the experiments. The parameters of
the resistorinductorcapacitor (RLC) load were as
specied by the IEEE Std. 929-2000 (Recommended Prac-
tice for Utility Interface of Photovoltaic (PV) Systems,
2000) for testing islanding operation performance. IEEE
Std. 929-2000 states that a non-islanding inverter must shut
down within 2 s of grid disconnection for loads with a qual-
ity factor (Qf) equals to or lower than 2.5. The values for L
and C are calculated through this formula:
V2
P 2
R
R grid voltage and grid frequency at PCC (see Table 4).
L 3
Qf  x
 2
Qf
C L 4
R
Fig. 8 is a diagram of the PSIM model of the islanding
circuit.
3. Results and discussion
3.1. Disconnection time for dierent method and algorithm
To prove that the proposed passive islanding detection
has advantages over the implemented algorithm in
TMS320F2812 DSP in terms of disconnection times, the
corresponding comparisons were made on both passive
islanding methods. Low cost PIC 18F4550, compared with
ATMEGA and TMS320F2812 DSP with under/over volt-
age and under/over frequency islanding detection algo-
rithms, were compared. The circuit connections and
algorithms of the past methods are as in Syamsuddin
et al. (2009). The prototype of both methods monitored

Vpcc

400

200

-200

-400
Iinv*10

100

50

-50

-100

0 0.2 0.4 0.6 0.8 1 1.2

Time (s)

(a)
Vpcc

400

200

-200

-400
Iinv*10

100

50

-50

-100

0 0.2 0.4 0.6 0.8 1 1.2

Time (s)

(b)
Fig. 10. Simulation result for (a) RL load (b) RC load under islanding operation with Q = 2.5 and P = 1 kW.
 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167 163

Table 5
Disconnection times of the two methods.
Under voltage Over voltage Under frequency Over frequency
disconnection time (s) disconnection time (s) disconnection time (s) disconnection time (s)
ATMEGA and DSP based Could not be determined 1.2 2.1 52.5
algorithm
PIC 18F4550 algorithm 0.6 0.6 0.6 0.6

Fig. 11. Experiment results for R load under islanding operation, for (a) 25% (500 W), (b) 50% (1 kW), (c) 75% (1.5 kW), and (d) 100% (2 kW) inverter
output, with (M1) Vgrid, (M2) Vpcc, (M3) the inverter output current and (M4) load current.

The disconnection time of PIC18F4550 was much faster
than that of ATMEGA and TMS320F2812. The cost of
design and implementation for the proposed method were
also much less. The disconnection times were validated
according to AS 4777.3-2005 standard. Table 5 compares
the disconnection times.
As the table shows, the proposed method is much faster
and more stable than the past method (very unstable).
Although over-voltage disconnection time of the past
method passed the less-than-2-s standard, the proposed
method enabled much faster disconnection. From Syam-
suddin et al. (2009), this method used TMS320F2812
DSP for reading the grid voltage at the sensor signal
through the ADC and calculates the RMS voltage value
for under/over voltage disconnection. This may add some
lagging to the systems when detecting under/over voltage.
The proposed circuit and algorithm aim to correct the
problem.
3.2. Simulation results
Simulations were performed using PSIM system. The
DC voltage source was 400 V, the grid voltage 240 V, the
grid frequency 50 Hz, and the output lter inductance
5mH. The inverter was designed for 1.4 kW power output.
The RMS current injected into the grid was 6 A. The main
parameters of the simulation were as those of the experi-
ments. The inverter was loaded by a parallel RLC circuit
164 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167

with quality factors 1, 2, and 2.5. Fig. 9 shows the point of
common coupling voltage Vpcc, the inverter current and
voltage, and grid current and voltage ideally when the
inverter is tripped o.
Fig. 10(a) shows the simulation result for RL under
islanding operation with 1 kW inverter output power.
The inverter output current is almost the same for both
simulation and experiment results (see Fig. 10(a) and see
Fig. 12(a)). From the simulation result for RL load under
islanding condition, the value of the maximum inverter
output current before inverter is tripped o is 7.08 A and
5.7 A from the experiment (see Fig. 12(a)). Fig. 10(b) shows
the simulation result for RC under islanding operation
with 1 kW inverter output power. The Vpcc voltage is
almost the same for both simulation and experiment results
(see Fig. 10(b) and 12(b)). From the simulation result for
RC load under islanding condition, the value of Vpcc volt-
age before inverter is tripped o is 160 V and 216 V from
the experiment (see Fig. 12(b)).
3.3. Experiment results
The grid system was rst connected to the inverter and
then removed to create islanding. Fig. 11 gives the dierent

Fig. 12. Experiment results for (a) RL load, and (b) RC load under islanding operation, with (M1) Vgrid, (M2) Vpcc, (M3) the inverter output current
and (M4) load current.
 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167 165

Fig. 13. Experiment results for RLC load under islanding operation, at (a) Q = 1, (b) Q = 2, and (c) Q = 2.5, with (M1) Vgrid, (M2) Vpcc, (M3) the
inverter output current and (M4) load current.

Fig. 14. Experiment results for RLC load under islanding operation, at Q = 2.5 with (M2) the inverter output current, (M3) load current.
166 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167

Watt Inverter starts to deliver power

Inverter power

Load power

load
power
grid
power
inverter
power
Grid power
seconds

Fig. 15. The inverter comes on-line and gradually increases its output to 1 kW.

Table 6 grid values. It has been proved that the larger the power
Detection times for the RLC load with Q = 2, as taken by PM6000 imbalance (DP and DQ in local generation and consump-
Universal Power Analyzer.
tion in the islanded system prior to grid disconnection),
Timestamp Channel Arms Watt the larger the variations are in the frequency of the voltage
20130130155137.30 B Load 5.00 1091.88 and voltage at the PCC. Therefore, standard under/over
20130130155137.30 C Grid 2.51 182.38 frequency and under/over voltage protections are success-
20130130155137.30 D Inverter 5.35 1283.13
20130130155137.60 B Load 0.00 0.00
ful in preventing islanding in system with large enough
20130130155137.60 C Grid 0.00 0.00 power imbalances. The islanding condition for the experi-
20130130155137.60 D Inverter 0.00 0.00 ments conducted was made to have the smallest power
imbalance possible, i.e., the worst-case scenario. Fig. 13
shows the experiment results for RLC load under islan-
Table 7
ding, at Q = 1, Q = 2, and Q = 2.5. In the following exper-
Detection times for the dierent quality factors.
iments, the grid-connected inverter will be tripped o
Capacity inverter Quality factor of the RLC Detection
21.25 ms (Q = 1), 24.8 ms (Q = 2) and 55.7 ms (Q = 2.5)
output Load time
after the grid is disconnected. From all the following exper-
1 kW 1 21.25 ms
iments (see Fig. 13), the inverter (Vpcc) briey swings up to
1 kW 2 24.8 ms
1 kW 2.5 55.7 ms slightly more than + and  400 volt peak after the grid is
disconnected, and then shuts down. The detection time of
islanding operation may be dierent under dierent loads
Table 8 and dierent quality factors of RLC load. As Fig. 14
Response to abnormal voltages.
shows, (M2) and (M3), at inverter output 1 kW and R
Voltage (at PCC) Maximum trip time LC load with Q = 2.5, the inverter output current was
V < 120 (V < 50%) 6 cycles almost identical with the load current. This indicates the
120 6 V < 211 (50% 6 V < 88%) 120 cycles worst case for islanding detection, where the power-ow
211 6 V 6 264 (88% 6 V 6 110%) Normal operation
between the grid-connected inverter and the local load is
264 < V < 329 (110% < V < 137%) 120 cycles
329 6 V (137% 6 V) 2 cycles balanced.
Table 6 lists the disconnection times for when the grid
was disconnected until the inverter was tripped o. As
shown in Table 6 the disconnection time is 0.3 s (24.8 ms)
inverter outputs: 25%, 50%, 75% and 100% with pure resis- for RLC load with Q = 2. PM6000 Universal Power
tive load under islanding condition. The results allow con- analyzer was set to the minimum time setting available
clusion that the ratio of the inverters output and load for data recording (every 0.3 s). The detection time satises
consumption can aect the amplitude of the load voltage. the IEEE 929-2000 control standard, verifying that the pro-
Fig. 12 shows the experiment results for the RL and R posed islanding method is able to detect islanding eec-
C loads under islanding operation. In the following exper- tively. As shown in Table 6, the inverter current value
iments, the grid-connected inverter will be tripped o when immediately zeros out after the grid is disconnected (see
islanding is detected. Table 7).
Under islanding conditions, the magnitude and fre- According to IEEE Std. 929-2000 standard, the relation-
quency of the voltage at PCC tend to slide from the rated ship between the amplitude of the load voltage and the
 K.N.E.K. Ahmad et al. / Solar Energy 97 (2013) 155167
maximum trip time for determining the islanding condition
are shown in Table 8. All the experiment results show the
amplitudes of the local load (Vpcc) to have passed the fol-
lowing requirement.
The proposed method is shown to eectively and eort-
lessly detect islanding operation under dierent load types
and quality factors. As Fig. 15 shows, the inverter comes
on-line and gradually increases its output power to
1300 W. Fig. 15 shows the transition as the inverter power
increases and the grid transitions from delivering the load
power to negative. Note that the load power stays constant
during the transition period.
4. Conclusions
A low cost and eective passive method for islanding
detection of single-phase grid-connected inverter is pro-
posed. An analog circuit for under/over voltage protection
has been developed, to ensure fast detection with no added
delay. An under/over frequency circuit has also been devel-
oped, for accurate and fast frequency detection and with
minimal external components. A new algorithm is devel-
oped in a low cost PIC18F4550. The circuit topology, con-
trol algorithm, and operational principle of the proposed
method have been presented. PIC18F4550 optimized the
methods performance, which has improved the disconnec-
tion time of a past method. The inexpensiveness, eective-
ness, and minimal external component count are the
proposed methods advantages. Its performance and feasi-
bility has been tested and proven by a purpose-developed
prototype. The main improvements are the disconnection
times, eectiveness in detecting islanding under various
load types, inverter output powers and quality factors
and also cost down of the end product.
Acknowledgments
This work was supported by UMPEDAC (University of
Malaya Power Energy Dedicated Advanced Centre), a ag-
ship HICoE (Higher Institution Centre of Excellence) of the
Ministry of Higher Education, Malaysia and HIR Grant H-
16001-00-0000032 Campus Network Smart Grid System for
Energy Security. The authors thank all concerned.
167
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