library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity pancho is

port(

ck: in std_logic;

x: in std_logic_vector ( 1 downto 0);

z: out std_logic_vector ( 3 downto 0));

end;

architecture maria of pancho is

type estados is (s10,s8,s9,s1,s5,s4,s6,s2);

signal ep, es:estados;

begin

process (ep,x)

begin

case (ep) is

when s10=>z<="1010";

if x="00" then es<=s8;

elsif x="01" then es<=s2;

elsif x="10" then es<=s9;

else es<=s6;

end if;

when s8=>z<="1000";

if x="00" then es<=s9;

elsif x="01" then es<=s10;

elsif x="10" then es<=s10;

else es<=s10;

end if;

when s9=>z<="1001";

if x="00" then es<=s1;

elsif x="01" then es<=s8;

elsif x="10" then es<=s5;

else es<=s10;

end if;

when s1=>z<="0001";

if x="00" then es<=s5;

elsif x="01" then es<=s9;

elsif x="10" then es<=s10;

else es<=s10;

end if;

when s5=>z<="0101";

if x="00" then es<=s4;

elsif x="01" then es<=s1;

elsif x="10" then es<=s6;

else es<=s9;

end if;

when s4=>z<="0100";

if x="00" then es<=s6;

elsif x="01" then es<=s5;

elsif x="10" then es<=s10;

else es<=s10;

end if;

when s6=>z<="0110";

if x="00" then es<=s2;

elsif x="01" then es<=s4;

elsif x="10" then es<=s10;

else es<=s5;

end if;

when s2=>z<="0010";

if x="00" then es<=s10;

elsif x="01" then es<=s6;

elsif x="10" then es<=s10;

else es<=s10;

end if;

end case;

end process;

process (ck)

begin

if ck ' event and ck='1' then

ep<=es;

end if;

end process;

end maria;