VHDL

OBJETIVO GENERAL
Conocer las bases, fundamentos y estructura del lenguaje
para programación de circuitos

Gustavo Cerda Villafaña

FIMEE, U. de Gto.
correo: gcerdav@salamanca.ugto.mx
VHDL – Very high speed integrated circuit
Hardware Description Language
• La estructura básica es la ENTIDAD (ENTITY)

En la entidad hay dos componentes

principales:
•Declaración de la entidad
•Cuerpo de la arquitectura
Declaración de la entidad

• Código ejemplo de la declaración de una entidad

1 -- eqcomp4 es un comparador de igualdad de cuatro bits

2 entity eqcomp4 is
3 port (
4 a, b: in bit_vector(3 downto 0); -- a, b son las entradas
5 equals: out bit); -- equals es la salida
6 end eqcomp4;

a
equals

b
Declaración de la entidad

• Código ejemplo de la declaración de una entidad

1 -- eqcomp4 es un comparador de igualdad de cuatro bits

2 entity eqcomp4 is
3 port (
4 a, b: in bit_vector(3 downto 0); -- a, b son las entradas
5 equals: out bit); -- equals es la salida
6 end eqcomp4;
7
8 architecture dataflow of eqcomp4 is
9 begin
10 equals <= ‘1’ when (a=b) else ‘0’;
11 end dataflow;
CIRCUITOS PROGRAMABLES
• PALs (Programmable Array Logic) – Lógica de arreglo programable

Son circuitos construidos con compuertas NOR o AND

El circuito se puede configurar (programar) al romper las conexiones

· · ·
entradas

matriz matriz
AND productos OR

salidas
· · ·
CIRCUITOS PROGRAMABLES
• GAL16V8

Al segmento combinacional se le agrega

un segmento secuencial denominado
Output Logic Macrocell (OLMC)
 CIRCUITOS PROGRAMABLES
• Como trabaja un FPGA

Los FPGAs se construyen a partir de una célula

lógica básica que se multiplica cientos o miles
de veces.

Una célula lógica es básicamente una “lookup

table” (LUT), un flip-flop D y un multiplexor 2 a 1
LUT
(para pasarse el flipflop D si se desea.)
D
La LUT es una RAM pequeña con típicamente 4
entradas que puede implementar cualquier
compuerta lógica con hasta 4 entradas. Logic-cell
 CIRCUITOS PROGRAMABLES
• Como trabaja un FPGA

Cada célula lógica se puede conectar con otras

células lógicas mediante recursos de conexión y
con células de entrada/salida

LUT LUT
D D

LUT LUT D
D D D

LUT LUT
D D
CIRCUITOS PROGRAMABLES
• Arquitectura de un FPGA
CIRCUITOS PROGRAMABLES
• Arquitectura de un FPGA de Actel
Elementos de la entidad

• Declaración de la entidad (entity declaration)

• Puertos (ports)

• Modos (modes)

• Tipos (types)

• Operadores

• Arquitecturas

• Objetos de datos
Elementos de la entidad

Puertos (ports)

Un puerto representa un pin. Cada puerto debe tener un nombre, una

dirección o modo (mode) y un tipo de dato.
Elementos de la entidad

Modo (mode)

El modo describe la dirección en la cual se transfieren los datos de un

puerto

• in

• out

• buffer

• inout
Elementos de la entidad

Tipos (types)

Los tipos definidos por el estándar IEEE 1076/93 son

• boolean (FALSE, TRUE)

• bit (‘0’, ‘1’)

• bit_vector
Elementos de la entidad

Tipos (types)

Los tipos definidos por el estándar IEEE std_logic_1164

• std_ulogic
‘U’ – No inicializado
• std_logic ‘X’ – Forzar desconocido
‘0’ – Forzar 0
‘1’ – Forzar 1
‘Z’ – Alta impedancia
‘W’ – Desconocido débil
‘L’ – 0 débil
‘H’ – 1 débil
‘-‘ – No importa
Palabras reservadas en VHDL
abs operator, absolute value of right operand. No () needed.
access used to define an access type, pointer
after specifies a time after NOW
alias create another name for an existing identifier
all dereferences what precedes the .all
and operator, logical "and" of left and right operands
architecture a secondary design unit
array used to define an array, vector or matrix
assert used to have a program check on itself
attribute used to declare attribute functions
begin start of a begin end pair
block start of a block structure
body designates a procedure body rather than declaration
buffer a mode of a signal, holds a value
bus a mode of a signal, can have multiple drivers
base part of a case statement
component starts the definition of a component
configuration a primary design unit
constant declares an identifier to be read only
disconnect signal driver condition
downto middle of a range 31 downto 0
Palabras reservadas en VHDL
else part of "if" statement, if cond then ... else ... end if;
elsif part of "if" statement, if cond then ... elsif cond ...
end part of many statements, may be followed by word and id
entity a primary design unit
exit sequential statement, used in loops
file used to declare a file type
for start of a for type loop statement
function starts declaration and body of a function
generate make copies, possibly using a parameter
generic introduces generic part of a declaration
group collection of types that can get an attribute
guarded causes a wait until a signal changes from False to True
if used in "if" statements
impure an impure function is assumed to have side effects
in indicates a parameter in only input, not changed
inertial signal characteristic, holds a value
inout indicates a parameter is used and computed in and out
is used as a connective in various statements
label used in attribute statement as entity specification
library context clause, designates a simple library name
linkage a mode for a port, used like buffer and inout
Palabras reservadas en VHDL
literal used in attribute statement as entity specification
loop sequential statement, loop ... end loop;
map used to map actual parameters, as in port map
mod operator, left operand modulo right operand
nand operator, "nand" of left and right operands
new allocates memory and returns access pointer
next sequential statement, used in loops
nor operator, "nor" of left and right operands
not operator, complement of right operand
null sequential statement and a value
of used in type declarations, of Real ;
on used as a connective in various statements
open initial file characteristic
or operator, logical "or" of left and right operands
others fill in missing, possibly all, data
out indicates a parameter is computed and output
package a design unit, also package body
port interface definition, also port map
postponed make process wait for all non postponed process to suspend
procedure typical programming procedure
process sequential or concurrent code to be executed
Palabras reservadas en VHDL
pure a pure function may not have side effects
range used in type definitions, range 1 to 10;
record used to define a new record type
register signal parameter modifier
reject clause in delay mechanism, followed be a time
rem operator, remainder of left operand divided by right op
report statement and clause in assert statement, string output
return statement in procedure or function
rol operator, left operand rotated left by right operand
ror operator, left operand rotated right by right operand
select used in selected signal assignment statement
severity used in assertion and reporting, followed by a severity
signal declaration that an object is a signal
shared used to declare shared objects
sla operator, left operand shifted left arithmetic by right op
sll operator, left operand shifted left logical by right op
sra operator, left operand shifted right arithmetic by right
srl operator, left operand shifted right logical by right op
subtype declaration to restrict an existing type
then part of if condition then ...
to middle of a range 1 to 10
Palabras reservadas en VHDL
transport signal characteristic
type declaration to create a new type
unaffected used in signal waveform
units used to define new types of units
until used in wait statement
use make a package available to this design unit
variable declaration that an object is a variable
wait sequential statement, also used in case statement
when used for choices in case and other statements
while kind of loop statement
with used in selected signal assignment statement
xnor operator, exclusive "nor" of left and right operands
xor operator, exclusive "or" of left and right operands
Descripción de arquitecturas

•Descripción de flujo de datos (data flow description)

1 -- eqcomp4 es un comparador de igualdad de cuatro bits

2 entity eqcomp4 is
3 port (
4 a, b: in bit_vector(3 downto 0); -- a, b son las entradas
5 equals: out bit); -- equals es la salida
6 end eqcomp4;
7
8 architecture dataflow of eqcomp4 is
9 begin
10 equals <= ‘1’ when (a=b) else ‘0’;
11 end dataflow;
Descripción de arquitecturas

•Descripción de comportamiento (behavioral description)

1 -- eqcomp4 es un comparador de igualdad de cuatro bits

2 entity eqcomp4 is
3 port (
4 a, b: in bit_vector(3 downto 0); -- a, b son las entradas
5 equals: out bit); -- equals es la salida
6 end eqcomp4;
7
8 architecture behavioral of eqcomp4 is
9 begin
10 comp: process (a,b)
11 begin
12 if a = b then
13 equals <= ‘1’;
14 else
15 equals <= ‘0’;
16 end if;
17 end process comp;
18 end behavioral;
Descripción de arquitecturas
•Descripción estructural (structural description)
1 -- eqcomp4 es un comparador de igualdad de cuatro bits
2 entity eqcomp4 is
3 port (
4 a, b: in std_logic_vector(3 downto 0); -- a, b son las entradas
5 equals: out std_logic); -- equals es la salida
6 end eqcomp4;
7
8 architecture struct of eqcomp4 is
9 component AND4 port ( --Declara una compuerta AND de 4 entradas
10 a,b,c,d: in std_logic;
11 q : out std_logic);
12 end component;
13 component XNOR port ( --Declara una compuerta XNOR de 2 entradas
14 a,b: in std_logic;
15 q: out std_logic);
16 end component;
10 signal x: std_logic_vector (0 to 3);
11 begin
12 u0: XNOR2 port map (a(0), b(0), x(0));
13 u0: XNOR2 port map (a(1), b(1), x(1));
14 u0: XNOR2 port map (a(2), b(2), x(2));
15 u0: XNOR2 port map (a(3), b(3), x(3));
16 u4: AND4 port map (x(0), x(1), x(2), x(3), equals);
17 end struct;
Circuitos combinacionales aritmeticos
•Medio sumador

AB CS
S = A⊕ B
0 0 0 0
0 1 0 1
1 0 0 1 C = A⋅ B
1 1 1 0

A
S
B

C
Circuitos combinacionales aritmeticos
•Sumador completo

A B CI CO S S = A' B' CI + A' BCI '+ AB' CI '+ ABCI

0 0 0 0 0 = CI ' ( A' B + AB') + CI ( A' B'+ AB )
= CI ' ( A ⊕ B ) + CI ( A ⊕ B )'
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0 = CI ⊕ A ⊕ B
1 0 0 0 1
1 0 1 1 0 CO = AB + A' BCI + AB' CI
1 1 0 1 0
1 1 1 1 1 = AB + CI ( A ⊕ B )

A
S
B

CO

CI
Circuitos combinacionales aritmeticos
• Código VHDL para sumador completo 1 bit

library IEEE;
use IEEE.std_logic_1164.all;

entity adder1 is
port (
A, B, CI : in std_logic;
S, CO : out std_logic);
end adder1;

architecture flow1 of adder1 is

begin
S <= CI XOR A XOR B;
CO <= (A AND B) OR (CI AND (A XOR B));
end flow1;
Circuitos combinacionales aritmeticos
• Diagrama de sumador completo 1bit

CO CI
 Circuitos combinacionales aritmeticos
• Diagrama de sumador completo 4bit

A4 B4 A3 B3 A2 B2 A1 B1

C5 C4 C3 C2 C1

S4 S3 S2 S1
Circuitos combinacionales aritmeticos
• Código VHDL para sumador completo 4 bit estructural
library IEEE;
use IEEE.std_logic_1164.all;
entity adder4 is
port (
A, B: in std_logic_vector(3 downto 0);
CI : in std_logic;
S: out std_logic_vector(3 downto 0);
CO : out std_logic);
end adder4;
architecture flow1 of adder4 is
component adder1
port (
A, B, CI : in std_logic;
S, CO : out std_logic);
end component;
signal X: std_logic_vector(2 downto 0);
begin
x1: adder1 port map (A(0), B(0), CI, S(0), X(0));
x2: adder1 port map (A(1), B(1), X(0), S(1), X(1));
x3: adder1 port map (A(2), B(2), X(1), S(2), X(2));
x4: adder1 port map (A(3), B(3), X(2), S(3), CO);
end flow1;
 Tipos de lógica: combinacional

circuito combiancional
Entrada actual sin memoria
Salida

La salida depende sólo de la

entrada
 Tipos de lógica: secuencial

La salida depende de las entradas presentes y

pasadas

circuito combiancional
Entrada actual sin memoria Salida

Almacenamiento de Memoria
entradas pasadas
agregada
Estabilidad
2 ejemplos
1 0 Q
Circuito astable

0 1
Q‘

Circuitos biestables
1
Q

Retardo de propagación Q‘
1
Latches
Los latches y los flip-flops son elementos de memoria que se utilizan en
circuitos secuenciales. Son conocidos también como compuertas biestables.

Los tipos más comunes de latches son:

Tipo IC

S-R 74279

D 7475, 7477

JK

T
 Latch RS
R
Q S R Q Q’
1 0 1 0
Q‘
S

S
R
Q
Q´
 Latch RS
R
Q S R Q Q’
1 0 1 0
Q‘ 0 0 1 0
S

S
R
Q
Q´
 Latch RS
R
Q S R Q Q’
1 0 1 0
Q‘ 0 0 1 0
S
0 1 0 1
S
R
Q
Q´
 Latch RS
R
Q S R Q Q’
1 0 1 0
Q‘ 0 0 1 0
S
0 1 0 1
S 0 0 0 1
R
Q
Q´
 Latch RS
R
Q S R Q Q’
1 0 1 0
Q‘ 0 0 1 0
S
0 1 0 1
S 0 0 0 1
R 1 1 0 0
Q
Q´
Latch RS
R
Q Q R S Q+
0 0 1 1
Q‘ 1 0 0 1
S
1 1 0 0
00 01 00
0 0 0 0
0 1

10 01
10
Dos dispositivos secuenciales

Flip-flop
Los cambios de la salida están determinados
por un reloj

Latch
Puede mantener la salida, dependiendo del
control
Output = input Output = input en el tiempo t
t
*Edge trigger D and J-K flip flop

D J-K

D CLK Q Q‘ J K CLK Q Q‘
0 0 1 0 1 0 1
1 1 0 1 0 1 0
X 0 last Q last Q‘ X X 0 last Q last Q‘
X 1 last Q last Q‘ X X 1 last Q last Q‘
0 0 last Q last Q‘
1 1 last Q‘ last Q
 J-K flip flop

J D Q

K clk

clk
J-K flip flop

library IEEE;
use IEEE.std_logic_1164.all;

entity FFJK is
port (
CLK, RSTN, J, K: in std_logic;
Q, QN : out std_logic);
end FFJK;
J-K flip flop
architecture beh of FFJK is
signal FF : std_logic;
begin
process (CLK, RSTN)
variable JK : std_logic_vector(1 downto 0);
begin
if (RSTN = '0') then
FF <= '0';
elsif (CLK'event and CLK = '1') then
JK := J & K;
case JK is
when "01" => FF <= '0';
when "10" => FF <= '1';
when "11" => FF <= not FF;
when others => FF <= FF;
end case;
end if;
end process;
Q <= FF;
QN <= not FF;
end beh;