Documentos de Académico
Documentos de Profesional
Documentos de Cultura
Unlike with Matlab, where is such a simple task, VHDL can give you few sleepless nights, even
for simple tasks. But once you know the basic initial steps, it would become much more easier.
in VHDL is big topic and its impossible to cover all the areas in a single post. What I try to do
here is explain some of the basics with an example.
An image is almost always a 2D matrix. But processing a 2D image in FPGA might not be a
good idea. It might lead to excessive delays and resources. So we convert the 2D image into a
linear 1 D array. This data can be stored in a RAM or ROM. To get the most efficient memory
module, its recommended that, we use the Block Memory Generator module available in coregen
to do this.
In this example, I am going to read the pixels of an image(of size 3*4), stored in a ROM, and
store the transpose of the image(of size 4*3) in a RAM.
Lets go through the steps in detail now. I have used Xilinx ISE 13.1 for this. The device selected
was xc6slx9-2csg324. These steps might be a little different for a different version of Xilinx, but
remember that the underlying ideas are still the same.
If you have never used coregen, you might want to go through these examples, before
proceeding.
memory_initialization_radix=10;
memory_initialization_vector=22,12,200,126,127,128,129,255,10,0,1,98;
Click generate and coregen would create the necessary files for you.
4. VHDL code:
This code initiates the RAM and ROM created above and calculates the transpose of the input
image. The code also acts as a testbench and reads the data from RAM, to verify the working of
the design.
Its not synthesisable because I have incorporated the functionalites of a testbench into this. But if
you remove the testbench part its synthesisable.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity image_process is
end image_process;
COMPONENT image2
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
begin
end Behavioral;
5. Simulated waveform:
The design was simulated using Xilinx ISIM. The waveform should look like the following: