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OVP, UVP, OTP and current limit protections. RT5041AB of Low Side MOSFET
45m
O_1P8
V1P15A O_1P15A IN_1P05A VIN
V1P5S O_1P5S
LX_1P05A V1P05A
VCC VCC
V1P8A SWO_1P8A
Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
SUSPWRDNACK
3D=YM
DNN
SLP_S0iX_B
EN_1P05A
LX_1P05A
LX_1P05A
LX_1P8
LX_1P8
28 27 26 25 24 23 22
IN_1P8 1 21 IN_1P05A
IN_1P8 2 20 IN_1P05A
O_1P8 3 19 O_1P05A
SLP_S3_B 4 PGND 18 O_3P3A
O_1P24A 5 17 IN_3P3A
29
O_1P15A 6 16 SWO_1P8A
IN_1P24A 7 15 PGND
8 9 10 11 12 13 14
IN_1P15A
IN_1P5S
O_1P5S
SWIN_1P8A
VCC
GND
RSMRST
WQFN-28L 4x4
Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
VCC
V1P05A + VNN V1P8
IN_1P05A IN_1P8
PGND PGND
O_1P05A O_1P8
EN_1P05A
LDO SW
IN_1P24A V1P24A V3P3A
PG_V1P24A IN_3P3A
PG_V3P3A_S
O_1P24A
O_3P3A
LDO RSMRST
IN_1P15A
V1P15A
PG_V1P15A
SW
O_1P15A V1P8A SWIN_1P8A
SLP_S0iX_B
PG_V1P8A_S
LDO
IN_1P5S SWO_1P8A
V1P5S
PG_V1P5S
SUSPWRDNACK
O_1P5S
SLP_S3_B GND
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Electrical Characteristics
(VCC = 5V, TA = 25C, No load, for every voltage rails unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
MOIC
Supply Voltage VCC 4.5 -- 5.5 V
Shutdown Current ISHDN VEN_1P05A = 0V -- -- 5 A
UVLO Threshold VUVLO -- -- 4 V
UVLO Hysteresis VUVLO_HYS -- 150 -- mV
Measured VEN_1P05A,
Enable Input High Voltage VEN_H VSUSPWRDNACK, VSLP_S3_B, 1 -- VCC V
VSLP_S0iX_B
Measured VEN_1P05A,
Enable Input Low Voltage VEN_L VSUSPWRDNACK, VSLP_S3_B, -- -- 0.4 V
VSLP_S0iX_B
Thermal Shutdown Threshold TSD -- 150 -- C
Thermal Shutdown
TSD_HYS -- 25 -- C
Hysteresis
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Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design.
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RT5041AB
7 1, 2
V1P8 IN_1P24A IN_1P8 VIN
10F x 3 8 10F x 3
IN_1P15A
9
IN_1P5S
5 1H
V1P24A O_1P24A 27, 28
LX_1P8 V1P8
22F 22F x 4 * Optional 1
3
O_1P8
V1P15A 6 O_1P15A 4.7R
20, 21
22F IN_1P05A VIN
10F x 3
V1P5S 10 O_1P5S
4.7F 0.47H
22, 23
LX_1P05A V1P05A
14 SWIN_1P8A 19 22F x 7 ** Optional 2
V1P8 O_1P05A
2.2F
11
VCC VCC
16 1F
V1P8A SWO_1P8A
2.2F
26
EN_1P05A V1P05A Enable
17 IN_3P3A 25
V3P3 SLP_S0iX_B S0iX
2.2F 24
SUSPWRDNACK SUSPWRDNACK
4
18 SLP_S3_B S3
V3P3A O_3P3A 10k
2.2F 13
RSMRST PG for V3P3A
GND PGND
12 15, 29 (Exposed Pad)
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EN_1P05A EN_1P05A
(5V/Div) (5V/Div)
V1P8 V1P24A
(1V/Div) (1V/Div)
V1P05A V1P8A
(1V/Div) (1V/Div)
V1P15A VIN = 5V, VCC = 5V, VIN = 5V, VCC = 5V,
(1V/Div) SUSPWRDNACK Low, No Load SUSPWRDNACK Low, No Load
EN_1P05A EN_1P05A
(5V/Div) (5V/Div)
SLP_S3_B
(5V/Div)
V3P3A
(2V/Div)
VIN = 5V, VCC = 5V, V1P5S
SUSPWRDNACK Low, No Load (1V/Div)
RSMRST VIN = 5V, VCC = 5V,
(5V/Div)
SUSPWRDNACK Low, No Load
EN_1P05A EN_1P05A
(5V/Div) (5V/Div)
V1P05A V1P24A
(1V/Div) (1V/Div)
V1P5S
V1P8 (1V/Div)
(1V/Div)
V1P15A V1P8A
(1V/Div) VIN = 5V, VCC = 5V, SUSPWRDNACK Low, No Load (1V/Div) V = 5V, V = 5V, SUSPWRDNACK Low, No Load
IN CC
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EN_1P05A SUSPWRNACK
(5V/Div) (5V/Div)
V3P3A V1P05A
(2V/Div) (1V/Div)
V1P8
(1V/Div)
RSMRST V1P15A
(5V/Div) VIN = 5V, VCC = 5V, SUSPWRDNACK Low, No Load (1V/Div) VIN = 5V, VCC = 5V, EN_1P05A High, No Load
SUSPWRNACK SUSPWRNACK
(5V/Div) (5V/Div)
V1P24A
(1V/Div)
V3P3A
(2V/Div)
V1P8A
(1V/Div)
RSMRST
(5V/Div) VIN = 5V, VCC = 5V, EN_1P05A High, No Load
VIN = 5V, VCC = 5V, EN_1P05A High, No Load
SUSPWRNACK SUSPWRNACK
(5V/Div) (5V/Div)
V1P05A V1P24A
(1V/Div) (1V/Div)
V1P5S
(1V/Div)
V1P8
(1V/Div)
V1P15A V1P8A
(1V/Div) VIN = 5V, VCC = 5V, EN_1P05A High, No Load
(1V/Div) VIN = 5V, VCC = 5V, EN_1P05A High, No Load
Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
SUSPWRNACK SLP_S0iX_B
(5V/Div) (5V/Div)
V1P15A
(1V/Div)
V3P3A SLP_S3_B
(2V/Div) (5V/Div)
RSMRST V1P5S
(5V/Div) (1V/Div)
VIN = 5V, VCC = 5V, EN_1P05A High, No Load VIN = 5V, VCC = 5V, V1P15A Load 1mA
SLP_S0iX_B SLP_S0iX_B
(5V/Div) (5V/Div)
V1P15A V1P15A
(1V/Div) (1V/Div)
SLP_S3_B SLP_S3_B
(5V/Div) (5V/Div)
V1P5S V1P5S
(1V/Div) (1V/Div)
VIN = 5V, VCC = 5V, V1P15A Load 1mA VIN = 5V, VCC = 5V, V1P15A Load 1mA
0.8
(5V/Div) 0.7
0.6
V1P15A
(1V/Div) 0.5
SLP_S3_B 0.4
(5V/Div) 0.3
0.2
V1P5S
(1V/Div) 0.1
VIN = 5V, VCC = 5V, V1P15A Load 1mA
0.0
Time (500s/Div) 4.5 4.7 4.9 5.1 5.3 5.5
VCC (V)
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141
Falling
0.6
140
139
0.4
138
0.2
137
VIN = 5V, EN_1P05A = 2V VIN = 5V, VCC = 5V
136 0.0
4.5 4.7 4.9 5.1 5.3 5.5 -50 -25 0 25 50 75 100 125
VCC (V) Temperature (C)
Input High/Low Voltage vs. Temperature Input High/Low Voltage vs. Temperature
1.0 1.0
SUSPWRDNACK SLP_S3_B
Rising Rising
Input High/Low Voltage (V)
Input High/Low Voltage (V)
0.8 0.8
Falling Falling
0.6 0.6
0.4 0.4
0.2 0.2
0.8
Falling IOUT
0.6 (1A/Div)
VOUT
(20mV/Div)
0.4
VIN = 5V, VCC = 5V,
ILOAD = 1A to 1.9A, SR = 0.9A/s,
COUT = 22F/0603/6.3V x 3
0.2
LX
VIN = 5V, VCC = 5V (5V/Div)
0.0
-50 -25 0 25 50 75 100 125 Time (10s/Div)
Temperature (C)
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LX LX
(5V/Div) (5V/Div)
LX LX
(5V/Div) (5V/Div)
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LX LX
(5V/Div) (5V/Div)
LX LX
(5V/Div) (5V/Div)
VOUT
(500mV/Div)
LX
(5V/Div)
VIN = 5V, VCC = 5V, Load = 2A
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VOUT VOUT
1V/Div) (500mV/Div)
VOUT
(1V/Div)
VOUT
1V/Div)
IL
VIN = 5V, VCC = 5V (5A/Div) VIN = 5V, VCC = 5V
(10V/Div) 1.054
1.052
1.050
VIN = 5V
VOUT 1.048 VIN = 3.3V
(1V/Div)
1.046
1.044
IL
(5A/Div) 1.042
VIN = 5V, VCC = 5V VCC = 5V
1.040
Time (10s/Div) 0 1 2 3 4 5
Load Current (A)
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Output Voltage vs. Load Current Switch Frequency vs. Load Current
1.830 1160
Converter V1P8 Converter V1P05A
1140 VIN = 3.3V
1.825
1.820
1100 VIN = 5V
VIN = 5V
1.815 1080
VIN = 3.3V
1060
1.810
1040
1.805
1020
VCC = 5V VCC = 5V
1.800 1000
0 1 2 3 4 5 1 2 3 4 5
Load Current (A) Load Current (A)
85
1120
VIN = 5V VIN = 5V
80
Efficiency (%)
1100
75
1080
70
1060
65
1040
60
1020 55
VCC = 5V VCC = 5V
1000 50
1 2 3 4 5 0 1 2 3 4 5
Load Current (A) Load Current (A)
90
VIN = 5V
IOUT
Efficiency (%)
85
(1A/Div)
80
VOUT
75
(20mV/Div)
70
VIN = V1P8, VCC = 5V,
65 ILOAD = 0.5A to 1A, SR = 0.5A/s,
VCC = 5V COUT = 22F x 1
60
0 1 2 3 4 5 Time (10s/Div)
Load Current (A)
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IOUT
(100mA/Div)
IOUT
(1A/Div)
VOUT VOUT
(20mV/Div) (10mV/Div)
VIN = V1P8, VCC = 5V, VIN = V1P8, VCC = 5V, SLP_S3_B = High,
ILOAD = 0.5A to 1A, SR = 0.5A/s, ILOAD = 83mA to 100mA, SR = 17mA/s,
COUT = 22F x 1 COUT = 4.7F x 1
Output Voltage vs. Load Current Output Voltage vs. Load Current
1.153 0.752
LDO V1P15A LDO V1P15A
1.149 0.750
Output Voltage (V)
1.145 0.748
1.141 0.746
1.137 0.744
VIN = V1P8, VCC = 5V, VIN = V1P8, VCC = 5V,
SLP_S0iX_B = High SLP_S0iX_B = Low
1.133 0.742
0 200 400 600 800 1000 0 100 200 300 400 500
Load Current (mA) Load Current (mA)
Output Voltage vs. Load Current Output Voltage vs. Load Current
1.244 1.4995
LDO V1P24A LDO V1P5S
1.240
1.4990
Output Voltage (V)
Output Voltage (V)
1.236
1.4985
1.232
1.4980
1.228
1.4975
1.224
VIN = V1P8, VCC = 5V,
VIN = V1P8, VCC = 5V SLP_S3_B = High
1.220 1.4970
0 200 400 600 800 1000 0 10 20 30 40 50 60 70 80 90 100
Load Current (mA) Load Current (mA)
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1.15 0.75
Output Voltage (V)
1.12 0.72
1.11 0.71
VIN = V1P8, VCC = 5V, SLP_S0iX_B = High VIN = V1P8, VCC = 5V, SLP_S0iX_B = Low
Temperature from 40C to 125C Temperature from 40C to 125C
1.10 0.70
-50 -40 -20 0 25 50 75 100 125 -50 -40 -20 0 25 50 75 100 125
Temperature (C) Temperature (C)
1.25
1.50
Output Voltage (V)
Output Voltage (V)
1.24 0mA
1.48 10mA
50mA
1.23 0mA 100mA
100mA 1.46
1.22 500mA
1000mA
1.44
1.21
VIN = V1P8, VCC = 5V, VIN = V1P8, VCC = 5V, SLP_S3_B = High
Temperature from 40C to 125C Temperature from 40C to 125C
1.20 1.42
-50 -40 -20 0 25 50 75 100 125 -50 -40 -20 0 25 50 75 100 125
Temperature (C) Temperature (C)
VOUT VOUT
(500mV/Div) (500mV/Div)
VIN = V1P8, VCC = 5V, SLP_S0iX_B = High VIN = V1P8, VCC = 5V, SLP_S0iX_B = Low
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VOUT VOUT
(500mV/Div) (500mV/Div)
VOUT VOUT
(500mV/Div) (500mV/Div)
IOUT IOUT
(1A/Div) (1A/Div)
VIN = V1P8, VCC = 5V, SLP_S0iX_B = High VIN = V1P8, VCC = 5V, SLP_S0iX_B = Low
VOUT VOUT
(500mV/Div) (500mV/Div)
IOUT IOUT
(1A/Div) (100mA/Div)
VIN = V1P8, VCC = 5V VIN = V1P8, VCC = 5V, SLP_S3_B = High
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80 80
70 70
RON (m )
RON (m )
60 60
50 50
40 40
80 80
70 70
RON (m )
RON (m )
60 60
50 50
40 40
VIN = V1P8, VCC = 5V, IOUT = 300mA, VIN = 3.3V, VCC = 5V, IOUT = 400mA,
Temperature from 40C to 125C Temperature from 40C to 125C
30 30
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (C) Temperature (C)
RSMRST SW RSMRST SW
(5V/Div) (5V/Div)
VOUT VOUT
(500mV/Div) (1V/Div)
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VOUT VOUT
(1V/Div) (2V/Div)
IOUT IOUT
(1A/Div) (500mA/Div)
VIN = V1P8, VCC = 5V VIN = 3.3V, VCC = 5V
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System Power
Battery 3.3V/5V
Charger
(2SXP)
DDR Power
Core Power
RT5041AB_MOIC
VIN V1P05A
V1P8
V1P5S SOC +
Platform Device
V1P24A
V1P15A
SW_V3P3A
SW_V1P8A
EN_V1P05A
SLP_S3_B
SLP_S0iX_B
SUSPWRDNACK
RSMRST(PG)
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Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
According to Table 2, set three control signals to high for S4/S5 status, set SLP_S0iX_B and SLP_S3_B to low to
satisfying S0 mode; for case S0iX mode, give a low level make the action. The relations of the control signals and
voltage to SLP_S0iX_B to change LDO_V1P15A voltage the VR power status are shown in the Table 3.
from 1.15V to 0.75V. If the system need move into S3 or
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SUSPWRDNACK
EN_1P05A 90%
<1ms
V1P8
90%
V1P05A 330s
90%
10% 1.15V
V1P15A 1ms
90%
10%
V1P24A 710s
90%
10%
V1P8A 260s
90%
10%
V3P3A 1ms
10%
RSMRST 760s
Sys to MOIC
SLP_S3_B
90%
V1P5S
V1P15A Start to monitor the signal
SLP_S0iX_B
Sys to MOIC
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EN_1P05A
V1P8
V1P05A
V1P15A
V1P24A
V1P5S
V1P8A
V3P3A
RSMRST
SUSPWRDNACK
EN_1P05A
V1P8
V1P05A
1.15V
V1P15A
V1P24A
V1P8A
85% 90%
V3P3A
RSMRST
system go low
SLP_S3_B
V1P5S
Figure 4. Power Off and Up Sequence with SUSPWRDNACK Going Low and then High
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SLP_S0iX_B
SLP_S3_B
80s* 5s*
V1P15A 1.15V 1.15V 1.15V
0.75V 0.75V
V1P5S 1s 330s
* Loading = 5mA
Thermal Considerations
For continuous operation, do not exceed absolute 4.0
Maximum Power Dissipation (W)1 Four-Layer PCB
maximum junction temperature. The maximum power 3.5
dissipation depends on the thermal resistance of the IC 3.0
package, PCB layout, rate of surrounding airflow, and
2.5
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the 2.0
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Certain points must be considered before starting a layout Place the bypass capacitor close to IN_1P24A,
using the RT5041AB. IN_1P15A, IN_1P5S, IN_1P8A, and IN_3P3A.
Make the traces of the main current paths as short and Place the filter capacitor close to O_1P24A, O_1P15A,
wide as possible. O_1P5S, O_1P8A, and O_3P3A to minimize trace
inductance.
Place input decoupling capacitors as close as possible
as to IN_1P8 and IN_1P05A. This cap provide the instant The GND pin and Exposed Pad should be connected to
current into this pin when the internal MOSFET a strong ground plane for heat sinking and noise
switching. It is preferable to connect the decoupling protection.
capacitors directly to the pins without using vias. An example of PCB layout guide is shown in Figure 7
for reference.
LX_1P05A
LX_1P05A
LX_1P8
LX_1P8
GND GND
Input capacitor The voltage divider must
28 27 26 25 24 23 22
must be placed be connected as close to
5Vin IN_1P8 1 21 IN_1P05A 5Vin
as close to the the device as possible.
IN_1P8 2 20 IN_1P05A
IC as possible. GND
O_1P8 3 19 O_1P05A
SLP_S3_B 4 18 O_3P3A SWO_V3P3A
O_1P24S O_1P24A 5 17 IN_3P3A IN_V3P3A
O_1P5S O_1P15A 6 PGND 29 16 SWO_1P8A SWO_V1P8A GND
IN_1P24A 7 15 PGND
GND
8 9 10 11 12 13 14
RSMRST
VCC
GND
IN_1P5S
O_1P5S
SWIN_1P8A
IN_1P15A
V1P8'
O_1P5S
IN_V1P8A
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D D2 SEE DETAIL A
L
1
E E2
1 1
2 2
e b
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.