De eee ed eon ‘steering Committe Cha shan! Agcawa! ‘General Chait NeanjonA Pol Technical Program Co-hals Rahul Rao Sudeep Posrcho Wend Singh ‘Organising Co-Chair kiran Dimi! Exhibits Co-Caies ‘Shona Menetre Joweedatthar Pubilty Co-Chairs ‘Abhi Ahovale Mono Bhoieroo Tutorial Co-Chairs Annee Gerimelo Vivek Gong Finance Chaie Ritesh in Sponsorship Chair ‘SUmo Mahesh User Tac Co-Chales ‘Ashish Batts Dinesh Pratok Pobiatons Chair MoshuriKrombete Design Contest Co-Chairs ‘mal Kedog Suni Desi Industry Forum Co‘chais Neha Mba Prasad och Fellowship Chale ull Sutoone ‘Student Contest Co-Chats Sorana Shee ‘itera Konan StartUp Co-Chairs ‘amo! anolior Pareg Sonawane Pho Forum Devesh Duved Registration Chal itn Poin ‘Women n-Engneerng Track ouchairs Ashlesho Kroniar Supaiv Kelior ‘Cont. Program Manager rear A Patankar ‘Adsory Members Bhorattumar uo Nog Negancthon Proseep Dharane ProvinDesole SochinSopatnekor Sonthonakrishnen Ramon VstUlison Jsinder Ano IEEE Uaison Vivek Deshpande Rajesh ingale TESA Uaeon Som Shuto Pol Choudhury Sponsored by VLSI Society of India ww Technical sponsors eee 31st International Conference on Nese Eee a ee Pune, Maharashira, India | Jan 6th See This joint conference is a forum for researchers and designers to present and discuss current topics in VLSI design, electronic design automation, embedded systems, and emerging technologies. Two days of tutorials will be followed by three days of regular paper sessions, special sessions, and embedded tutorials. Industry presentation sessions along with exhibits, panel discussions, Design Contest, and Education Forum round off the program. The conference is followed by the Reliability Aware System Design and Test (RASDAT) workshop. TOPICS OF INTEREST: Papers are invited on previously unpublished results in the following categories: EMBEDDED SYSTEMS DESIGN DESIGN TOOLS AND EDA DESIGN METHODOLOGIES AND TECHNOLOGY 1: Embedded Systems Hardware: ‘Ti: Design Verfation: Funcsonal, |: ystemevel Design: Methodoloaes and HW/SW co-desg, So, multicore formal, coverage-siven, hada archtetures, processor and memory desien, mul systems, board lve hardware, HW assisted, and assertion based re, GPU design, network-on-hi, deck scutty, ItemetofTings (oT devices, | verfeaton, behavioral ATL and gate- | tolerant architectures, arcelratos,ditbuted Sensorsactuaters, splays level simulaton, emulation, systems (eg, automate, cyber ahysical ystems 2: Embedded Systems Software: equivalence checking M2: Advances in Digital Design: ogi and pv Operating systems, frmuare algrthms, | T2Test, Reliability Foul-Tolerance: | synthesis place and route, deck tree dsr, midaleware runtimes, paralelzation, DFT, aul modeling and simulation, APG, | sing and nl inogriy,dsin for ‘itualzation, sofware fr low power, Bist repay, delay tet, fault tolerance, "| manufactur and els, power nee, Security reliability, eal tme support, online text AIMS/RF text, oard-level and | variation leant design temerting applications. automotive, | sjtervleveltest, sion debug ost. | M3: Analog, Mined Signal, and RF Desig: Desi telemates, analyses) ‘icon validstion, memory tes relabity.| of analog, med sigral, ana Ff, highspeed wired EB: FPGA and Reconfigurable Systems: | testre and wireless interfaces, low-power analog and RF FPGA rchtecture and FPGA ‘3: Computer-Aided Design (CAD: | M: Power-Aware Design: Power ana and chu design, CAD for FPGA, FPGA logic and behavioralsynthet, lope | estimation, optimization andiow power des, prototyping, FA based accelerators mapping, simulation and formal enerpyefcient des, batteryaware des, Ef: Wireless Systems: Sensor networks, | verifeaton, yout (partitioning, ‘hermal management energy harvesting low power wireless systems, wireless placement, rutng for panning, and | MS: CMOS Technology and Devices: Dep protocols, wireless power delivery ‘compaction, post route optimizations | nanoscale CMOS devs, device modeling and a eae ae cae erm re SImulaton, mult-domain simulation, devee/ercut ose ce enced level rei and variably design in various application areas Me: Emerging Technologies: Post. cMOs dees, wireless, medal, networking, [MEMS sensors biomedical ruts lb-on chip, muted, automotive, contol et. ‘arbon nanotubes, soon photons, spintroni, ‘memos, euremerphlc and quantum “SAFE AND SECURE INTELLIGENT SYSTEMS St: Design for Safety and Reiabllty $2: Secure Ciruts and Systems ‘53: Safety Assurance of Crcults/ Systems Physically unctonabe functions, random System security side channel attacks and Design for functional safety and number generators, faut tolerance anti pracy methodologies, Embedded cerfcation in arzorne, healthcare, systems and architectures systems security n healthcare, dutomotve systems ‘utometive, industrial and Io applications EMBEDDED TUTORIALS AND SPECIAL SESSIONS: Proposals in relevant emerging areas should be submitted as two-page abstracts. On acceptance, authors are required to submit full regular papers. HALF-DAY AND FULL-DAY TUTORIALS: Tutorial proposal are invited for topics of interest including VLSI design, EDA, VLSI technology, and embedded systems. The tutorials will be arranged on the first two days of the conference. PANELS: Proposals must be submitted with an abstract, and alist of panelists SUBMISSIONS: All submissions should be made electronically via the conference website by July 16, 2017. Your manuscript should clearly state the novel ideas, results, and applications of the contribution. Paper submissions will undergo o double-blind review. Papers must be in PDF format and not exceed 6 single spaced pages including figures and references in two-column IEEE conference paper format. Papers ‘exceeding the page limit or identifying the authors will be rejected without review. EXHIBITS: Please contact the Exhibits Chair to explore opportunities for companies to display their products/services. FELLOWSHIPS: The conference will award fellowships, based on need and merit, to partially cover, ‘expenses of attendees from India. Application details will be posted at the conference website. DESIGN CONTEST: Please check the conference website or contact the Design Contest Chair for more details USER TRACK AND PHD FORUM: Please check the conference website for details on criteria and submission dates. IMPORTANT DATES: Submission of Full paper deadline : July 16, 2017 ‘Acceptance of notification September 17, 2017 Camera ready paper due October 8, 2017