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Outline

l Bridge Fault Model
l Bridge Fault Simulation
l Test Generation for Bridge Fault

ECE 1767 University of Toronto

Bridge Fault Model
l After single stuck-at faults, bridge faults are the
most important class of faults.
l Most commonly occurring type of fault.
l Simplified model assumes 0Ω resistance (short)
between two lines (dotted line in the figure)

x1

x
x2

y
ECE 1767 University of Toronto

Bridge Fault Model l Wired-AND ♦ y=0 --> x is s-a-0 ♦ Test for bridge fault: s Set y to 0 and test for x s-a-0 -or- s Set x to 0 and test for y s-a-0 l Wired-OR ♦ y=1 --> x is s-a-1 ♦ Test for bridge fault: s Set y to 1 and test for x s-a-1 -or- s Set x to 1 and test for y s-a-1 l Dominant driver ♦ x always outdrives y ♦ y always outdrives x ECE 1767 University of Toronto Bridge Fault Model x1 x x2 Bridge Function y Assumes 0Ω resistance ECE 1767 University of Toronto .

depending on their logic threshold voltages. ♦ Byzantine Generals Problem x1 x x2 y ECE 1767 University of Toronto . x 1 y 0 ECE 1767 University of Toronto Bridge Fault Model l Gates driven by the bridged nodes may interpret the voltage level differently. Bridge Fault Model l Need to consider drive strengths of bridged nodes to determine voltage level.

but not through f (i. ♦ The back line b is the line closest to the PI’s. the circuit may oscillate. ♦ The front line f is the line closest to the PO’s. f is not sensitive to b). Feedback Bridge Faults l In a feedback bridge fault.. ♦ AND-bridge b f ♦ OR-bridge b f ECE 1767 University of Toronto .e. b f l AND: ♦ set b=0 and test for f s-a-0 (no logical feedback) ♦ set f=0 and test for b s-a-0. there exists at least one path between the two bridged nodes. ECE 1767 University of Toronto Feedback Bridge Faults l If a feedback loop involves an odd number of inversions.

l Input-to-Input ♦ Between inputs of the same gate in polysilicon l Input-to-Output ♦ Between an input and output of the same gate l Source-to-Drain ♦ Between source and drain of the same transistor in diffusion. if the short causes an error. Thesis. l Input-to-Output shorts not targeted in BART ECE 1767 University of Toronto . Bridge Faults l Output-to-Output ♦ Between metal lines in routing channels ♦ Outputs of different gates.. l BART [Patel et al. Glaser. 1993] l Test vectors for input and output stuck-at faults cover Input-to-output shorts. Meyer. M.S. then input value is forced upon the output [Vierhaus. 1996]: Bridge Fault Test Generator ECE 1767 University of Toronto Input-to-Output Short l In a simple CMOS gate. ITC’93] l This is also true for complex CMOS gates such as And-Or-Invert (AOI) and Or-And- Invert (OAI) gates ♦ [Cusey.

H = 1.1 ECE 1767 University of Toronto . any test vector that detects such a fault must always detect some structurally related logic stuck-at fault. l Source-drain shorts not targeted in BART. ECE 1767 University of Toronto Logic Model for a Bridge A 0 G B C H D 1é 0 FAULT-FREE FAULTY MODEL G.H = 0.0 G s-a-0 G.1 G s-a-1 G.H = 0. ♦ Not strictly a logic fault. ♦ However.0 H s-a-1 G.1 G. Source-to-Drain Short l Also called transistor stuck-on fault.H = 1.H = 0.0 H s-a-0 G.H = 1.

ECE 1767 University of Toronto . One of Four Possible Error Manifestations 1 0 A 0 G B 1 A G B 1 1/0 s-a-1 C F X D H 0 0/1 0 1/0 C 1 H D 0 Modeled as Logic Fault F s-a-1 ECE 1767 University of Toronto Circuit Modification for ATPG l All four possible manifestations of a bridge are simultaneously addressed in a single circuit modification ♦ Adds about 10 gates per bridge. l Four single stuck-at faults in the modified circuit represent the four error manifestations. l ATPG can be used to generate four possible test vectors l Test generation complexity is the same as a stuck-at fault test generation.

Strong and Weak Logic Values 1 A weak 1 G ? B0 C 1 H ? D 0 weak 0 A 0 strong 1 G 1 B 0 C 1 H 1 (error) D weak 0 -> 1 0 ECE 1767 University of Toronto Generalized Bridge Model A 0 B MUX G G’ A 1 B Bridge Function C D H’ 1 MUX H C D 0 F X s-a-1 ECE 1767 University of Toronto .

BART Test Generation l Faults extracted by a randomly generated list l Site of the target bridge modified according to the strength model. BART reverts to the normal logic value model. l BART generates vectors for 10 target bridges before invoking a fault simulator ECE 1767 University of Toronto . l ATPG generates tests for the 4 stuck-at faults. l If strength values cannot be justified.