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Basic Operational Concept

1. The decoded instruction is stored in ______ .
a) IR
b) PC
c) Registers
d) MDR
Answer (a)

2. Which registers can interact with the secondary storage?

a) MAR
b) PC
c) IR
d) R0
Answer (a)

3. During the execution of a program which gets initialized first?

a) MDR
b) IR
c) PC
d) MAR
Answer (c )

4. Which of the register/s of the processor is/are connected to Memory Bus?

a) PC
b) MAR
c) IR
d) Both a and b
Answer (b )

5. ISP stands for,

a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
Answer (a )

6. The internal Components of the processor are connected by _______ .

a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
Answer ( b)
7. ______ is used to choose between incrementing the PC or performing ALU operations .
a) Conditional codes
b) Multiplexer
c) Control unit
d) None of these
Answer (b )

8. The registers,ALU and the interconnection between them are collectively called as _____ .
a) Process route
b) Information trail
c) information path
d) data path
Answer (d )

9. _______ is used to store data in registers .

a) D flip flop
b) JK flip flop
c) RS flip flop
d) none of these
Answer ( a)

Memory locations and Addresses

1. The smallest entity of memory is called as _______ .
a) Cell
b) Block
c) Instance
d) Unit
Answer (a)

2. The collection of the above mentioned entities where data is stored is called as ______ .
a) Block
B) Set
c) Word
d) Byte
Answer (c)

3. An 24 bit address generates an address space of ______ locations.

a) 1024
b) 4096
c) 2 ^ 48
d) 16,777,216
Answer (d)
4. If a system is 64 bit machine, then the length of each word will be ____ .
a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
Answer (b)

5. The type of memory assignment used in Intel processors is _____ .

a) Little Endian
b) Big Endian
c) Medium Endian
d) None of the above
Answer (a)

6. When using the Big Endian assignment to store a number, the sign bit of the number is stored
in _____ .
a) The higher order byte of the word
b) The lower order byte of the word
c) Cant say
d) None of the above
Answer (a)

7. To get the physical address from the logical address generated by CPU we use ____ .
a) MAR
b) MMU
c) Overlays
d) TLB
Answer (b)

8. _____ method is used to map logical addresses of variable length onto physical memory.
a) Paging
b) Overlays
c) Segmentation
d) Paging with segmentation
Answer c()

9. During transfer of data between the processor and memory we use ______ .
a) Cache
b) TLB
C) Buffers
d) Registers
Answer (d)
10. Physical memory is divided into sets of finite size called as ______ .
a) Frames
b) Pages
c) Blocks
d) Vectors
Answer (a)

Memory Operations and Management

1. Add #%01011101,R1 , when this instruction is executed then,
a) The binary addition between the operands takes place
b) The Numerical value represented by the binary value is added to the value of R1
c) The addition doesnt take place , whereas this is similar to a MOV instruction
d) None of the above
Answer (a)

2. If we want to perform memory or arithmetic operations on data in Hexa-decimal mode then

we use ___ symbol before the operand .
a) ~
b) !
c) $
d) *
Answer (c)

3. When generating physical addresses from logical address the offset is stored in _____ .
a) Translation look-aside buffer
b) Relocation register
c) Page table
d) Shift register
Answer (b)

4. The technique used to store programs larger than the memory is ______ .
a) Overlays
b) Extension registers
c) Buffers
d) Both b and c
Answer (a)

5. The unit which acts as an intermediate agent between memory and backing store to reduce
process time is _____ .
a) TLBs
b) Registers
c) Page tables
d) Cache
Answer (d)
6. The Load instruction does the following operation/s,
a) Loads the contents of a disc onto a memory location
b) Loads the contents of a location onto the accumulators
c) Load the contents of the PCB onto the register
d) Both a and c
Answer (b)

7. Complete the following analogy: - Registers are to RAMs as Caches are to _____ .
a) System stacks
b) Overlays
c) Page Table
d) TLB
Answer (d)

8. The BOOT sector files of the system are stored in _____ .

a) Hard disk
b) ROM
c) RAM
d) Fast solid state chips in the motherboard
Answer (b)

9. The transfer of large chunks of data with the involvement of the processor is done by _______
a) DMA controller
b) Arbitrator
c) User system programs
d) None of the above
Answer (a)

10. Which of the following technique/s used to effectively utilize main memory ?
a) Address binding
b) Dynamic linking
c) Dynamic loading
d) Both b and c
Answer (c)

Accessing I/O Devices

1. In memory-mapped I/O
a) The I/O devices and the memory share the same address space
b) The I/O devices have a separate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation
Answer (a)
2. The usual BUS structure used to connect the I/O devices is
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
Answer (c)

3. In intels IA-32 architecture there is a seperate 16 bit address space for the I/O devices..??
a) False
b) True
Answer (b)

4. The advantage of I/O mapped devices to memory mapped is

a) The former offers faster transfer of data
b) The devices connected using I/O mapping have a bigger buffer space
c) The devices have to deal with fewer address lines
d) No advantage as such
Answer (c)

5. The system is notified of a read or write operation by

a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
c) Raising an appropriate interrupt signal
d) sending a special signal along the BUS
Answer (d)

6. To overcome the lag in the operating speeds of the I/O device and the processor we use
a) BUffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions
Answer (b)

7. The method of accessing the I/O devices by repeatedly checking the status flags is
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None
Answer (a)
8. The method of synchronising the processor with the I/O device in which the device sends a
signal when it is ready is
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA
Answer (c)

9. The method which offers higher speeds of I/O transfers is

a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA
Answer (d)

10. The process where in the processor constantly checks the status flags is called as
a) Polling
b) Inspection
c) Reviewing
d) Echoing
Answer (a)
Standard I/O Interfaces
1. ______ is used as an intermediate to extend the processor BUS.
a) Bridge
b) Router
c) Connector
d) Gateway
Answer (a)

2. ________ is an extension of the processor BUS.

b) USB
d) None of the above
Answer (c)

3. ISA stands for

a) International American Standard.
b) Industry Standard Architecture.
c) International Standard Architecture.
d) None of the above.
Answer (b)
4. ANSI stands for
a) American National Standards Institute.
b) Architectural National Standards Institute.
c) Asian National Standards Institute.
d) None of the above.
Answer (a)

5. The video devices are connected to ______ BUS.

a) PCI
b) USB
Answer (d)

6. SCSI stands for

a) Signal Computer System Interface.
b) Small Computer System Interface.
c) Small Coding System Interface.
d) Signal Coding System Interface.
Answer (b)

7. ISO stands for

a) International Standards Organisation.
b) International Software Organisation.
c) Industrial Standards organisation.
d) Industrial Software Organisation.
Answer (a)

8. The system developed by IBM with ISA architecture is ______.

c) PC-AT
d) None of the above
Answer (c)

9. IDE disk is connected to the PCI BUS using ______ interface.

a) ISA
b) ISO
Answer (a)
10. IDE stands for
a) Intergrated Device Electronics.
b) International Device Encoding.
c) Industrial Decoder Electronics.
d) International Decoder Encoder.
Answer (a)

Hazards Of Processor Architecture

1. Any condition that causes a processor to stall is called as _____.
a) Hazard
b) Page fault
c) System error
d) None of the above
Answer (a)

2. The periods of time when the unit is idle is called as _____.

a) Stalls
b) Bubbles
c) Hazards
d) Both a and b
Answer (d)

3. The contention for the usage of a hardware device is called as ______.

a) Structural hazard
b) Stalk
c) Deadlock
d) None of the above
Answer (a)

4. The situation where in the data of operands are not available is called ______.
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
Answer (a)

5. The stalling of the processor due to the unavailability of the instructions is called as ____.
a) Control hazard
b) structural hazard
c) Input hazard
d) None of the above
Answer (a)
6. The time lost due to branch instruction is often referred to as _____.
a) Latency
b) Delay
c) Branch penalty
d) None of the above
Answer (c)

7. The pipeline bubbling is a method used to prevent data hazard and structural hazards.
a) True
b) False
Answer (a)

8. _____ method is used in centralized systems to perform out of order execution.

a) Scorecard
b) Score boarding
c) Optimizing
d) Redundancy
Answer (b)

9. The algorithm followed in most of the systems to perform out of order execution is ______.
a) Tomasulo algorithm
b) Score carding
c) Reader-writer algorithm
d) None of the above
Answer (a)

10. The problem where process concurrency becomes an issue is called as ______.
a) Philosophers problem
b) Bakery problem
c) Bankers problem
d) Reader-writer problem
Answer (d)

1. During the execution of the instructions, a copy of the instructions is placed in the
______ .
a) Register
b) RAM
c) System heap
d) Cache
Answer (d)

2. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively.
Suppose A can execute an instruction with an average of 3 steps and B can execute with
an average of 5 steps. For the execution of the same instruction which processor is faster
a) A
b) B
C) Both take the same time
d) Insufficient information
Answer (a)

3. A processor performing fetch or decoding of different instruction during the execution of

another instruction is called ______ .
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
d) None of these
Answer (b)

4. For a given FINITE number of instructions to be executed, which architecture of the

processor provides for a faster execution?
a) ISA
c) Super-scalar
d) All of the above
Answer (c)

5. The clock rate of the processor can be improved by,

a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using overclocking method
d) All of the above
Answer (d)
6. An optimizing Compiler does,
a) Better compilation of the given piece of code.
b) Takes advantage of the type of processor and reduces its process time.
c) Does better memory managament.
d) Both a and c
Answer (b)

7. The ultimate goal of a compiler is to,

a) Reduce the clock cycles for a programming task.
b) Reduce the size of the object code.
c) Be versatile.
d) Be able to detect even the smallest of errors.
Answer (a)

8. SPEC stands for,

a) Standard Performance Evaluation Code.
b) System Processing Enhancing Code.
c) System Performance Evaluation Corporation.
d) Standard Processing Enhancement Corporation.
Answer (a)

9. As of 2000, the reference system to find the performance of a system is _____ .

a) Ultra SPARC 10
d) None of these
Answer (a)

10. When Performing a looping operation, the instruction gets stored in the ______ .
a) Registers
b) Cache
c) System Heap
d) System stack
Answer (b)

11. 11. The average number of steps taken to execute the set of instructions can be made to
be less than one by following _______.
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential
Answer (c)
12. If a processor clock is rated as 1250 million cycles per second, then its clock period is
________ .
a) 1.9 * 10 ^ -10 sec
b) 1.6 * 10 ^ -9 sec
c) 1.25 * 10 ^ -10 sec
d) 8 * 10 ^ -10 sec
Answer (d)

13. If the instruction, Add R1,R2,R3 is executed in a system which is pipe-lined, then the
value of S is (Where S is term of the Basic performance equation)
a) 3
b) ~2
C) ~1
d) 6
Answer (c)

14. CISC stands for,

a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
Answer (c)

15. As of 2000, the reference system to find the SPEC rating are built with _____ Processor .
a) Intel Atom SParc 300Mhz
b) Ultra SPARC -IIi 300MHZ
c) Amd Neutrino series
d) ASUS A series 450 Mhz
Answer (b)