Design Compiler J-2014.09 TrainingUpdate

Design Compiler J-2014.
09
Update Training
RTL Synthesis
2014 Synopsys, Inc. All rights reserved. 1

CONFIDENTIAL INFORMATION
The following material is confidential information of Synopsys
and is being disclosed to you pursuant to a non-disclosure
agreement between you or your employer and Synopsys. The
material being disclosed may only be used as permitted under
such non-disclosure agreement.
IMPORTANT NOTICE
In the event information in this presentation reflects Synopsys
future plans, such plans are as of the date of this presentation
and are subject to change. Synopsys is not obligated to develop
the software with the features and functionality discussed in
these materials. In any event, Synopsys products may be
offered and purchased only pursuant to an authorized quote and
purchase order or a mutually agreed upon written contract.
2014 Synopsys, Inc. All rights reserved. 2 Synopsys Confidential

Design Compiler J-2014.09
QoR Highlights
15% smaller area compared to H-2013.03
20% reduction in leakage power compared to H-2013.03
25% runtime improvement compared to I-2013.12

on designs with long runtime (20+ hours)

J-2014.09 RTL Synthesis
Optimization
Improved Usability
Correlation to Layout
Improved Test Support
Improved Timing Support
DC Explorer

Optimization
Improved Usability
DC Explorer

Optimization
One-Pass Retiming Improvement

Checkpoint Guidance for Formality Verification
Improved Area Optimization of Gate-Level Netlist
Multibit Mapping Improvements
Changes to Shift Register Identification
Register Replication Enhancements
Manual Control of MUX Mapping
One-Pass Retiming Improvement
Automatically detects the number of pipeline stages and

adjusts the timing constraints before retiming
Produces better QoR
Beneficial for designs with a large number of pipeline
stages
create_clock period 1.0 clk
set_optimize_registers true
compile_ultra scan
Before Retiming After Retiming
Delay goal 4.0 clk 1.0

I-2013.12-SP4
Checkpoint Guidance
For Formality Verification
Enables higher completion rate in one-pass retiming
Eliminates the manual two-pass verification process with
placement-aware multibit mapping
Creates an intermediate netlist and writes the
guide_checkpoint guidance command to the .svf file
when
Retiming a design using the set_optimize_registers
command before running the compile_ultra command
Performing placement-aware multibit mapping of replicated
registers, using the create_register_bank command
Works with Formality I-2013.12-SP4 and later

I-2013.12-SP2
Improved Area Optimization
Of Gate-Level Netlist
The optimize_netlist -area command was added
in Design Compiler in I-2013.12 to improve the area of
new and legacy netlists
This flow enhancement improves area by 10% compared
to the H-2013.03 release
Run this command after compile_ultra:
compile_ultra
optimize_netlist -area
The optimize_netlist command is included in the

I-2013.12-SP2 Design Compiler Reference Methodology

I-2013.12-SP2
Improved Area Optimization
Of Gate-Level Netlist: Reference Methodology Flow
Library setup
Read RTL
Apply constraints
Apply power settings
Tcl or DEF Optional compile_ultra scan gate_clock

Floorplan
insert_dft
compile_ultra incremental -scan
optimize_netlist -area
Write design and reports

(.ddc, Milkyway, Verilog)
To next reference methodology

I-2013.12-SP2
set_multibit_options -mode timing_only
Multibit register inference in compile_ultra now
supports a new timing_only mode
set_multibit_options [-mode
non_timing_driven
;# default
;# maps to multibit register whenever possible
| timing_driven
;# maps to multibit register only when it does not
;# hurt timing or area QoR
| timing_only ]
;# maps to multibit register only when it does not
;# hurt timing QoR even if area QoR is adversely
;# affected

I-2013.12-SP1
Additional Scan Register Support
Multibit register inference in compile_ultra now
supports multibit scan registers with internal scan chains
and a dedicated or gated scan output
1-bit register
(SDFF_SO) New
2-bit register 2-bit register
(SDFF2_SO)

Scan Cell Library Modeling Requirements
Both single bit and multibit versions of scan registers
must be present in the same .lib file
This type of multibit register is marked as blackbox

Recommended: Specify the user_function_class
attribute for sizing optimization
Compile the .lib using Library Compiler I-2013.12 or later

versions
See Library Compiler I-2013.12 update training for more

information
I-2013.12-SP2
Shift Register Identification
Synchronous Shift Registers Not Identified by Default
Synchronous shift register identification is disabled by
default to achieve higher multibit cell usage
Preserves multibit mapping throughout the flow
Enable only under both conditions:

When multibit cells are not used
When it helps to improve area for your design
set_app_var
compile_seqmap_identify_shift_registers_with_synchronous_logic
true (default is now false)
I-2013.12-SP2
Shift Register Identification
Short Shift Registers Not Identified Across Hierarchy
Shift registers are only identified across hierarchical
boundaries if they have a length of 3 or more
Reduces excessive scan chain criss-crossing with registered
interfaces
Helps improve congestion and scan chain wire lengths
Reduces port punching during scan insertion
Shift register identified
Shift register not identified

(all registers scan-replaced)

I-2013.12-SP1
Manual Register Replication
Across Hierarchy
Design Compiler version I-2013.12 can replicate
registers and combinational logic on a timing path from or
to that register
Limited to logic in the same hierarchy or across one level of
hierarchy
Starting in I-2013.12-SP1, Design Compiler can now

replicate registers and combinational logic that are
beyond a single level of hierarchy

I-2013.12-SP1
Manual Register Replication
Across Hierarchy
m1
m1/m2
m1/m2/m3
U2
Original logic
A_reg U3
U1
U4
m1
m1/m2
m1/m2/m3 New logic after
U1_rep1
using the following
A_reg_rep1 U2
command
U3
A_reg U1
U4
set_register_replication num_copies 2 m1/m2/m3/A_reg -include_fanout_logic U1

I-2013.12-SP2
map_to_mux Attribute Design Compiler
Graphical
Manual Control for MUX Mapping
New map_to_mux attribute to specify MUX mapping
Set on specific MUX_OP or SELECT_OP instances in GTECH
Does not restrict optimization (no size_only or dont_touch)
Replaces hdlin_infer_mux with size_only or the
//synopsys infer_mux_override directive
In some situations, MUX mapping can help improve congestion
Use with compile_ultra spg to ensure mapping to library MUX

cells
Use cross-probing data from the congestion map to help identify the target
instances
Set the map_to_mux attribute on these specific instances before running
compile_ultra -spg
Verify with get_attribute or report_attribute -cell

I-2013.12-SP2
map_to_mux Attribute Design Compiler
Graphical
Example
read_verilog test.v
link
...
report_cell [get_cells block1_0/C572] ;# identify targeted SELECT_OP
...
#Cell Reference Library Area Attributes
#-----------------------------------------------------------------------------
#block1_0/C572 *SELECT_OP_32.16_32.1_16 0.000000 s, u
#-----------------------------------------------------------------------------
#Total 1 cells 0.000000
set_attribute [get_cells block1_0/C572] "map_to_mux" true

compile_ultra -spg
report_reference ;# muxes now present
...
#Reference Library Unit Area Count Total Area Attributes
#-----------------------------------------------------------------------------
...
#mylib_mux2_b1 mylib 1.001000 16 16.016001
#mylib_mux4_a1 mylib 2.717000 160 434.720001
...

Optimization
Improved Usability
DC Explorer

Improved Usability (1 of 2)
Enhanced report_resources
Multiple-Port Net Fixing Options
ILM Obsolescence
Multicore Enhancements
Infeasible Paths Support
New -physical option with report_timing
Support for Flat Query Commands
Improved Usability (2 of 2)
Cross-Probing from RTL to Gates

RTL Browser Enhancements
RTL Cross-Probing for Datapath

Enhanced report_resources
Reports datapath leakage that blocks datapath extraction

after synthesis
Generates the following HDL messages from
analyze_datapath_extraction in report_resources
HDL-120: Datapath leakage blocks extraction
HDL-125: Instantiated DesignWare component cannot be extracted
HDL-132: Mixed sign data types blocks extraction
Available in text report, HTML report, and RTL cross-
probing
Datapath Extraction Report
Information: The output of subtractor associated with
resources 'sub_388 (test.v:388)' is treated as signed
signal. (HDL-132)

Multiple-Port Net Fixing Options
User Interface
The set_fix_multiple_port_nets command has
two new options:
Use the new -exclude_clock_network option to exclude nets
belonging to the clock network from multiple-port net fixing
Use the new no_rewire option to disable rewiring attempts
before buffering multiple-port and constant-port nets
Effective when advanced multiple-port net fixing is enabled
The compile_advanced_fix_multiple_port_nets
variable still controls advanced multiple-port net fixing
Enabled by default in DC Explorer (default: true)
Disabled by default in Design Compiler topographical and wire
load modes (default: false)

H-2013.03
ILM Obsolescence
In Design Compiler
Beginning in H-2013.03, log messages warned you that
ILMs are in the flow
Block-level message with create_ilm:

Information: Use of command 'create_ilm' is not recommended.
This command will be obsolete in a future release. (INFO-103)
Top-level message when using ILM blocks:
Information: Use of ILM blocks is not recommended. The use of

ILM blocks will be obsolete in a future release. (ABS-259)

ILM Obsolescence
No Support for ILMs in J-2014.09
Design Compiler no longer supports the creation or use
of ILMs
IC Compiler no longer supports ILM usage
Ensure that you have successfully migrated to the use of

block abstractions in your flow
Work with your AC or Synopsys support center if you

face issues when trying block abstractions

J-2014.09
ILM Obsolescence
In Design Compiler
Beginning in J-2014.09, error messages are issued when
ILMs are used in the flow
Block-level message with create_ilm:

Error: Starting with version 2014.09, the create_ilm command
is no longer supported. Use the 'create_block_abstraction'
command instead. (OBS-012)
Top-level message when trying to read ILM designs:
Error: Reading of ILM designs is no longer supported. Cannot

read ILM.ddc. (DDC-35)

I-2013.12-SP2
Overview
set_host_options max_cores invokes multicore
capability in Design Compiler
Helps improve the tool runtime
The license requirement in Design Compiler has

changed to one set of licenses for every four cores
In previous releases, one set of licenses were needed for every
two cores
If the number of available cores on the machine is less

than the number of cores requested, performance can be
impacted

Enhanced set_host_options -max_cores Command
Case 1: Machine with fewer cores I-2013.12-SP1
Number of cores on the machine < number of user-specified cores
set_host_options resets the max cores to the maximum
number of cores on the machine
Warning: You requested 4 cores. However, the host hostname1
only has 2 available cores. The tool will ignore the request
and use -max_cores 2. (UIO-230)
Case 2: Machine with high load I-2013.12-SP2

Most of the cores on the machine are already overloaded
set_host_options limits the number of cores based on the
machine load
Warning: You requested 14 cores. However, load on host
hostname2 is 10.150000. Tool will ignore the request and use 6
cores. (UIO-231)

I-2013.12-SP3
Enhanced set_host_options -max_cores Command
Both checks are on by default
To disable the checks:

set_app_var disable_multicore_resource_checks true
Setting to true can impact multicore performance

I-2013.12-SP2
Automatic Detection During Compile
Paths are infeasible when timing cannot be met due to:
Unreasonable input or output delays
Missing timing exceptions (false path and multicycle path)
Starting in I-2013.12-SP2, Design Compiler
Detects and treats infeasible paths as false paths during synthesis
Optimizes other critical paths in presence of infeasible paths
Removes tool-derived timing exceptions at the end of compile
The write_sdc command writes out only user-specified timing
exceptions
Supports consistent capability with DC Explorer
Supporting infeasible paths helps improve synthesis
runtime and timing QoR of feasible paths

I-2013.12-SP2
Impact on Design Timing Constraints and Reports
There maybe differences between the timing numbers
reported in the compile log and the post-compile timing,
QoR, and constraint reports
Timing numbers reported in the log take the tool-derived infeasible

path exceptions into account
Post-compile reports do not account for infeasible path exceptions
Use the new ignore_infeasible_paths option with

report_timing, report_qor, and report_constraints to
exclude infeasible paths from the reports

I-2013.12-SP2
Timing Reports
The report_timing attributes command adds a new inf
attribute to the startpoint and endpoint of tool-detected infeasible paths
Attributes:
d - dont_touch
u - dont_use
mo - map_only
so - size_only
i - ideal_net or ideal_network
inf - infeasible path New attribute
Point Fanout Cap Trans Incr Path Attributes
-------------------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 6.00 6.00 f
in1 (in) 0.00 0.00 6.00 f inf
in1 (net) 2 4.75 0.00 6.00 f
u_in1/A_in (unit_0) 0.00 6.00 f startpoint &
u_in1/A_in (net) 4.75 0.00 6.00 f endpoints
u_in1/U7/INP (INVX0_LVT) 0.00 0.00 6.00 f marked as
u_in1/U7/ZN (INVX0_LVT) 0.06 0.03 6.03 r
u_in1/N0 (net) 1 2.12 0.00 6.03 r
infeasible
u_in1/A_out_reg/D (DFFX1_LVT) 0.06 0.00 6.03 r inf
data arrival time 6.03

I-2013.12-SP2
Categorized Timing Reports
Use the new infeasible_paths option of create_qor_snapshot and
query_qor_snapshot to capture the paths and add an infeasible path
column in the HTML-based report:
create_qor_snapshot -name snap1 -max_paths 30 -infeasible_paths
query_qor_snapshot -name snap1 -infeasible_paths -columns \
{path_group infeasible_paths startpoint endpoint wns zero_path}

I-2013.12-SP1
Support for report_timing -physical
Reports Pin Locations and Capacitive Loads
The new physical option of report_timing reports
pin locations and capacitive loads for pins and nets
Consistent with IC Compiler
Works in Design Compiler topographical and DC Explorer physical flows

I-2013.12-SP1
Support for Flat Query Commands
get_flat_cell, get_flat_net, get_flat_pin
Design Compiler supports new flat versions of query
commands, similar to IC Compiler:
get_flat_cells
get_flat_nets
get_flat_pins
The arguments for these commands are:
[-quiet]
[-regexp |-exact]
[-nocase]
[-filter expression]
[patterns | -of_objects objects]
[-all]
The of_objects option is supported in Design Compiler only
Overview
Works with Verilog, VHDL, and SystemVerilog RTL
Helps you analyze inferred cells from RTL source files

Use to find and analyze the implementation and placement of
timing-critical or congestion-critical portions of RTL source files
Helps you find and analyze the placement of instantiated

cells (clock gates for example)
Cross-probing from RTL to datapath resource reports can

help you to better understand datapath extraction
This analysis can help you to improve the datapath coding style
for better extraction
User Interface
1. Choose Open RTL Files on the AnalyzeRTL menu
2. The Open RTL Files dialog box appears
The current
The design RTL files mentioned
directory in the run script

User Interface
3. Open the RTL file to be cross-probed
The RTL file appears in

the RTL browser
The lines that can be

cross-probed are
highlighted in green

User Interface
4. Follow these steps to cross-probe from RTL to gates:
Step 1: Select a line in the RTL file, and Step 2: Choose Select Objects of
then right-click to open the pop-up menu Selected Line(s)
Step 3: The Selection List dialog box

appears showing the cells inferred
from the selected line
Note: Multiple line cross-probing is
not supported

Inferred Cells Selected in Schematic and Layout Views
Step 1: Select a line in the RTL file, and Step 2: Choose Select Objects of
then right-click to open the pop-up menu Selected Line(s)
Step 3: The Inferred cells are selected

and colored white in any schematic and
layout views in which they appear
Cross-probing from RTL to gates opens only the Selection List dialog box
RTL That Can Be Cross-Probed
Only RTL lines that have netlist
correspondence can be cross-probed
Select Objects of Selected Line(s) is dimmed

for lines that cannot be cross-probed

First Column Grouping
The default view has the
The first column shows
first RTL file name in
the file names, line
expanded format
numbers, and cell names
The second column

shows the number of
cells inferred by the line

Multi-Source Cell Support
A cell might be associated with two RTL files
The RTL browser displays the other RTL files associated
with that cell
A + symbol in the cell name
list indicates multiple sources
for the corresponding cell

Multi-Source Cell Support
Click the + symbol to This line shows the

view the other source second RTL file associated
file names with cell m2/O_reg

I-2013.12-SP1
Generating a Datapath Extraction Report
Run analyze_datapath_extraction from GUI menu
Use either AnalyzeRTL > Analyze Datapath Extraction
or Design > Analyze Datapath Extraction
Cross-probe from datapath extraction report to RTL
Clicking a file name in datapath extraction report opens a new
RTL browser and highlights the corresponding line number
Click the RTL file

Cross-probed line

I-2013.12-SP3
Generating a Datapath Resource Report
To generate a design resources report from the RTL
browser:
Select a cell, right-click and choose Report Resources of Selected
report_resources runs for the design that contains this cell

I-2013.12-SP2
Cross-Probing from RTL to Datapath Resources Report
Find the datapath report for the operators in the selected
line in the RTL browser
The line number is
3 displayed, click the
Find button
Choose Search in
2 Resource Report
Observe cross-probed
4 report
Select a line
1 and right-click
Optimization
Improved Usability
DC Explorer

Zroute-Based Global Buffering

Zroute-Based Congestion-Driven Placement
Milkyway Schema V8.1 Update
Analyzing RTL Congestion
Congestion Report Enhancements
Faster Execution of start_icc_dp Command

Zroute-Based Global Buffering
Design Compiler
Improves Congestion in Narrow Channels Graphical
Congestion-aware global buffering reduces congestion

along narrow channels across macros
Based on Zroute estimation
Use the new -global_route true option of the
set_ahfs_options command to enable
The default is false in Design Compiler
report_ahfs_options will show status Global Route: ON
Enable for macro-intensive designs with narrow channels
Enable in both Design Compiler and IC Compiler for best results
Might impact QoR and runtime
Use only when needed to improve congestion in narrow channels

Congestion-Driven Placement
Design Compiler
Zroute-Based for Improved Correlation Graphical
Improves congestion estimation and correlation with

IC Compiler on highly congested designs
Zroute-based, consistent with IC Compiler
Uses the same congestion thresholds as IC Compiler
Set the new placer_enable_enhanced_router

variable to true to enable
The default is false in Design Compiler
The default is true in IC Compiler
Might impact QoR and runtime

Use only when needed for highly congested designs

Two Release Interoperability Model
Schema version has changed to v8.1 in J-2014.09
Two release schema interoperability model:
No schema change in I-2013.12 (default schema is v7)
Schema change in J-2014.09 (default schema is v8.1)
Full backward compatibility across previous releases
Older schema versions can always be read by a newer release
Implicit conversion supported, explicit conversion recommended
Forward compatibility for one release, then on by default:
Design Compiler I-2013.12-SP4, SP5 supports Schema v8.1
Design Compiler J-2014.09 generated Milkyway can be read by
Design Compiler I-2013.12-SP4 and later, but not I-2013.12-SP3
Design Compiler J-2014.09 has schema v8.1 on by default

Details
Why the change?
Emerging node designs need more data types per layer and a
routing layer index above 187
All routes at 10nm and below need native coloring support
Milkyway v8.1 Schema supports 2 layer modes
Default mode: Milkyway database and technology file support up
to 255 layers and 4096 data types per layer
Extended mode: Milkyway database and technology file support
up to 4095 layers and 4096 data types per layer
Use the extend_mw_layers command to enable
The change is transparent in default layer mode
See IC Compiler J-2014.09 update training for further
details on Schema v8.1
I-2013.12-SP2
Analyzing RTL Congestion Design Compiler
Graphical
Pre-Synthesis Congestion Analysis
Predicts RTL congestion before synthesis
Provides early feedback to influence RTL decisions for congestion
Allows you to try alternatives in RTL to alleviate congestion
Provides a report to identify potential congestion sources
in the RTL such as:
Large MUX (MUX_OP)
Large selector (SELECT_OP)
Large data switch network
Large ROM
Parallel high-fanout nets
Identifies RTL source files and includes line numbers

I-2013.12-SP2
Graphical
User Interface
New analyze_rtl_congestion command does not
require physical data
Required input
Link libraries
Target libraries (for any instantiated gates)
RTL
Available in Design Compiler and DC Explorer
Still need post-synthesis report_congestion to
identify floorplan congestion

I-2013.12-SP2
Graphical
Example
dc_shell> analyze_rtl_congestion
****************************************
Report : RTL congestion
Design : my_design
Version: I-2013.12-SP2
Date : Thu Feb 27 03:54:00 2014
****************************************
########################################
Large MUX details
########################################
------------------------------------------------------------------------
Structure Cell name Size (width) Line No RTL File
------------------------------------------------------------------------
MUX_OP C10567 16 x 1 (163) 83 /u/9000560869.v
MUX_OP C10566 16 x 1 (163) 82 /u/9000560869.v
...

I-2013.12-SP1
report_congestion Design Compiler
Graphical
Now Reports Cells in Congested Regions
New option for report_congestion provides a
text-based report of cells in congested regions:
-list_cells_over_grc_violation
grc_violation_threshold
The grc_violation_threshold is an integer value
Cells are listed if they have a Max number at or above the
threshold
Cells are presorted to list designs with the most
congested cells first
Does not require interactive GUI session
Also works in DC Explorer
Cross-probing to RTL source not supported

I-2013.12-SP1
report_congestion Design Compiler
Graphical
Report Example
dc_shell-topo> report_congestion -list_cells_over_grc_violation 30
****************************************
Report : congestion
Design : my_design
Version: I-2013.12-SP1
Date : Wed Apr 23 15:37:28 2014
****************************************
Both Dirs: Overflow = 590305 Max = 33 (1 GRCs) GRCs = 85938 (67.13%)

H routing: Overflow = 275009 Max = 29 (1 GRCs) GRCs = 43141 (33.70%)
V routing: Overflow = 315296 Max = 33 (1 GRCs) GRCs = 42797 (33.43%)
Cells in Congested Regions:
Design Cell Reference Congestion
---------------------------------------------------------------------------
my_subdesign U2359 MYLIB_AO22X1 33
my_subdesign U7117 MYLIB_AOI22X1 31
my_subdesign U12115 MYLIB_INVX4 32
my_subdesign U12002 MYLIB_BUFFX8 30

I-2013.12-SP2
Floorplan Exploration Design Compiler
Graphical
Faster Execution of start_icc_dp command
The start_icc_dp command now executes faster with
a new default location for storing temporary files
Previous releases stored in current working directory
New default stores at $TMPDIR/dcg_unique_string
The $TMPDIR is the TMPDIR UNIX environment variable
If TMPDIR UNIX environment variable is not defined, Design
Compiler Graphical stores the files in the /tmp directory
You can override the default behavior by using the

-work_dir option with the set_icc_dp_options
command

Optimization
Improved Usability
DC Explorer

Physical Scan Cell Repartitioning During

Incremental Compile
New SCANDEF Flow

Physical Scan Cell Repartitioning
During Incremental Compile Design Compiler
Graphical
Starting with J-2014.09:

Design Compiler now also supports physical scan cell
repartitioning in the binary flow for both DFTMAX compressed
and standard scan designs
Provides improved results and QoR after incremental

compile in terms of cell count, congestion, and timing
Requires:
DFT Compiler license for standard scan designs
DFTMAX license for compressed scan designs
Design Compiler Graphical license

During Incremental Compile: User Interface Design Compiler
Graphical
Starting with J-2014.09, you must specify the -scan and

-spg options in the incremental compile command to
perform reordering:
compile_ultra incremental scan -spg
Physical scan cell repartitioning is disabled by default

Use the set_optimize_dft_options command to
enable and configure repartitioning
set_optimize_dft_options
[-repartitioning_method none | single_directional
| multi_directional | adaptive ] ;# default is none
[-single_dir_option vertical | horizontal ]
;# default is horizontal

During Incremental Compile: Behavior Design Compiler
Graphical
Behavior of physical optimization features under different

conditions
Re- Re-
Conditions
ordering partitioning
Default
ON OFF
set_optimize_dft_options
repartitioning_method single_directional ON ON
| multi_directional | adaptive
set
test_enable_scan_reordering_in_compile_ OFF OFF
incremental false (default: true)

During Incremental Compile: Example 1 Design Compiler
Graphical
Running in a single session:

# Perform initial compile with spg option
compile_ultra scan -spg
# Insert DFT
insert_dft
# Perform incremental compile with re-ordering and multi-directional

# re-partitioning
set_optimize_dft_options repartitioning_method multi_directional

During Incremental Compile: Example 2 Design Compiler
Graphical
Running in multiple sessions:

### Session 1 ###
# Perform initial compile with spg option

compile_ultra scan -spg
# Insert DFT
insert_dft
# Write the design

write_file format ddc hierarchy output ./design.ddc
### Session 2 ###
# Read the design

read_ddc ./design.ddc

# Perform incremental compile with re-ordering and multi-directional
# re-partitioning
set_optimize_dft_options repartitioning_method multi_directional

New SCANDEF Flow
Overview
Starting in J-2014.09:
Design Compiler uses a new SCANDEF writer
New SCANDEF writer is enabled by default in J-2014.09
Benefits:
Solution is more solid and robust
Requires:
DFT Compiler license (no change from previous release)
Limitations:
Hierarchical SCANDEF still uses the old SCANDEF writer

New SCANDEF Flow
Supported Features
The following DFT features are supported:
Standard scan and compressed scan
Multiple test-mode scan
Internal pins flow
Memories with test models
Multivoltage
PLL flows
Core wrapping
Shift registers
Multibit registers

New SCANDEF Flow
Single Session Example
# Perform initial compile
compile_ultra scan
# Perform Insert DFT

insert_dft
# Write SCANDEF before writing .ddc file

write_scan_def output before_inc.def
# Always check the SCANDEF file
check_scan_def
# Write the design
write_file format ddc hierarchy output ./before_inc.ddc
# Perform incremental compile

compile_ultra incremental scan

write_scan_def output after_inc.def
check_scan_def
# Write the design
write_file format ddc hierarchy output ./after_inc.ddc

New SCANDEF Flow
Multiple Session Example
### Session 1 ###
# Perform initial compile
compile_ultra scan
# Perform Insert DFT
insert_dft
write_scan_def output before_inc.def
check_scan_def
# Write the design
write_file format ddc hierarchy output ./before_inc.ddc
### Session 2 ###

# Read the design
read_ddc ./before_inc.ddc
# Perform incremental compile
compile_ultra incremental scan
write_scan_def output after_inc.def
check_scan_def
# Write the design
write_file format ddc hierarchy output ./after_inc.ddc

Optimization
Improved Usability
DC Explorer

Launch Clock Behavior of Transparent Latches

Support for rise_exclude and fall_exclude options

I-2013.12-SP4
Launch Clock Behavior
Of Transparent Latches
The behavior of the variable
timing_early_launch_at_borrowing_latches
has been changed for consistency with PrimeTime
This variable became public in the Design Compiler

I-2013.12-SP4 release
This variable is true by default and removes clock

latency pessimism for paths that begin at the data pin of
a transparent latch

I-2013.12-SP4
Of Transparent Latches: Time Borrowing Example
F1 L1 F2
Big
D Q D Q D Q
delay
CP GN CP
CLK
F1-L1 path borrowed timing from L1-F2

Borrowing path launched from L1/D : Blue Arrow

I-2013.12-SP4
Of Transparent Latches: Solution
The F1-L1 path needs to time
borrow F1 Big L1 F2
D Q delay D Q D Q
The setup time for L1/GN uses
the early launch clock edge CP GN CP
CLK
The L1-F2 path needs to use

the early launch clock edge to
calculate timing correctly if time
borrowing has occurred CLK
*Green edge : early launch F1-L1 TB

*Red edge : late launch
*TB : amount of time borrow L1-F2

I-2013.12-SP4
Of Transparent Latches: Usage Recommendation
timing_early_launch_ CRPR Behavior Note

at_borrowing_latches
True False Use early skew launch
False False Use late skew launch NOT

(pessimistic) recommended
True True Use early skew launch Check for non-

CRPR applied zero CRPR
(can be optimistic) value
False True Use late skew launch
CRPR applied
Note: CRPR = Clock Reconvergence Pessimism Removal

I-2013.12-SP4
rise_exclude and fall_exclude
New Options for report_timing and get_timing_paths
The new exclude option for the report_timing and
get_timing_paths commands was added in
Design Compiler I-2013.12
Prevents reporting of all data paths from, through, or to the named
pins, ports, nets, and cell instances
The new rise_exclude and fall_exclude options
are added in Design Compiler I-2013.12-SP4
These options behave the same as -exclude, but only apply to
rising or falling paths at the named pins, ports, nets, and cell
instances
These options do not apply to clock pins, clock paths, or
time borrowing latch paths
I-2013.12-SP4
rise_exclude and fall_exclude
Usage Example
report_timing -from ff3/CK -to latch3/D report_timing -from ff3/CK -to latch3/D
-rise_exclude inv6/Z -fall_exclude inv6/Z

Optimization
Improved Usability
DC Explorer

DC Explorer
AnalyzeRTL Multicycle Path Histogram

Support for UPF Flow in DC Explorer

I-2013.12-SP3
AnalyzeRTL Multicycle Path Histogram
In DC Explorer
Multicycle Paths
Starting in I-2013.12-SP3, you can create separate path

slack and logic-level histograms for multicycle paths
A new Clock Cycles column in the data table shows the
number of clock cycles for a timing path

I-2013.12-SP2
UPF Flow in DC Explorer
Create Design Data and Explore Results
UPF in DC Explorer is UPF Support
different than UPF in UPF RTL
(incomplete) (incomplete)
Design Compiler
DC Explorer:
Works with minimal UPF
DC Explorer
Automates insertion of power
management cells
High quality
Allows exploration of power plan design data, including UPF
Outputs a complete RTL UPF

for Design Compiler
Explore the impact of low power intent

I-2013.12-SP2
Automated Approach to Handle UPF
Inputs
Minimal UPF input needed to start the exploration
Power domain definitions
Power state table (PSTs)
RTL: Pre-instantiated power management cells will be treated as
standard cells
Outputs
Gate-level netlist with power management cells
Full UPF with power management cell strategies
Early floorplanning for Design Compiler topographical and
IC Compiler implementation

I-2013.12-SP2
Automated Approach to Handle UPF
Isolation insertion: on all outputs of shutdown domains
Example: Output ports of PD1 and PD2
Level-shifter insertion: on power domain boundaries with
a voltage difference in any state
Example: Between PD1 and PD2 (voltage difference in S1, S3)
Example: Between PD1 and PD3 (voltage difference in S1)
Always-on buffers: on all Power State Table (PST)
feedthrough paths that cross PD1 PD2 PD3
domain boundaries S1 1.2V 0.8V 0.8V
Example: on a net from PD1 to PD3 S2 off off 0.8V
that goes through PD2 S3 1.2V 0.8V 1.2V
No support for retention registers
yet
I-2013.12-SP2
Power Exploration Summary Report
Power domain # Instances Area Leakage
PD1 32465 942.3 1100
PD2 5678 59.5 370

* Generated by report_mv_qor
Top-level table with basic information

HTML links to get detailed information on a specific
power domain
Overhead from power management cells level shifters
and isolation cells
Power-domain centric view of area and leakage

I-2013.12-SP2
Power Exploration Detailed Report
Domain: PD2 # Instances Area Leakage
Level shifters 70 4.5 45
Isolation cells 60 7.0 25
Always-on cells 50 3.5 20
PM cells total 180 15.0 90
Macros 0 0 0
I/O Pads 0 0 0
Standard cells 5488 15.0 280
Total 5678 59.5 370
* Generated by report_mv_qor
Power domain details provide area and leakage

requirements to meet multivoltage design goals

Thank You

APPENDIX
Command and Variable Changes

New, Changed, and Removed
Commands and Variables in J-2014.09
Compared to I-2013.12
LEGEND
Design Compiler
Power Compiler
Timing related
DFT Compiler
DesignWare minPower
Tcl built-in

New Commands in J-2014.09
analyze_library
Design Compiler
analyze_rtl_congestion
Power Compiler check_upf
get_defined_commands
Timing related
get_shift_register_chains
DFT Compiler gui_create_task_item
gui_create_tk_palette_type
DesignWare minPower
gui_report_task
Tcl built-in remove_scan_skew_group
report_ieee_1500_configuration
report_scaling_lib_group
report_scan_skew_group
reset_ieee_1500_configuration
set_ieee_1500_configuration
set_scan_skew_group
set_upf_query_options
Removed Commands in J-2014.09
change_macro_view
Design Compiler
change_selection_no_core
Power Compiler change_selection_too_many_objects
compare_interface_timing
Timing related
create_ilm
DFT Compiler get_ilm_objects
get_ilms
DesignWare minPower
print_proc_new_vars
Tcl built-in report_ilm
set_clock_skew
set_delay_calculation
write_interface_timing

Changed Commands in J-2014.09
all_registers:
Design Compiler Removed -inverted_output option
analyze_dw_power:
Added -sort_ascending option
Power Compiler
Removed -sort_asending option
change_names:
Timing related Added -skip_inactive_constraints option
create_command_group:
DFT Compiler Added -info option
create_net_shape:
DesignWare minPower Removed -quiet option
create_qor_snapshot:
Tcl built-in Added -nosplit option
create_qtm_delay_arc:
Added -max_insertion_delay option
Added -min_insertion_delay option
create_qtm_drive_type:
Removed -lib_cell_input_transition option
create_route_guide:
Removed -switch_preferred_direction option
create_user_shape:
Removed -quiet option

create_via:
Design Compiler Removed -no_snap option
define_dft_partition:
Added -extest_cells option
Power Compiler
define_name_maps:
Added -design_name option
Timing related Removed -design option
define_test_mode:
DFT Compiler Added -target option
Added -transparent_mode_of option
DesignWare minPower Removed -inherit option
find_objects:
Tcl built-in Added -exact option
Added model argument to object_type option
get_cells:
Added -at option
Added -intersect option
Added -touching option
Added -within option
get_timing_paths:
Added -fall_exclude option
Added -rise_exclude option

get_tracks:
Design Compiler Removed -nocase option
Removed -regexp option
gui_set_current_task:
Power Compiler
Added -task option
Removed -name option
Timing related read_file:
Removed -ilm option
DFT Compiler read_lib:
Added -imported_jcr option
DesignWare minPower remove_core_area:
Removed -verbose option
Tcl built-in remove_die_area:
Added -verbose option
remove_placement_blockage:
remove_route_guide:
remove_target_library_subset:
Removed -clock_path option
remove_terminal:

report_annotated_delay:
Design Compiler Added -min option
report_clock_gating:
Added -enable_conditions option
Power Compiler
report_congestion:
Added -list_cells_over_grc_violation option
Timing related report_constraint:
Added -ignore_infeasible_paths option
DFT Compiler Added -min_period option
report_datapath_gating:
DesignWare minPower Added -gated option
report_lib:
Tcl built-in Added -jcr option
report_power_domain:
Added -hierarchy option
Added object_list2 argument
report_qor:
report_resources:
Added design_list argument

report_timing:
Design Compiler Added -fall_exclude option
Added -rise_exclude option
Power Compiler
save_qtm_model:
Added -format option
Timing related set_ahfs_options:
Added -global_route option
DFT Compiler set_always_on_strategy:
Removed -bias_type option
DesignWare minPower set_annotated_delay:
Added -dont_touch option
Tcl built-in set_check_library_options:
Added -char_integrity option
Added -significant_digits option
set_dft_configuration:
Added -ieee_1500 option
Removed -lbist option
Removed -logicbist option
set_fix_multiple_port_nets:
Added -exclude_clock_network option
Added -no_rewire option

set_route_zrt_common_options:
Design Compiler Added -extra_via_off_grid_cost_multiplier_by_layer_
name option
Added -ignore_var_spacing_to_blockage option
Power Compiler
Added -ignore_var_spacing_to_pg option
Added -ignore_var_spacing_to_shield option
Timing related Added -min_edge_offset_for_macro_pin_connection_by_
layer_name option
DFT Compiler Added -separate_tie_off_from_secondary_pg option
Added -via_on_grid_by_layer_name option
DesignWare minPower Added -wire_on_grid_by_layer_name option
set_scan_compression_configuration:
Tcl built-in Added -shared_codec_controls option
set_scan_path:
Added -init_data option
Added -opcode option
set_scan_replacement:
Removed -aux_clock_lssd option
set_streaming_compression_configuration:
Added -exclude_clocks option
set_target_library_subset:
Removed -clock_path option

set_test_point_configuration:
Design Compiler Removed -exclude_elements option
write_test_protocol:
Added -disable_codecs option
Power Compiler
Timing related
DFT Compiler
DesignWare minPower
Tcl built-in

New Variables in J-2014.09
compile_seqmap_honor_sync_set_reset (Default is false)
Design Compiler
disable_multicore_resource_checks (Default is false)
Power Compiler dont_bind_unused_pins_to_logic_constant (Default is false)
hdlin_report_sequential_pruning (Default is false)
Timing related link_portname_allow_period_to_match_underscore
(Default is false)
DFT Compiler mv_make_primary_supply_available_for_always_on
(Default is true)
DesignWare minPower placer_channel_detect_mode (Default is false)
placer_enable_enhanced_router (Default is false)
Tcl built-in
route_guide_naming_style (Default is %s_%d)
sh_help_shows_group_overview (Default is true)
test_dedicated_clock_chain_clock (Default is false)
test_fast_feedthrough_analysis (Default is false)
test_sync_occ_1x_period (Default is 20)

New Variables in J-2014.09
timing_consider_internal_startpoints (Default is true)
Design Compiler
timing_dont_traverse_pg_net (Default is true)
Power Compiler timing_early_launch_at_borrowing_latches (Default is true)
timing_enable_slack_distribution (Default is false)
Timing related
timing_use_ceff_for_drc (Default is false)
DFT Compiler upf_allow_refer_before_define (Default is false)
upf_block_partition (Default is "")
DesignWare minPower
upf_iso_filter_elements_with_applies_to (Default is ENABLE)
Tcl built-in upf_isols_allow_instances_in_elements (Default is true)
upf_suppress_etm_model_checking (Default is false)

Changed Variables in J-2014.09
compile_seqmap_identify_shift_registers_with_synchronous_
Design Compiler logic:
Default changed to false
from true
Power Compiler
hdlin_preserve_sequential:
Default changed to none
Timing related from false
hdlin_while_loop_iterations:
DFT Compiler Default changed to 4096
from 1024
DesignWare minPower
Tcl built-in


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Design Compiler J-2014.

2014 Synopsys, Inc. All rights reserved. 1

2014 Synopsys, Inc. All rights reserved. 2 Synopsys Confidential

20% reduction in leakage power compared to H-2013.03

25% runtime improvement compared to I-2013.12

2014 Synopsys, Inc. All rights reserved. 3 Synopsys Confidential

2014 Synopsys, Inc. All rights reserved. 4 Synopsys Confidential

2014 Synopsys, Inc. All rights reserved. 5 Synopsys Confidential

One-Pass Retiming Improvement

Automatically detects the number of pipeline stages and

Before Retiming After Retiming

Delay goal 4.0 clk 1.0

2014 Synopsys, Inc. All rights reserved. 7 Synopsys Confidential

2014 Synopsys, Inc. All rights reserved. 8 Synopsys Confidential

The optimize_netlist command is included in the

2014 Synopsys, Inc. All rights reserved. 9 Synopsys Confidential

Apply power settings

Tcl or DEF Optional compile_ultra scan gate_clock

compile_ultra incremental -scan

Write design and reports

To next reference methodology

2014 Synopsys, Inc. All rights reserved. 10 Synopsys Confidential

2014 Synopsys, Inc. All rights reserved. 11 Synopsys Confidential

2-bit register 2-bit register

2014 Synopsys, Inc. All rights reserved. 12 Synopsys Confidential

This type of multibit register is marked as blackbox

Compile the .lib using Library Compiler I-2013.12 or later

See Library Compiler I-2013.12 update training for more

Enable only under both conditions:

Shift register identified

Shift register not identified

2014 Synopsys, Inc. All rights reserved. 15 Synopsys Confidential

Starting in I-2013.12-SP1, Design Compiler can now

2014 Synopsys, Inc. All rights reserved. 16 Synopsys Confidential

set_register_replication num_copies 2 m1/m2/m3/A_reg -include_fanout_logic U1

2014 Synopsys, Inc. All rights reserved. 17 Synopsys Confidential

Use with compile_ultra spg to ensure mapping to library MUX

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set_attribute [get_cells block1_0/C572] "map_to_mux" true

2014 Synopsys, Inc. All rights reserved. 19 Synopsys Confidential

2014 Synopsys, Inc. All rights reserved. 20 Synopsys Confidential

Cross-Probing from RTL to Gates

2014 Synopsys, Inc. All rights reserved. 22 Synopsys Confidential

Reports datapath leakage that blocks datapath extraction

2014 Synopsys, Inc. All rights reserved. 23 Synopsys Confidential

2014 Synopsys, Inc. All rights reserved. 24 Synopsys Confidential

Block-level message with create_ilm:

Top-level message when using ILM blocks:

Information: Use of ILM blocks is not recommended. The use of

2014 Synopsys, Inc. All rights reserved. 25 Synopsys Confidential

IC Compiler no longer supports ILM usage

Ensure that you have successfully migrated to the use of

Work with your AC or Synopsys support center if you

2014 Synopsys, Inc. All rights reserved. 26 Synopsys Confidential

Block-level message with create_ilm:

Top-level message when trying to read ILM designs:

Error: Reading of ILM designs is no longer supported. Cannot

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The license requirement in Design Compiler has

If the number of available cores on the machine is less

2014 Synopsys, Inc. All rights reserved. 28 Synopsys Confidential

Case 2: Machine with high load I-2013.12-SP2

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To disable the checks: