Importing digital code block into Cadence AMS

Ayman E. Selmy,
Analog IC Designer,
IMEC.
1 Contents
1. ABSTRACT:................................................................................................................................. 3
2. VHDL / VERILOG SETUP. ......................................................................................................... 4
3. PROCEDURE ............................................................................................................................... 5

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 1. Abstract:
In this document, importing a vhdl/verilog block into cadence AMS simulator is presented. Even though
many current tools are built to automate this step, such as: NCSim, NCVHDL, they arent guaranteed to work
all the time without unexpected errors out of nowhere, such as compilation errors while the code is error-
free.

The audience are expected to have a high maturity level in Cadence simulations, and in VHDL/Verilog.
The goal of this document is to nicely, easily, quickly import vhdl/verilog codes into Cadence and generate a
symbol for them to start the simulations. This document is prepared on Cadence 64x, and a VHDL code,
hidden for confidentiality.

For questions, please contact Ayman Selmy at: ayman.selmy.ext@imec.be.

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2. Vhdl / verilog setup.

- You must verify that your code is 100% error-free and compiled / built / simulated on a digital design
environment, like ISE, Modelsim, etc.

- NOTE: the entity name, must be same name as the cell name in Cadence when you create it.

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3. Procedure
1) Create a new library, whatever name and attach it to your tech file.

2) In this library, create a VHDL AMS cell like below. NOTE that the type is VHDLAMSText for VHDL,
there is another one for Verilog code, and cell name has to as the entity in your VHDL.

3) After this a text file . vams will pop-up, to add your vhdl/verilog.

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4) Add your code, save it, and close the window, make sure to copy all the vhdl codes including
everyhting like IEEE library inclusion line codes. Click yes, NOTE: it will only give you this pop-
up window ONLY WHEN your code is mounted into cadence ERROR FREE. If it didnt
give you this pop-up window, you messed up with some steps.

5) After clicking yes, a symbol will be presented.

6) Add another View with vhdl/verilog Type, and write rtl into it and again paste your code
(VHDL/Verilog)

7) Done! Simulate it with Cadence AMS only, another tutorial will be made for AMS.