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HomeELECTRONICSVLSI/VHDL/VerilogDSPApplicationsAHighSpeedFPGAImplementationofanRSDBasedECCProcessor2016

A HIGH-SPEED FPGA IMPLEMENTATION OF AN RSD-BASED ECC PROCESSOR 2016

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DSPApplications February13,2017
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AHighSpeedFPGAImplementationofanRSDBasedECCProcessor2016 Phone

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In this paper, an exportable applicationspecific instructionset elliptic curve

cryptographyprocessorprimarilybasedonredundantsigneddigitrepresentation
is proposed. The processor employs extensive pipelining techniques for Subject

KaratsubaOfman methodology to realize high throughput multiplication. Re: A HighSpeed FPGA Implementation of an RSDBased ECC Processor 2016
Furthermore, an efficient modular adder without comparison and a high
throughput modular divider, that results in a short datapath for maximized Message

frequency, are implemented. The processor supports the recommended NIST

curve P256 and is based on an extended NIST reduction scheme. The proposed processor performs singlepurpose multiplication
usingpointsinaffinecoordinatesin2.twentysixmsandrunsatamaximumfrequencyof160MHzinXilinxVirtex5(XC5VLX110T)
fieldprogrammablegatearray.

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