Electric Power Systems Research 140 (2016) 722734

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Electric Power Systems Research

journal homepage: www.elsevier.com/locate/epsr

A new topology for Z-source half-bridge inverter with low voltage

stress on capacitors
Ebrahim Babaei , Elias Shokati Asl
Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran

a r t i c l e i n f o a b s t r a c t

Article history: In this paper, a new topology for Z-source half-bridge inverter is proposed. This topology is achieved by
Received 14 November 2015 using LC networks in conventional half-bridge converter. The proposed inverter can produce symmetric
Received in revised form 31 March 2016 and asymmetric voltages with different amplitudes during positive and negative half-cycles. By appro-
Accepted 11 April 2016
priate value of duty cycle it is possible to achieve the conventional half-bridge characteristics. Other
Available online 30 May 2016
advantage of this inverter is producing zero voltage level at output. It is noticeable that the conventional
half-bridge inverter cannot generate zero voltage at the output. This inverter can be used in different
Keywords:
applications in industry such as electrochemical, electroplating and residential applications. In this paper,
Half-bridge inverter
Z-source converter
the steady state analysis of the proposed inverter in different operating modes is presented. Moreover,
LC network the calculations of voltage stress of capacitors, current ripple of inductors, voltage ripple of capacitors,
Series Z-source inverter and power loss of the proposed inverter are presented. Then, design of proper values of inductors and
capacitors is given. To show the advantages and disadvantages of the proposed topology, it is compared
with some conventional topologies. The correct operation of the proposed topology is reconrmed by
simulation and experimental results.
2016 Elsevier B.V. All rights reserved.

1. Introduction limited to below of dc input voltage. To overcome the above prob-

In conventional voltage source inverter (VSI), the RMS value of
the output voltage is less than the input voltage [1]. To increase
the voltage gain, a transformerless step-up inverter has been pre-
sented in [2]. This topology reduces the size of the inverter but
increases the control complexity. A new control method based on
digital signal processor instead of redesigning the main circuit has
been presented in [3]. Redesigning the main circuit can enhance
the stability and reduce the cost and complexity of the converter.
In conventional VSI, a short circuit in legs of inverter which is
called shoot-through (ST) can destroy the converter. To prevent the
short-circuit in conventional VSI, both switches of each phase leg
must not turn on simultaneously. So, the conventional three-phase
VSI has six active states when the dc voltage is impressed across
the load and two zero states when the load terminals are shorted
through either the upper or lower three devices. These total eight
non-shoot-through (non-ST) switching states and their combina-
tions have created many pulse width-modulation (PWM) control
methods [4]. Moreover, in conventional VSI, the ac output voltage is
Corresponding author..
E-mail addresses: e-babaei@tabrizu.ac.ir (E. Babaei), e.shokati@tabrizu.ac.ir
(E. Shokati Asl).
lems of conventional VSI, a new topology which is called Z-source
inverter (ZSI) has been presented in [5]. The ZSI has additional zero
state which is called shoot-through zero state that is forbidden in
the conventional VSI. The ZSI uses the shoot-through zero states
to increase the voltage gain by gating on both upper and lower
switches of legs simultaneously. In this conditions, the current is
limited by the series inductors.
The ZSI topology is daily improved and new topologies of it
have been presented [6,7]. The ZSI is used in fuel cell systems
[8], dynamic voltage restorer [9], distributed generation [10], pho-
tovoltaic systems [11] and electric vehicles [12]. Despite many
advantages of the ZSI, it has some drawbacks such as high vol-
tages stress on capacitors, high start-up inrush current and lack
of common ground between the input source and the inverter. In
order to solve these drawbacks of the conventional ZSI, series Z-
source inverter (SZSI) has been presented in [13]. This topology
reduces voltage stress on capacitors and start-up inrush current,
but its boost factor is same as conventional ZSI. Another topol-
ogy called quasi Z-source inverter (QZSI) has been presented in
[14], and its design and application in PV systems and motors drive
are investigated in [1517]. Having common ground between the
input source and inverter and reduction of rated values of ele-
ments are the advantages of this topology, but this topology has the
same boost factor as SZSI. The switched inductor Z-source inverter

http://dx.doi.org/10.1016/j.epsr.2016.04.010
0378-7796/ 2016 Elsevier B.V. All rights reserved.
 E. Babaei, E. Shokati Asl / Electric Power Systems Research 140 (2016) 722734
(SL-ZSI) has been presented in [18] which has greater boost factor
than the conventional ZSI, but it has high voltage stress on capac-
itors and high start-up inrush current. New control methods for
ZSI have been presented in [1921] to control output ac voltage
and increase dc-link voltage. To reduce the circuit size and weight,
the switched boost inverter (SBI) has been presented in [22]. In
this topology, the voltage stress on capacitor is same as ZSI and
its voltage gain is lower than the conventional ZSI. To improve the
voltage gain, another topology called current-fed switched inverter
(CFSI) has been presented in [23]. This topology has various disad-
vantages such as higher voltage stress on capacitor in comparison
with the conventional ZSI and SBI. To overcome high start-up inrush
current and also increasing the voltage gain, LZ-source inverter
(LZSI) has been presented in [24]. In this inverter, to reduce the
number of inductor-diode units and to reach high voltage gain,
the inverter must operate at high value of duty cycle of shoot-
through zero state. The conventional half-bridge ZSI may operate
in shoot-through zero state, consequently the output voltage will
have higher range than conventional one [25]. Nevertheless, for
some special applications such as electrochemical power supply,
this range is not appropriate [2629]. In electrochemical power
supply, in positive and negative half-cycles of output voltages, it is
needed to have voltages with different waveforms and amplitudes.
For example, these applications require higher voltage amplitude
in positive half-cycle than negative one. As another example, in
plating technology the density and direction of current must be
changed, immediately [2830] which in general the conventional
converters cannot satisfy these characteristics.
In this paper, a new topology for series Z-source half-bridge
inverter is proposed. Moreover, to reach high value of voltage gain,
an extended topology for half-bridge series Z-source inverter based
on series connection of several impedance networks is proposed.
The proposed topologies have low voltage stress on capacitors. Also,
these topologies can produce symmetric and asymmetric voltages
with different amplitudes during positive and negative half-cycles.
Generating zero voltage level at the output is another advantage of
the proposed topologies, while this voltage level cannot be obtained
in conventional half-bridge inverters. In the following sections, in
addition to steady state analyses of the proposed inverter in dif-
ferent operating modes, calculation of voltage stress on capacitors,
the current ripple of inductors, and voltage ripple of capacitors are
presented. Moreover, the calculation of power losses of the pro-
posed inverter is given with details. Then, a simple control method
is introduced to control the proposed inverter. A comprehensive
comparison is presented to show the advantages and disadvantages
of the proposed topology in comparison with the conventional
topologies. Finally, the simulation and experimental results are
presented to prove the correct operation of the proposed inverter.
Fig. 2. Operating modes in D1 + D2 1 state; (a) S1 is on and S2 is off; (b) S1 is off and S2 is on; (c) S1 and S2 are off.
723
Fig. 1. Power circuit of the proposed inverter.
2. Proposed half-bridge inverter
The power circuit of the proposed inverter based on series
connection of two impedance networks is shown in Fig. 1. The
upper impedance network consists of C1p and C2p capacitors and
L1p and L2p inductors and the lower impedance network con-
sists of C1n and C2n capacitors and L1n and L2n inductors. The S1
and S2 switches, Dp and Dn diodes, and two dc voltage sources
with the magnitude equal to Vi are other components of the pro-
posed half-bridge inverter. The inductors in impedance networks
are used to avoid high current during time interval of shoot-
through zero state. To simplify analysis, the following assumptions
have been made: all elements are ideal, L1p = L2p = L1n = L2n = L and
C1p = C2p = C1n = C2n = C, all capacitors values are large and the load
is assumed resistive.
2.1. Analysis of the proposed inverter in different operating states
The on and off states of switches and diodes produce different
operating states of inverter. The proposed inverter can operate in
two different states that each of them has three operating modes.
At the following, D1 and D2 are duty cycles of S1 and S2 switches,
respectively and DST is the duty cycle of shoot-through zero state.
At the next subsections, two different states are investigated.
2.1.1. First state
In this state, D1 + D2 1 and the switches cannot turn on simul-
taneously. Therefore, the circuit would not be under ST state. In this
state, there are three operating modes. In the rst operating mode
which is shown in Fig. 2(a), S1 and Dn are turned on and S2 and
Dp are turned off. In the second operating mode which is shown in
Fig. 2(b), S1 and Dn are turned off and S2 and Dp are turned on. In
724 E. Babaei, E. Shokati Asl / Electric Power Systems Research 140 (2016) 722734

where iL,1p , iL,2p , iL,1n and iL,2n show the current through L1p , L2p , L1n
and L2n , respectively.
Considering the relation vL = L(diL /dt), (5) and (6), the following
equations can be obtained:

vL,1p = vL,2p (7)

vL,1n = vL,2n (8)

According to (1) and (2), vo can be obtained as follows:

vL,2n vL,2p + vC,1p vC,2n
Fig. 3. Waveforms of switching signals in rst operating state (D1 + D2 1). vo = (9)
2

the third operating mode which is shown in Fig. 2(c), S1 and S2 are Considering (1) and (9), we can write:
turned off and Dp and Dn are turned on. The on and off signals of vC,1p vC,2n vL,2p vL,2n
switches (GS1 , and GS2 ) are shown in Fig. 3. In this gure, 1 means
vL,2p = vL,1p = Vi + + + (10)
2 2 2 2
the on state of switches and 0 shows the off state of switches.
By substituting (10) in (2), the following equation is obtained:

2.1.2. Second state vC,1p vC,2n vL,2n vL,2p

vL,2n = vL,1n = Vi + + + (11)
In this state, D1 + D2 > 1 and there are three operating modes as 2 2 2 2
shown in Fig. 4. In the rst operating mode, S1 and S2 are on, in the
second operating mode S1 is on and S2 is off, and nally in the third 2.1.2.2. Second operating mode (time interval t1 t < t2 ). In this
operating mode, S1 is off and S2 is on. Considering t0 as the start time mode, the voltage and energy of C1p and C2p are reduced and the
of the rst operating mode, then t1 with value t1 = t0 + (D2 + D1 1)T voltages of C1n and C2n are increased. The inductors current and
will be the start time of second operating mode, t2 will be the start their energy are reduced, too. Applying KVL in the circuit shown in
time of third operating mode with value of t2 = t1 + (1 D2 )T and Fig. 4(b) and (c) results:
t3 = T will be the end of period. These three modes are studied in


vC,1p + vL,1p = 0
details at the following subsections.

vC,2p + vL,2p = 0
(12)
2.1.2.1. First operating mode (time interval t0 t < t1 ). In this mode,

vC,1n + vL,2n = 0
to simplify the calculations t0 = 0 is assumed. In this mode, the

voltage across capacitors and their energy are decreased and the vC,2n + vL,1n = 0
current through inductors are increased. Applying KVL in circuit
By substituting the value of vL,2p from (12) in (1), the following
shown in Fig. 4(a) results:
equation is obtained:
Vi vC,1p + vL,2p + vo = 0 (1)
vo = vo,p = Vi + vC,1p + vC,2p (13)
Vi vC,2n + vL,2n vo = 0 (2)
where vo,p shows the positive value of the output voltage.
where vL,2p and vL,2n are the voltages across L2p and L2n , respec-
tively. vC,1p and vC,2n are the voltages across C1p and C2n , 2.1.2.3. Third operating mode (time interval t2 t < t3 ). In this oper-
respectively and vo is load voltage. ating mode, the voltage of C1p and C2p capacitors and their energy
Duo to symmetry of circuit in Fig. 1, the following equations can are increased and the voltage of C1n and C2n and their energy are
be written: reduced. The inductors current and their energy are reduced, too.
vC,1p = vC,2p (3) For this operating mode, Eqs. (2) and (12) are valid. By substitut-
ing the value of vL,2n from (12) in (2), the following equation is
vC,1n = vC,2n (4) obtained:
iL,1p = iL,2p (5) vo = vo,n = Vi vC,1n vC,2n (14)
iL,1n = iL,2n (6) where vo,n denotes the negative value of output voltage.

Fig. 4. Operating modes in D1 + D2 1 state; (a) S1 and S2 are on; (b) S1 is on and S2 is off; (c) S1 is off and S2 is on.
 E. Babaei, E. Shokati Asl / Electric Power Systems Research 140 (2016) 722734 725

Fig. 5. Total voltage of inductors L1p and L1n .

Considering the voltage balance law and (10)(12), the follow-

ing equation can be written:

(vL,1p + vL,1n )dt
T
 
= (vL,1p + vL,1n )dt + (vL,1p + vL,1n )dt
(D2 +D1 1)T (2D2 D1 )T
 
vC,1p vC,2n vL,2p vL,2n Fig. 6. Variations curve of vo /2Vi versus D1 and D2 .
= Vi + + +
(D2 +D1 1)T
2 2 2 2
 vC,1p vC,2n vL,2n vL,2p

Considering Fig. 4(a), the currents through capacitors of C1p and

+ Vi + + + dt C1n in time interval t0 < t < t1 are calculated as follows:
2 2 2 2
 iC,1p = iL,2p , iC,1n = iL,1n (20)
+ (vC,1p + vC,2n )dt = 0 (15)
(2D2 D1 )T
Considering Fig. 4(b), the currents through capacitors of C1p and
C1n in time interval t1 < t < t2 are calculated as follows:
Considering Fig. 5, the above equation can be simplied as fol- vo,p vo,n
iC,1p = + iL,2p , iC,1n = + iL,1n (21)
lows: RL RL
(2Vi + vC,1p + vC,2n )(D2 + D1 1)T Considering Fig. 4(c), the currents through capacitors of C1p and
C1n in time interval t2 < t < t3 are calculated as follows:
(vC,1p + vC,2n )(2 D2 D1 )T = 0 (16)
iC,1p = iL,2p , iC,1n = iL,1n (22)

From (16), the following equation is obtained: By using (20)(22) and considering the current balance law, the
following equation can be written:
2Vi (D2 + D1 1)
vC,1p + vC,2n = (17)  T  t1 =t0 +(D2 +D1 1)T
2D2 + 2D1 3
iC,1p dt = iL,2p dt
It is noticeable that the voltage difference between positive and 0 t0 =0
negative voltage levels in conventional half-bridge is a constant  t2 =t1 +(1D2 )T  v  t3 =T
value (2Vi ) while this value in the proposed inverter may be vari- o,p
+ + iL,2p dt + iL,2p dt = 0 (23)
able. To obtain the voltage difference between positive and negative t1
RL t2
voltage levels (vo ), Eqs. (13) and (14) can be used as follows:
where RL denotes the output load resistance.
vo = vo,p vo,n = Vi + vC,1p + vC,2p + Vi + vC,1n + vC,2n (18) The current through inductor of L2p (iL,2p ) changes linearly in
time intervals t0 < t < t1 , t1 < t < t2 , and t2 < t < t3 . By using the average
Using (3), (4) and (17), the above equation can be simplied as value of iL,2p (IL,2p ), Eq. (23) can be simplied as follows [31]:
below:
vo,p
4Vi (D2 + D1 1) 2Vi IL,2p (D2 + D1 1)T + IL,2p (1 D2 )T (1 D2 )T
vo = 2Vi + = (19) RL
2D2 + 2D1 3 2D2 + 2D1 3
+ IL,2p (1 D1 )T = 0 (24)
Considering (19), the variations curve of D1 , D2 and vo /2Vi is
plotted in Fig. 6. In this gure, vo /2Vi is signicantly increased
when D1 + D2 is almost 1.5. It can be concluded that by choosing From (24), the value of vo,p is calculated as below:
proper values for D1 and D2 , the proposed inverter can produce
RL (3 2D2 2D1 )
wide range of voltage difference between positive and negative lev- vo,p = IL,2p (25)
1 D2
els in comparison with the conventional half-bridge inverter. When
vo /2Vi < 1, the inverter operates as step-down and otherwise it Similarly for iC,1n by using (20)(22) and considering the current
operates as step-up. By suitable control of switches, different wave- balance law, the following equation can be written:
forms of output voltage can be produced. For example, it is possible  T  t1 =t0 +(D2 +D1 1)T  t2 =t1 +(1D2 )T
to generate symmetric and asymmetric voltages in both buck and iC,1n dt = iL,1n dt + iL,1n dt
boost operation. The key waveforms of proposed inverter in second 0 t0 =0 t1
operating state for D1 + D2 1 and D2 > D1 are shown in Fig. 7(a) and  t3 =T v
for D1 + D2 1 and D1 > D2 are shown in Fig. 7(b). It is noticeable that +
o,n
+ iL,1n dt = 0 (26)
in conventional inverter, the positive and negative output voltages t2
RL
is limited to Vi and Vi , respectively. Fig. 7 shows the advantage of
the proposed topology in comparison with conventional topology The current through inductor of L1n (iL,1n ), changes linearly in
from this point of view. time intervals t0 < t < t1 , t1 < t < t2 and t2 < t < t3 . By using the average
726 E. Babaei, E. Shokati Asl / Electric Power Systems Research 140 (2016) 722734

Fig. 7. Key waveforms of proposed inverter in second operating state; (a) D1 + D2 1 and D2 > D1 ; (b) D1 + D2 1 and D1 > D2 .

value of iL,1n (IL,1n ), Eq. (26) can be simplied as follows: where VC,1p and VC,1n denote the average values of voltage across
vo,n C1p and C2p , respectively. IL,1p and IL,1n are the average values of
IL,1n (D2 + D1 1)T + IL,1n (1 D2 )T + (1 D1 )T current through L1p and L1n , respectively.
RL
At the following, the different operating modes of the proposed
+ IL,1n (1 D1 )T = 0 (27) inverter in symmetric operation are investigated.
Now, the value of vo,n is calculated as follows:
2.2.1.1. First operating mode
RL (3 2D2 2D1 )
vo,n = IL,1n (28) In this operating mode, S1 and S2 are on and all diodes are
(1 D1 )
off. This mode occurs twice in one period. The output voltage
It can be observed from (25) and (28) that the proposed inverter has zero value and as a result the proposed half-bridge inverter
produces positive and negative voltage levels with different ampli- can generate zero voltage at output. However, the conventional
tude. half-bridge inverter cannot produce zero voltage level. In the pro-
posed inverter with symmetric output voltage, since vL,2n = vL,2p
2.2. Operation of the proposed inverter with symmetric output and both vC,1p and vC,2n have low ripple and also same average
voltage values (VC,1p = VC,2n ), therefore considering (9), it can be concluded:
vL,2n vL,2p + vC,1p vC,2n
In the proposed inverter if D1 = D2 and D1 + D2 1, the output vo = 0 (31)
2
voltage waveform will be symmetric and the amplitude of vo,n and
vo,p will be equal. Due to symmetry of the proposed topology, the
2.2.1.2. Second operating mode
following equations can be written:
Considering (16), the following equation can be obtained for this
VC,1p = VC,1n = VC (29) operating mode:

IL,1p = IL,1n = IL (30) vo = vo,p = Vi + 2VC (32)

 E. Babaei, E. Shokati Asl / Electric Power Systems Research 140 (2016) 722734 727

2.2.1.3. Third operating mode

Considering (14), it can be written:

vo = vo,n = Vi 2VC (33)

Eqs. (32) and (33) show symmetry in output voltage in posi-

tive and negative half-periods. According to (17) and assuming that
D1 = D2 = D result:
1 2D
VC = V (34)
4D 3 i
where D is the duty cycle of switches and is related to duty cycle of
shoot-through zero state, DST , by the following equation:

DST = 2D 1 (35)

By substituting the value of D from (35) in (34) results:

DST
VC = V (36)
1 2DST i
From practical point of view to prevent sudden increase in
capacitor voltage, DST must be increased gradually.
By substituting the value of VC from (36) in (32), the value of vo,p
obtained as follows:
1
vo,p = V = BVi (37)
1 2DST i
where B denotes the voltage gain.
By substituting the value of DST from (35) in (37), the relationship
between vo,p in terms of D can be obtained as follows:

1
vo,p = V (38)
3 4D i
Simplifying (25) and with assumption of D1 = D2 = D it can be
written:
RL (3 4D)
vo,p = IL (39)
1D
Using (38) and (39), the value of IL can be calculated as follows:
1D
IL = Vi (40)
RL (3 4D)2
Substituting the value of D from (35) in (40), the relationship
between IL in terms of DST is obtained as follows:
1 DST Fig. 8. Waveforms of proposed inverter for D1 = D2 = D and D1 + D2 > 1.
IL = Vi (41)
2RL (1 2DST )2
The key waveforms of proposed inverter for D1 = D2 = D and By simplifying the above equation and using vL = L(diL /dt), it
D1 + D2 > 1 are shown in Fig. 8. It is noticeable that by considering can be written:
D1 = D2 = 0.5 the proposed inverter produces output voltage same
(1 DST )DST T
as the conventional inverter. Thus, the proposed inverter has high iL = V (43)
2L(1 2DST ) i
ability in producing voltage with various waveforms in addition to
keeping the conventional half-bridge inverter capabilities. where iL denotes the inductor current ripple, which decreases
by increasing the switching frequency and the value of inductors
2.2.2. Calculation of inductor current and capacitor voltage inductance.
ripples under symmetric output voltage
To have proper design of inductor and capacitor values in
2.2.2.2. Capacitor voltage ripple calculation. Considering
impedance network, calculation of inductor current and capaci-
iC = C(dvC /dt), we can write:
tor voltage ripples is necessary. Calculations of these ripples are
provided at following subsections. vC
IL = C (44)
(1 D)T
2.2.2.1. Inductor current ripple calculation. In the rst operating
mode, considering (1), (31) and (36) and assumption of D1 = D2 = D, By simplifying the above equation and substituting the value of
the voltage across inductor (vL ) is calculated as follows: D in (35), the following equation is obtained:

DST IL (1 DST )
vL = Vi + V (42) vC = T (45)
1 2DST i 2C
728 E. Babaei, E. Shokati Asl / Electric Power Systems Research 140 (2016) 722734

where vC denotes the capacitor voltage ripple, which decreases

by increasing the switching frequency and the value of capacitors
capacitance.
By substituting the value of IL from (41) in (45), vC is obtained
as below:

(1 DST )2
vC = Vi (46)
4RL fs C(1 2DST )2

2.2.3. Selection of the values of L and C

The ripples of capacitor voltage and inductor current effect on
the stability of inverters. To proper design the values of capaci-
tances, the allowable voltage ripple, xC %, can be used as follows:
vC
xC % = (47)
VC
By substituting the values of vC and VC from (46) and (36) in
(47), the value of capacitance is calculated as below:
Fig. 10. Equivalent circuit of the proposed converter considering the parasitic resis-
(1 DST )2 tances and the diodes and switches offset voltages.
C= (48)
4RL fs DST (1 2DST )xC %
For topology shown in Fig. 9, the voltage gain is calculated by
By the same way, the proper value of inductors with assumption
the following equation:
of allowable current ripple, xL %, is carried out. The allowable current
ripple is dened as follows: 1
B= (53)
1 (N + 1)DST
iL
xL % = (49)
IL Eq. (53) is the extension of Eq. (37). To calculate the average of
capacitors voltage, the following equation is used:
By substituting the values of IL and iL from (41) and (43) in
(49), the value of inductance is calculated as follows: DST
VC = V (54)
1 (N + 1)DST i
RL DST (1 2DST )
L= (50)
fs xL % 3. Conduction and switching losses calculation

2.3. Extension of the proposed topology
To reach higher voltage gain, more numbers of series impedance
networks can be used. In the series connection, the parallel induc-
tors of two impedance networks are replaced by one inductor
which reduce the size, weight and cost. The extension of the pro-
posed topology is shown in Fig. 9. According to this gure, N
impedance networks are in series in top and N impedance networks
are in series in bottom. The following equations are true for this
inverter:
L1p = L1n = L2p = L2n = = LNp = LNn = L(N+1)p = L(N+1)n
C1p = C1n = C2p = C2n = = C(2N1)p = C(2N1)n = C(2N)p = C(2N)n
According to Fig. 10, in order to calculate the losses of the
proposed inverter under symmetric output voltage the following
assumptions are considered:
The diodes are replaced by an ideal switch in series with a resistor
(rD ) and a voltage source.
The power electronic switches are considered by an ideal switch
in series with a resistor (rS ) and a voltage source (VF,S ).
The equivalent series resistors of inductors and capacitors are
considered by rL and rC , respectively.
The inductors, capacitors, switches and diodes are all the same.
(51)
The internal parallel capacitors of switching elements are very
small and the effect of them in power losses calculation is ignored.
The ripple of inductors current is ignored.
(52)
The conduction power losses of a switch (PCond,S ) are calculated
as follows:
 T
1 2
PCond,S = (VF,S iS + rS iS2 )dt = VF,S IL + rS I 2 (55)
T 0
1 DST L

The switching losses can be obtained by integrating of the prod-

uct of the voltage and current waveforms in turn-on and turn-off
switching transitions time intervals. Fig. 11 shows the current and
voltage waveforms of the switch during the turn on and off time
intervals. In this gure, td,on and td,off are delay times in beginning
of the turn-on and turn-off of the switches, respectively. Consider-
ing Fig. 11(a), the switch turn-on power loss (PSw,Son ) is calculated as

follows:
on 1 1
PSw,S = (2IL )(2BVi )tr,i fs + (2BVi )(2IL )tf,v fs = 2IL BVi ton fs (56)
2 2
where tr,i , tf,v and ton are the current rise time, the voltage fall time
Fig. 9. Extension of the proposed topology. and the turn-on time, respectively.
 E. Babaei, E. Shokati Asl / Electric Power Systems Research 140 (2016) 722734 729

Fig. 11. Current and voltage waveforms of the switch; (a) during turn-on; (b) during turn-off.

off ) is calculated
diode (Fig. 12), the diode turn-off power loss (PSw,D
as follows:
off 1 1
PSw,D = (BVi )(Irr )tb fs = BVi Irr tb fs (60)
6 6
where Irr is maximum reverse recovery current.
The diode turn-off occurs twice in a period. So, from (59) to (60),
the total power loss of both diodes (PD,Tot ) is obtained as follows:
 on off

PD,Tot = 4 PCond,S + PSw,D + PSw,D  4VF,D IL

8rD IL2 (2DST

2 2D
ST + 1) 2BVi Irr tb fs
+ + (61)
1 DST 3

The power loss of the capacitor (PrC ) is as follows:

 T 2
1 1 3DST + 4DST
PrC = rC iC2 dt = rC IL2 (62)
T 0
1 DST
Fig. 12. Current and voltage waveforms of the diode during turn-off.
Considering the existence of four capacitors in the proposed
inverter, the total power losses of four capacitors (PrC,Tot ) are
off ) is
Considering Fig. 11(b), the switch turn-off power loss (PSw,S obtained as follows:
2 )
4(1 3DST + 4DST
calculated as follows:
PrC,Tot = rC IL2 (63)
1 1 1 DST
off
PSw,S = (2IL )(2BVi )tr,v fs + (2BVi )(2IL )tf,i fs = 2IL BVi toff fs (57)
2 2 The power losses of inductors consists of core and winding
losses. Typically in PWM converters, the core power loss is negligi-
where tr,v , tf,i and toff are the voltage rise time, the current fall time
ble (PCore  0). The winding power loss (PrL ) depends on the winding
and the turn-off time, respectively.
resistance (rL ) and is calculated as follows:
From (55) to (57), the total power losses of two switches (PS,Tot )
are obtained as follows: PrL = rL IL2 (64)
 on off

PS,Tot = 2 PCond,S + PSw,S + PSw,S Considering the existence of four inductors in the proposed
 4rS IL

inverter, the total power losses of inductors (PrL,Tot ) are obtained
= 4BVi (toff + ton )fs + 2VF,s + IL (58) as follows:
1 DST
PrL,Tot = 4rL IL2 (65)
The conduction power loss of diode (PCond,D ) is calculated as Hence, from (58), (61), (63) and (65), the total power losses
follows: (PLoss ) in the proposed inverter is given by:
 T
1 2
2rD IL2 (2DST
2 2D
ST + 1) PLoss = PS,Tot + PD,Tot + PrC,Tot + PrL,Tot (66)
PCond,D = (VF,D iD + rD iD )dt = VF,D IL +
T 0
1 DST
(59) 4. Control method of the proposed inverter

To generate appropriate trigger pulses (as shown in Fig. 8), a

At turn-on, the diode can be considered as an ideal switch simple control method based on PWM technique is used. Fig. 13
because it turns on rapidly compared to the transients in the power shows the control method of generation of switches control signals.
circuit. So, the diode turn-on power loss is ignored (PSw,Don  0). According to this gure, a triangle carrier signal (vtri ) with frequency
However, at turn-off, considering the reverse recovery time (trr ) of of fs and minimum and maximum magnitudes of 0 pu and 1 pu is
730 E. Babaei, E. Shokati Asl / Electric Power Systems Research 140 (2016) 722734
Fig. 13. Control signal waveforms.
used. Also, two constant signals of VST1 and VST2 with the following
magnitudes are applied to determine shoot-through zero state:
VST 1 = DST , VST 2 = 1 DST
Moreover, a signal (u) with frequency of fs is required that is gen-
erated by comparison of zero value with a sinusoidal signal (vm (t))
with magnitude of 1pu and frequency of fs as follows:
If vm (t) > 0 u=1
If vm (t) < 0, u=0
As shown in Fig. 13, by comparison vtri with VST1 and VST2 , the
signals of h1 and h2 are achieved. Moreover, the new signals of ST1
and ST2 are extracted by the following logical expression:
ST1 = h1 u,
ST2 = h2 u
where means logical AND and u is NOT of u.
Finally, using (69), the trigger pulses (GS1 and GS2 ) are obtained
as follows:
GS1 = u ST1 = u (h1 u)
GS2 = u ST2 = u (h2 u)
where means logical OR.
5. Comparison of proposed inverter with conventional
topologies
By increasing the time interval of shoot-through zero state and
also increasing the numbers of series impedance networks, the
higher voltage gain can be obtained. The calculated and experi-
mented voltage gain of the proposed inverter in terms of DST is
Fig. 14. Variation of voltage gain versus N.
Fig. 15. Theoretical comparison of voltage gain in proposed and conventional
topologies.
shown in Fig. 14. For example, for N = 1 and DST = 0.15 the voltage
gain is 1.43. This value for N = 2 and in same duty cycle of shoot-
through zero state is 1.82. By increasing the value of N, the value of
voltage gain is increased. For example, for N = 3 and N = 4, the values
(67) of voltage gain are 2.5 and 4, respectively.
The equations of voltage gain and voltage stress across
the capacitors and also the number of required components
for the proposed inverter and the conventional topologies in
[5,13,14,18,2224] are given in Table 1. In this table, n is the number
of inductors in given topology in [24]. Fig. 15 shows the theoretical
(68) variation of voltage gain versus DST for the proposed and conven-
tional topologies. According to this gure, by increasing the number
of series networks, the voltage gain of the proposed inverter can be
higher than the conventional topologies. For instance for DST = 0.2,
the voltage gain in the proposed topology with N = 3 is 5, while this
value for LZ-source inverter presented in [24] with n = 3 is 1.75.
(69) This value for ZSI [5] and CFSI [23] is 1.67. The voltage gain for
switched boost inverter [22] and switched-inductor ZSI [18] is 1.33
and 3, respectively. Among all of these, the proposed inverter with
N = 3 has highest voltage gain.
Fig. 16 shows the theoretical variation of capacitors voltage
(70) stress versus DST for proposed and conventional topologies. Accord-
ing to this gure, the capacitors voltage stress in the proposed
(71)
topology is smaller than the conventional ones. This feature has
various advantages such as reduction in cost due to reducing in
rating value of capacitors. For example in DST = 0.15, for proposed
inverter with N = 4, the value of VC /Vi is 0.6, which is less than the
calculated value 1.21 for conventional ZSI [5] and SBI [22]. This
value for CFSI [23] and switched-inductor ZSI [18] is 1.43 and 1.55,
respectively. This ratio is higher than the calculated ratio for pro-
posed inverter. According to Fig. 16, it is evident that the capacitors
voltage stress for proposed inverter with N less than 4 is smaller
amount.
 E. Babaei, E. Shokati Asl / Electric Power Systems Research 140 (2016) 722734 731

Table 1
The equations of B and VC /Vi for proposed and single-phase conventional topologies.

SL-ZSI [18] SZSI [13] QZSI [14] ZSI [5] LZSI [24] SBI [22] CFSI [23] Extension of Proposed
the proposed topology in
topology in Fig. 1 (N = 1)
Fig. 9
1+DST 1 1 1 1+(n1)DST 1DST 1 1 1
B 13DST 12DST 12DST 12DST 1DST 12DST 12DST 1(N+1)DST 12DST
VC 1DST DST 1DST DST 1DST 1DST 1 DST DST
Vi 13DST 12DST 12DST
and 12DST 12DST
12DST 12DST 1(N+1)DST 12DST
Number of inductors 4 2 2 2 n 1 1 2N + 2 4
Number of capacitors 2 2 2 2 0 1 1 4N 4
Number of transistors 4 4 4 4 4 5 5 2 2
Number of diodes 11 5 5 5 3n + 1 6 6 2N + 2 4

DST = 0.2, xL = 7.3%, xC = 1.9%. By using (48) and (50), the values of
inductances and capacitances are obtained 2.4 mH and 470 F,
respectively.

6.1. Simulation results

To verify the accuracy of equations and theoretical analysis, in

Fig. 16. Theoretical comparison of capacitor voltage stress between the proposed
and conventional topologies.
6. Simulation and experimental results
In this section to verify the accuracy of the proposed inverter,
the simulation results by using PSCAD/EMTDC software and exper-
imental results are provided. Designed values of inductor and
capacitor corresponding to allowable current ripple (xL %) and
voltage ripple (xC %) are carried out. The following values of
parameters are considered: Vi = 20 V, N = 1, RL = 14.66 , fs = 10 kHz,
simulation all elements are assumed ideal. The simulation results
for the proposed inverter are shown in Fig. 17. Fig. 17(a) shows
current of inductors. According to this gure, the current ripple
of inductors is 0.113 A. This value is in agreement with the cal-
culated value of 0.111 A from (43) with 1.8% error. The inductors
average current is 1.512 A which is close to the calculated value of
1.516 A from (41) with 0.26% error. Fig. 17(b) shows the voltage
across inductors which has value of 26.65 V during time interval
shoot-through zero state and in another time interval has value
of 6.64 V. These values are in agreement with 26.67 V and 6.67
obtained from theoretical equations with 0.075% and 0.45% errors,
respectively. According to Fig. 17(c), voltage across capacitors has
average value of 6.63 V and ripple of 0.127 V. These values have
good agreement with values 6.67 V and 0.129 V obtained from
(36) and (46) with 0.60% and 1.55% errors. Fig. 17(d) shows the
capacitors currents. According to this gure, the values of currents
in different operating modes have good agreement with the

Fig. 17. Simulation results for D1 = D2 = 0.60; (a) inductors current; (b) inductors voltage; (c) capacitors voltage; (d) capacitors current; (e) output voltage.
732 E. Babaei, E. Shokati Asl / Electric Power Systems Research 140 (2016) 722734
Fig. 18. Experimental prototype of the proposed inverter.
calculated values. Fig. 17(e) shows the output voltage. The output
voltage has three voltage levels: positive, negative and zero lev-
els. The values of positive and negative voltage levels are 33.24 V
and 33.24 V, respectively. These values have very small difference
with the values of 33.33 V and 33.33 V obtained from (33) and (37).
In this case, the error is 0.27%. As the simulation results show, there
is good agreement between the simulation and calculated values.
6.2. Experimental results
Fig. 18 shows the experimental prototype of the proposed
inverter. The equivalent series resistance of inductors is 0.4 . The
type of power MOSFETs and diodes are IRF840 and MUR1560G,
respectively.
Fig. 19. Experimental results for D1 = D2 = 0.60; (a) inductors current; (b) inductors voltage; (c) capacitors voltage; (d) capacitors current; (e) output voltage.
Fig. 19(a) shows the current of inductors. According to this g-
ure, the average current of inductors is about 1.4 A, which is close
to value of 1.516 A obtained from (41) and the error is 7.65%. The
inductors current ripple is about 0.120 A. This value has little dif-
ference with value of 0.111 A calculated by (43) and the error is
8.11%. Fig. 19(b) shows the voltage across inductors. According
to this gure, when S1 and S2 are on simultaneously, the voltage
across inductors is positive with value about 25 V and otherwise it
is negative with value about 6 V. These values correspond to val-
ues of 26.67 V and 6.67 V obtained from theory and the errors are
6.26% and 10.04%, respectively. Fig. 19(c) shows capacitors volt-
age waveform. According to this gure, the average voltage across
capacitors is 5.5 V. The calculated value for this parameter by using
(36) is 6.67 V. Fig. 19(d) shows the capacitors current waveform.
Fig. 19(e) shows the output voltage waveform. As expected, this
gure consists of positive, negative and zero levels. The maximum
and minimum values of the output voltage are about +31.5 V and
31 V which has a little difference with obtained values of 33.33 V
and 33.33 V from (32) and (33), respectively. The errors are 5.49%
and 6.99%, respectively. The reason of little difference between the
experimental and theoretical results is that the non-ideal elements
are used in laboratory prototype.
The experimental results for D2 = D1 = 0.5 are shown in Fig. 20.
Applied pulses to gates of switches are shown in Fig. 20(a), which
have 180 phase shift. Fig. 20(b) shows the output voltage wave-
form. According to this gure, the output voltage waveform is same
as the output voltage waveform of the conventional half-bridge
inverter. In this case, the positive voltage level is about 19.5 V, which
coincides with value of 20 V obtained from calculation and the error
is 2.5%.
As the experimental results show, there is good agreement
between the experimental results and calculated values. To give a
 E. Babaei, E. Shokati Asl / Electric Power Systems Research 140 (2016) 722734 733

Fig. 20. Experimental results for D2 = D1 = 0.5; (a) applied pulses to S1 and S2 ; (b) output voltage.

Table 2
Comparison between mathematical analysis, simulation and experimental results for the proposed inverter.

Calculated Simulated Simulation error Experimented Experimental error

Average current of inductors 1.516 A 1.512 A 0.26% 1.4 A 7.65%

Current ripple of inductors 0.111 A 0.113 A 1.8% 0.12 A 8.11%
Voltage across inductors in ST zero state 26.67 V 26.65 V 0.075% 25 V 6.26%
Voltage across inductors in non-ST 6.67 V 6.64 V 0.45% 6 V 10.04%
Average value of voltage across capacitors 6.67 V 6.63 V 0.60% 5.5 V 11.54%
Voltage ripple of capacitors 0.129 V 0.127 V 1.55% 0.14 V 8.52%
Positive level of output voltage 33.33 V 33.24 V 0.27% 31.5 V 5.49%
Negative level of output voltage 33.33 V 33.24 V 0.27% 31 V 6.99%

more clear insight about the performance of the proposed inverter,
the theoretical, simulation and experimental results are summa-
rized in Table 2.
7. Conclusion
In this paper, a new topology for half-bridge Z-source inverter
was proposed. The different operating modes of the proposed
topology were studied. In addition, the ripples of capacitors voltage
and inductors current were calculated and by using these results
the proper values of capacitances and inductances were obtained.
The proposed inverter generates high voltage gain. For example,
for DST = 0.2 the voltage gain of the proposed inverter is 1.67. Other
advantages of the proposed half-bridge inverter are low voltage
stress of capacitors and producing zero voltage level at output. It is
noticeable that in the conventional half-bridge inverter, it is impos-
sible to generate zero voltage at output. The proposed topology
also can generate symmetric and asymmetric voltages with differ-
ent amplitude during positive and negative half-cycles. In addition,
the proposed half-bridge inverter contains all characteristics of the
conventional half-bridge inverter. Coincidence of simulation and
experimental results with results obtained from theoretical recon-
rms the performance of the proposed topology.
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