2015 IEEE International Conference on Cluster Computing
An FPGA-based Accelerator for Neighborhood-based Collaborative Filtering
Recommendation Algorithms
Xiang Ma, Chao Wang, Qi Yu, Xi Li, Xuehai Zhou
School of Computer Science
University of Science and Technology of China, Hefei, China
Email: {maxiang, yuiq1123}@mail.ustc.edu.cn; {cswang, llxx, xhzhou}@ustc.edu.cn
AbstractNeighborhood-based Collaborative Filtering (CF) is
a kind of techniques in the field of recommendation algorithms
and has been widely used in lots of personalized recommender
systems. In the big data era, the increasing data amounts make
these CF recommendation algorithms become time-consuming
and energy-wasted. At present, Cloud computing and Graphic
Processing Unit (GPU) are the two major platforms to accele-
rate CF algorithms. However, both platforms exist some re-
markable shortcomings such as efficiency and power. To solve
these problems, in our work, we investigate three neighbor-
hood-based CF algorithms and design a general and flexible
accelerator for them based on Field Programmable Gate Array
(FPGA). This accelerator cooperates with host CPU and could
accelerates primary time-consuming parts that these algo-
rithms share. Experimental results show that our accelerator
could significantly improve the acceleration efficiency with the
affordable hardware cost and less energy consumption.
Keywords-accelerator; FPGA; recommendation algorithm;
neighborhood-based collaborative filtering; heterogeneous
I. INTRODUCTION
Neighborhood-based Collaborative Filtering (NCF) [1] is
a primary kind of techniques in the field of recommendation
algorithms and has been widely used in a wide range of per-
sonalized recommender systems. However, due to the prop-
erties of data-intensive and compute-intensive, NCF become
time-consuming when dealing with vast amounts of data.
Thus, In order to guarantee the real-time interaction require-
ment between users and recommender systems, it is very
necessary to accelerate the process of NCF algorithms.
Currently, cloud computing and GPU are the two major
platforms that used to accelerate NCF algorithms. However,
both platforms exist some remarkable shortcomings to be
overcome: regarding cloud platform, the build and mainten-
ance cost are relatively high, and actually the efficiency of
each common CPU-based computing node may not satisfy-
ing; as for GPU, although the efficiency is usually much
better than a cloud computing node, the energy consumption
of each GPU board is quite outstanding.
In order to improve the efficiency of CPU based compu-
ting node for NCF algorithms and reduce the runtime energy
consumption at the same time, in this paper, we investigate
three common neighborhood-based CF algorithms: User-
based CF [2], Item-based CF [3] and SlopeOne [4], and pro-
pose a general accelerator architecture based on FPGA for
them. This accelerator acts as a co-processor and could acce-
lerate prime time-consuming parts that these algorithms
share. To evaluate our design, we implement a prototype
978-1-4673-6598-7/15 $31.00 2015 IEEE
DOI 10.1109/CLUSTER.2015.79
using Xilinx ZYNQ SOC and take several experiments on it.
Experimental results demonstrate the accelerator could im-
prove the speedup and acceleration efficiency with the af-
fordable hardware cost and less energy consumption.
II. NEIGHBORHOOD-BASED COLLABORATIVE FILTERING
User-based CF, Item-based CF and SlopeOne are three
representative NCF recommendation algorithms and all
could be divided into the training and prediction phases. For
training phase, user CF accepts user vectors to calculate all
similarities for each two users; item CF/slopeone accepts
item vectors to calculate similarities/differences for each two
items. As to prediction phase, given an active user vector, all
algorithms use the information from training phase to predict
those items ratings which the user have not rated. User vec-
tor contains all the items IDs and ratings that the user has
rated and item vector contains all the users IDs and ratings
who has rated this item.
There are many similarity metrics such as Jaccard Coef-
ficient, Cosine Similarity and Pearson Correlation. Most
metrics do calculations on all the IDs and ratings that both
two vectors share, same with SlopeOne. These calculations
mainly involve operations such as multiplication or subtrac-
tion on two vectors followed by an accumulation operation.
It could be seen that the three algorithms have large in
common and slight differences on calculation. Thus we
could build a general and flexible accelerator with all needed
function modules and using instructions to compose these
fine-grained functions into different algorithms.
III. ACCELERATOR ARCHITECTURE
A. Overall architecture of CF accelerator
Accelerator and Peripherals
CF Accelerator
Instruction Buffer
Execution
Control Interconnect
Unit 1
DMA
Host Execution DDR
Unit 2
CPU Accelerator RAM
Controller
Execution
Unit 3
Execution
Unit 4
Data Bus
Figure 1. The overall architecture of NCF accelerator.
494
 The overall architecture of NCF accelerator is illustrated
in Fig. 1. As we can see, NCF accelerator has an instruction
buffer, a controller and many execution units and works in
SIMD mode: all execution units execute same instruction on
different input vectors. When utilizing this accelerator, host
CPU first informs DMA to transfer the instructions to in-
struction buffer, then accelerator reads instructions one by
one and execute the corresponding operations such as load,
store or vector accumulation.
B. Execution Units architecture
Execution Units architecture is illustrated in Fig. 2. In
each Execution Unit, there are I/O module, calculation unit,
vector operation unit and vector update unit. All modules
and units need instructions to execute certain function.
Input Module executes load instructions to read two vec-
tors from DMA by stream and put them into input X and Y
buffer. Besides, when reading the second input vector, input
module could do the vector intersection operation at the
same time to put the shared elements of two vectors into
temp X and Y buffers. As to training phase, output module
executes scalar store instructions to put scalars such as simi-
larity value which stored in result scalars back to DMA; for
prediction phase, output module executes corresponding
vector store instructions to send output vector which stores
all the prediction values of each item back.
Vector operation unit does operations such as multiplica-
tion or subtraction on each element of two vectors and ac-
cumulates them and then stores the accumulation value into
corresponding scalar buffer. It is implemented as several
operation-adder trees to work efficiently. Calculation unit
usually calls vector operation unit first to get needed scalar
values and then do the rest special calculations for different
metrics. Finally the similarity or difference value is also
stored in result scalar buffer. Vector update unit only works
in prediction phase, it does the weighed-accumulation and
accumulation operation for each item of every input vector.
The weighed-accumulation values for each item are stored
in output buffer and the accumulation values stored in temp
buffer Z. After dealing with all input vectors, update unit
executes division on each item of output and temp Z buffers
and then stores final prediction values in output buffer.
Input Module
Output: Result Scalars
Accelerator Controller
Central Storage
Temp: Vector X
Input: Vector X
Input: Vector Y
Calculation
Vector Operation Unit
Unit
Operation-
Adder Tree
... Operation-
Adder Tree
Figure 2. The architecture of Execution Unit.
IV. EXPERIMENT
Figure 3. Speedups of accelerator compared with Intel Xeon E5
We build an accelerator prototype on ZYNQ platform of
DIGLENT ZedBoard. ZYNQ is an embedded SOC which
consists of two sections, processing system (PS) and pro-
grammable logic (PL). PS mainly integrates two ARM Cor-
tex-A9 cores and PL is full of FPGA logic. Our prototype
exists in PL and it has one execution unit. The execution
unit has one 16-sized operation-adder tree in vector opera-
tion unit and 16 PEs in vector update unit, and the calcula-
tion unit support Jaccard, Cosine, Pearson and SlopeOne
metrics. The prototypes frequency is 101MHz. Comparison
platform is a 2.3GHz Intel Xeon E5 processor and all algo-
rithms run in single-thread mode.
We choose MovieLens-1M [5] as test dataset. There are
3883 movies and 6040 users. Experimental results are
shown in Fig. 3. For prediction, the speedup is the average
value. If we could add more operation-adder trees and PEs
in every execution unit, the speedups would be better.
Moreover, the power of our NCF accelerator prototype is
237mW, which is far less than the Xeon and other CPU/GPU.
The maximum used resource is LUT, which occupied 75.9%
of the totals. As to other resources, the usage is almost 41.8%
on average.
V. CONCLUSION
In this paper, we design an accelerator based on FPGA as
DMA the co-processor to accelerate NCF recommendation algo-
rithms. Experimental results show that this accelerator could
Output Module
Execution significantly improve speedup with the affordable hardware
Unit cost and less energy consumption.
REFERENCES
[1] X. Su and T. M. Khoshgoftaar, "A survey of collaborative filtering
Temp: Vector Y
Temp: Vector Z
Output: Vector
techniques," Advances in artificial intelligence, vol. 2009, p. 4, 2009.
[2] D. Goldberg, D. Nichols, B. M. Oki, and D. Terry, "Using
collaborative filtering to weave an information tapestry,"
Communications of the ACM, vol. 35, pp. 61-70, 1992.
[3] B. Sarwar, G. Karypis, J. Konstan, and J. Riedl, "Item-based
collaborative filtering recommendation algorithms," in Proceedings of
the 10th international conference on World Wide Web, 2001, pp. 285-
Vector Update Unit 295.
PE PE ... PE [4] D. Lemire and A. Maclachlan, "Slope One Predictors for Online
Rating-Based Collaborative Filtering," in SDM, 2005, pp. 1-5.
[5] http://grouplens.org/datasets/movielens/.
495