Proceedings of 2009 ,(((Student Conference on Research and Development (SCOReD 2009),

16-18 Nov. 2009, UPM Serdang, Malaysia

TMS320F2812 Digital Signal Processor (DSP)

Implementation of DPWM
M. F. N. Tajuddin1, N. H. Ghazali2, M. F. Mohammed3, B. Ismail4, Z. M. Isa5, T. C. Siong6 and N. Ghazali7
7

1-6
School of Electrical System Engineering, Universiti Malaysia Perlis, 01000, Perlis, Malaysia
Faculty of Computer Science and Information Technology, Universiti Teknologi Malaysia, 81310 Johor, Malaysia
faridun@unimap.edu.my, m.fayzul@.unimap.edu.my, baha@unimap.edu.my

AbstractThis paper presents the programming and use of

TMS320F2812 Digital Signal Processor (DSP) in generating the
Digital Pulse Width Modulation (DPWM). The structure and
functions of eZdsp 2812 board used in this work is explained
briefly and the steps need to be taken for the programming is
explain in detail to control the frequency, the duty cycle and dead
band of the generated PWM. The PWM generated by DSP from
programming can be used to control and regulate power
electronic converters.
Keywords-Digital Signal Processor (DSP); PWM

I.

INTRODUCTION

With the growth of the Power Electronic (PE) converters,

diverse new requirements for using the electronic converters
have been put forward. In this work, an advanced electronic
processor, Digital Signal Processor (DSP) developed by Texas
Instruments Inc. has been used, whose main circuit is made up
of Pulse Width Modulation (PWM), Analog-to-Digital
Converter (ADC) and Input-Output (I/O) peripherals. This
circuit mainly used as a controller for the power electronic
converters. The combination of analog control and digital
control can make the design and the debugging of the control
system easy, and also can improve the reliability of the whole
system [1].
A Digital Signal Processor is a special-purpose CPU
(Central Processing Unit) that provides ultra-fast instruction
sequences, such as shift and add, and multiply and add, which
are commonly used in math-intensive signal processing
applications [1]. DSP processor architectures are evolving to
meet the changing needs of DSP applications. The architectural
homogeneity that prevailed during the first decade of
commercial DSP processor has given way to reach diversity.
Some of the forces driving the evolution of DSP processors
today include the perennial push for increased speed, decrease
cost, all of which enable DSP processor to better meet the
needs of new and existing applications [2].
II.

INTRODUCTION BASIC TMS320 ARCHITECTURES

Digital signal processor is fast arithmetic operations and

high throughput to handle mathematically intensive algorithms
in real time. In the TMS320 family, this is accomplished by
using the following basic concepts; Harvard architecture,
extensive pipelining, dedicated hardware multiplier, special
DSP instructions and fast instruction cycle [2, 3, and 6]. These
concepts are designed into the TMS320 digital signal
processors to handle the vast amount of data characteristic of
DSP operations and to allow most DSP operations to be

executed in a single-cycle instruction. Furthermore, the

TMS320 processors are programmable devices, providing the
flexibility and ease of use of general purpose microprocessors.
The TMS320 utilizes a modified Harvard architecture for
speed and flexibility. In a strict Harvard architecture, the
program and data memories lie in two separate spaces,
permitting a full overlap of instruction fetch and execution. The
TMS320 family's modification of the Harvard architecture
further allows transfer between program and data spaces,
thereby increasing the flexibility of the device. This
architectural modification eliminates the need for a separate
coefficient ROM and also maximizes the processing power by
maintaining two separate bus structures (program and data) for
full-speed execution [2, 3].
III.

DIGITAL PULSE WIDTH MODULATION

PWM are implemented using both analog and digital

control schemes. Pulse width modulator produces a logic
signal, which is periodic with frequency, and has duty cycle,
d. The signal is used to control the duration over which power
transistor or switch in the converter are switched on. The input
to the pulse width modulator is an analog control signal. The
modulator manipulates the analog control voltage to produce
the duty cycle in proportion to it [2].
With the recent advances in the semi-conductor industry,
microprocessors and digital signal processors are used in
producing digital PWM. A PWM controller using DSP is
shown in Fig. 1. In this control scheme the parameters of
interest like the output voltage, input voltage and current are
fed into a set of preamplifiers and digitized using an A/D
converter. These parameters are manipulated suitably in the
digital signal processor where the required numerical values
namely  , , , corresponding to switching period, on-time
for the converter switches and start time for the A/D signal
conversion are generated. The calculations of these values are
based on a set of gain equations. The architecture of this
approach is shown in Fig. 1.
Pulse width modulation is used to reduce the total power
delivered to a load without resulting in loss, which normally
occurs when a power source is limited by a resistive element.
The underlying principle in the whole process is that the
average power delivered is directly proportional to the
modulation duty cycle. If the modulation rate is high, it is
possible to smooth out the pulse train using passive electronic
filters and recover an average analog wave form [5]. Pulse
width modulation is widely used in voltage regulators. It works

978-1-4244-5187-6/09/$26.00 2009 IEEE

142

generate a PWM output with a GP timer, a continuous up- or

up-/down counting mode can be selected. Edge-triggered or
asymmetric waveform as shown in Fig. 2 is generated when the
GP timer is in continuous up-counting mode. Centered or
symmetric PWM waveforms shown in Fig. 3 are generated
when a continuous-up/-down mode is selected.

by switching the voltage to the load with the appropriate duty

cycle; the output will maintain a voltage at the desired level.

To generate a PWM signal, an appropriate timer is needed

to repeat a counting period that is the same as the PWM period.
A compare register is used to hold the modulating values. The
value of the compare register is constantly compared with the
value of the timer counter. When the values match, a transition
(from low to high, or high to low) happens on the associated
output. When a second match is made between the values, or
when the end of a timer period is reached, another transition
(from high to low or low to high) happens on the associated
output. In this way, an output pulse is generated whose on (or
off) duration is proportional to the value in the compare
register. This process is repeated for each timer period with
different (modulating) values in the compare register. As a
result, a PWM signal is generated at the associated output.

Figure 1. Architecture of Digital PWM Using Digital Signal Processor [4]

IV.

PWM GENERATION IN TMS320F2812

The generation of the PWM in the TMS320F2812 DSP is

mainly controlled by the Event Manager (EV). The eventmanager (EV) modules provide a broad range of functions and
features that are particularly useful in motion control and motor
control applications. The EV modules include general-purpose
(GP) timers, full-compare/PWM units, capture units, and
quadrature-encoder pulse (QEP) circuits. The two EV modules,
EVA and EVB, are identical peripherals, intended for multiaxis/motion-control applications. Each EV is capable of
controlling three Half-H bridges, when each bridge requires a
complementary PWM pair for control. Each EV also has two
additional PWMs with no complementary outputs.
The PWM waveform generation capability of each event
manager module (A and B) is summarized as follows [6, 7, and
8]:
x

Five independent PWM outputs, three of which are

generated by the compare units; the other two are
generated by the GP timer compares plus three
additional PWM outputs, dependent on the three
compare unit PWM outputs.

Figure 2. GP Timer Compare/PWM Output in Up-Counting Mode.

To set up the GP timer for the PWM operation, the following

steps need to be done:
1.

Programmable dead-band for the PWM output pairs

associated with the compare units.

Set up TxPR according to the desired PWM (carrier)

period

2.

Minimum dead-band duration of one device clock

cycle.

Set up TxCON to specify the counting mode and

clock source, and start the operation

3.

Load TxCMPR with values corresponding to the online calculated widths (duty cycles) of PWM pulses

Minimum PWM pulse width and pulse width

increment/decrement of one clock cycle.

Programmable generation of asymmetric, symmetric,

and space vector PWM waveforms.

V.

GENERATION OF PWM OUTPUT USING THE GENERAL

PURPOSE (GP) TIMERS

Both asymmetric and symmetric PWM waveforms can be

generated by every compare unit on the EV module. In
addition, the three compare units together can be used to
generate 3-phase symmetric space vector PWM outputs. To

Figure 3. GP Timer Compare/PWM Output in Up-/Down-Counting Modes.

143

The period valuue is obtained by

b dividing thee desired PWM
M
period by the perriod of the GP
G timer inpput clock, andd
subtraacting one from
m the resulting number when the continuouss
up-co
ounting mode is selected to generate asym
mmetric PWM
M
waveeforms. When the
t continuouss up-/down-couunting mode iss
selectted to generatee symmetric PW
WM waveform
ms, this value iss
obtain
ned by dividing the desired PWM
P
period by
y two times thee
period of the GP timer input clock. The GP
P timer can bee
he previous exxample. Duringg
initialized the samee way as in th
mer compare register
r
is consstantly updatedd
run tiime, the GP tim
with newly determ
mined compare values correspponding to thee
newly
y determined duty
d cycles.
VI.

Comp
pare register vaalue calculationn:





mple, let say that

t
the desireed frequency vvalue is 30
For exam
kHz with
h 50% Duty Cyycle:


= 22500


  

PR
ROGRAMMING OF TMS320F2
2812

Fo
or the prograamming, softw
ware called Coode Composerr
Studiio (CCS) will be use. This
T
softwaree comes withh
TMS320F2812 Dig
gital Signal Prrocessor and especially
e
beenn
use for
f design the programming and uploadin
ng the program
m
into the
t hardware (eZdsp
(
2812 Board)
B
[6, 7]. CCS 3.0 weree
desig
gned for the Teexas Instrumen
nts TMS320Cx
x digital signaal
proceessor (DSP) pllatforms, The CCS
C
applicatioon provides ann
integrrated environnment that comprises the
t
followingg
capab
bilities [2]:
x

Integrated development environment with

w an editorr,
debugger, project
p
manageer, profiler andd etc.

C/C++ com
mpiler, assembbly optimizer an
nd linker (codee
generation
n tools)

Simulator

Real-Timee Data Exchannge (RTDXtm

m) between thee
Host and Target
T

Real-time analysis and daata visualizatioon

 


Figure 4. Period T
Time and Comparee value setting in CCS.
C

The calculated
c
Periood Time and Compare
C
value need to be
set in theeir respective registers. Fig. 4 shows the registers that
need to be
b set, in order to get the requuired PWM ouutput in the
main proogram. Fig. 5 sshows the corrresponding PW
WM output
generated
d by the calculated period tiime and compare values.
From thee figure, it is sseen that the generated
g
PWM
M output is
exactly thhe same as the desired frequeency and the duuty cycle.

Figurre 5. PWM outpuut by DSP with Freequency=30 kHz annd Duty

Cycle=50%

B. Generration of Deadd Band

The deead-band unit is
i designed to prevent
p
an oveerlap under
any operaating situation between the tuurn-on period oof the upper
and lower devices coontrolled by the two PWM
M outputs
d with each compare uniit. This incluudes those
associated
situationss where you have
h
loaded a dead-band vaalue greater
than that of the duty cyccle, and when the
t duty cycle is 100% or
WM outputs asssociated with a compare
0%. As a result, the PW
unit do noot reset to an innactive state att the end of a period when
dead bandd is enabled forr the compare unit.
u

od Time registeer value calculaation:

Perio

(1))

w
where,




= 12550

A. Fix
F Frequency And
A Duty Cyclle PWM
The frequency and
a the duty cyycle generated by DSP can bee
contrrol by following the steps desscribed in Section V. In orderr
to crreate a PWM Signal with specific
s
frequeency and dutyy
cyclee, the value of Period Time and
a Compare that
t
need to bee
writteen in the proogramming reegister is firsst need to bee
calcu
ulated. In ord
der to calculaate the valuees, the properr
SYSC
CLKOUT freequency need
ds to be knnown. In thiss
TMS320F2812 DSP
P application, its SYSCLKO
OUT frequencyy
0MHz. To gen
nerate the PWM
M with specificc frequency andd
is 150
duty cycle, the follo
owing equationns are used exteensively.



(3)

(2))

144

Thee DSP controoller TMS320F

F2812 has a programmablee
dead band generatoor, to insert a dead
d
band betw
ween two PWM
M
uts (PWM1&
&2, PWM3&4, PWM5&66, PWM7&8,
outpu
PWM
M9&10, and PWM11&12).
P
The appropriaate dead bandd
betweeen two PWM outputs can bee inserted usingg the DBTCON
N
registter. Fig. 6 show
ws the program
mming that need
ds to be done too
contrrol the Dead Band
B
for the PW
WM output. The
T example off
the PWM wavefform generated by the correspondingg
own in Fig. 7:
progrramming is sho

Figuure 10. Programmiing to enable the chhanging variable inn DSP.

Figuure 6. Dead Bandd control setting.

Figurre 11. Example PW

WM output by DSP
P via keyboard inpput with
Freequency=20 kHz, Duty Cycle=50% and Dead Band=66.4s

V
VII.

CONCLUS
SION

The TMS320F2812
T
Digital Sign
nal Processor has high
capabilityy usage in pow
wer electronic converter.
c
To achieve
a
this
target, the programmingg using Code Composer
C
Studdio need to
be explorre in detail so that the desireed PWM wavee form can
be easily control by useer.
Figurre 7. Example off a figure caption Example
E
PWM outtput by DSP with
Dead Band = 4.4 s.

REFERENCESS
[1]

Figure 8.

[2]

C. G
Generation of Variable
V
Frequency and Dutyy Cycle with
D
Dead
Band Con
ntrol
By
y setting the programming
p
code,
c
the variaable frequencyy
and Duty
D
Cycle PW
WM can be gen
nerated. The changing
c
of thee
frequ
uency and dutyy cycle can be made via key
yboard input orr
analo
og input. The variable can be change usiing the Watchh
Regisster in CCS as shown in Fig. 8. Fig. 9 show
ws the program
m
codess need to be ad
dded within thhe while loop in
i the program
m
to maake it possiblee to change thhe frequency, duty
d
cycle andd
Dead
d Band through
h variables. Thhe example PW
WM waveform
m
generrated by the pro
ogramming is shown in Fig. 10.

[3]
[4]

[5]
[6]
[7]
[8]

Figure 9. Register Watcch Window in CCS

S.

145

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to thhe Latest Develo
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TMS3320F28x Event Manager (EV) Perippheral Reference Guide. Texas
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