Aldec Webinar

Created by

Jerry Kaczynski

UVM for Hardware Designers

Rev. 1.2

Agenda

www.aldec.com

Introduction
Basic Ideas
UVM
Conclusion

2012 Aldec, Inc.

www.aldec.com

2012 Aldec, Inc.

What Is UVM?

UVM Universal Verification Methodology is a library of

SystemVerilog classes and other utilities that simplifies creation
of advanced, reusable verification environments.
UVM requires at least basic understanding
of OOP and TLM the better your understanding,
the more you can squeeze from UVM.
Typical hardware designer can quickly learn
enough UVM to:
Use verification IP written by others.

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Work with verification engineers on creation of new testbenches.

Creating advanced UVM testbenches requires slightly more

knowledge and practice

2012 Aldec, Inc.

Who Needs UVM?

UVM works best in case of:

Bus-Based
High-Traffic

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System-Level Designs.

UVM is the most efficient when verification

procedures require randomization and/or functional coverage.

UVM can be adapted to handle other classes of design,

but may not be the best solution in those cases.

UVM uses mainly black-box verification approach, so it should

work with designs written in any language (as long as the
simulator supports all involved languages).

2012 Aldec, Inc.

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Required to understand UVM description

2012 Aldec, Inc.

OOP: Simple Class and UML Diagram

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class Base_Counter;
int contents;
function new();
contents = -7;
endfunction
task clear();
contents = 0;
endtask
task count();
contents += 1;
endtask
function int show();
return contents;
endfunction
endclass

2012 Aldec, Inc.

property
methods

Class Inheritance Example

package oop;
class Base_Counter;
int contents;
function new();
contents = -7;
endfunction
task clear();
contents = 0;
endtask
task count();
contents += 1;
endtask
function int show();
return contents;
endfunction
endclass
class Load_Counter extends Base_Counter;
task load(input int val);
contents = val;
endtask
endclass

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endpackage

2012 Aldec, Inc.

child class adds method

TLM Ports

TLM components work at 2 levels:

Produce or consume data via transactions.
Initiate or execute transactions.

Data flow (from producer to consumer) is represented by arrows on

TLM diagrams.
Control flow is represented by port shape:

Transaction initiator has square-shaped port:

Transaction executor has circle-shaped export:
(sometimes called import=implementation port)

Some components that process critical data have port represented

by diamond shape called analysis port:

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Analysis port is the only one that allows one-to-many connection.

Analysis port has just one method write that is implemented in exports

connected to it.
2012 Aldec, Inc.

10

TLM Data/Control Flow

subscriber1

(put)
producer

FIFO

subscriber2

(get)
consumer

Put producer initiates transaction executed by FIFO.

Get consumer retrieves transaction from FIFO.

Analysis port writes data to subscribers (if present).

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2012 Aldec, Inc.

11

Interface Universal Signal Container

master

Module

Bus

monitor

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slave

clk
reset
enable
din[]
dout[]
ready

my_ifc

Bus

Module

SV Interface is a module-level
container for signal and port
direction data.
It can also contain behavioral
code (tasks, assertions, etc.)

interface my_ifc ( input logic clk ); // interface with clock port;

logic
reset;
// asynchronous reset
logic
enable;
// data enable
logic [7:0] din;
// data input
logic [7:0] dout;
// data output
logic
ready;
// data ready
modport slave
( input clk, reset, enable, din,
output dout, ready
);
modport master ( input clk, dout, ready,
output reset, enable, din
);
modport monitor ( input clk, reset, enable, din, dout, ready );
endinterface : my_ifc

2012 Aldec, Inc.

12

Virtual Interfaces

Since SV interface is a module-level construct,

it cannot be used inside a class.

You can have virtual interface as a class attribute

it is treated as a pointer to real (non-virtual) interface.

Virtual interface must be tied to real interface

if object plans to do anything with it:
You can assign real interface to virtual interface in the class constructor

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(not recommended in UVM!)

You can use UVM Factory and configuration database to tie virtual interfaces
to their real counterparts.
Virtual interfaces are the only area of UVM where TLM world meets RTL world.
They are also one of the least popular SV constructs.
Lack of understanding in this area is one of the main reasons of hostility towards UVM

2012 Aldec, Inc.

13

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Nice Example of Verification Methodology

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14

General UVM Structure

Top Level Module

UVM Class-based Verification Environment

Sequencers
Data Items

Monitors
Drivers

...

Scoreboards

System Bus

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Control Logic

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Design Under Test (DUT)

15

UVM Class Diagram

For those who prefer more programmatic approach,
we present UML diagram of the UVM classes.
Some classes deserve
our special attention

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2012 Aldec, Inc.

16

UVM Flow Summary

Establish interface(s)
Create data items (packets, sequences)
Create sequencer and driver to send data

Create monitor to observe data

Create agent (sequencer+driver+monitor)

Create result checkers (scoreboards, etc.)

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Create environments/tests
Create top-level module
2012 Aldec, Inc.

Driver and monitor

are transactors or BFMs
translators between
TLM and RTL layers.

17

Design Under Test

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Class-based part of UVM communicates with RTL Design Under

Test (DUT) via SystemVerilog interface construct.
New SV descriptions of DUT can already utilize interfaces, but
what to do if they dont?
If your DUT does not use interfaces (because
it is written in Verilog or VHDL, etc.), consider
creating SV wrapper with interface around it.
The less UVM testbench knows about DUT
implementation details, the better

2012 Aldec, Inc.

UVM Work Flow

Now that we have covered background information, lets

review typical work flow of UVM testbench creation.

Lets use bottom-up approach, best suited

for hardware designers.

The next slide introduces all non-class based

elements of UVM test environment.

The following slides introduce class-based

elements, from simplest to more complicated.

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18

2012 Aldec, Inc.

19

Top Level Module

SystemVerilog Interface instance (works as a bus)

clk

reset

enable

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Interface Modport
Clock
Generator

System
Reset

RTL Top Level and DUT

2012 Aldec, Inc.

Design Under Test (DUT)

20

Top Level
Module

UVM Class-based Verification Environment

SystemVerilog Interface instance (works as a bus)

clk

reset

enable

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Interface Modport
Clock
Generator

System
Reset

Design Under Test (DUT)

Adding Class-based Environment

2012 Aldec, Inc.

21

Top Level
Module

Packet

UVM Class-based Verification Environment

SystemVerilog Interface instance (works as a bus)

clk

reset

enable

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Interface Modport
Clock
Generator

System
Reset

Adding Basic Data Items

2012 Aldec, Inc.

Design Under Test (DUT)

22

Top Level
Module

Sequence
Packet
Packet
Packet

UVM Class-based Verification Environment

SystemVerilog Interface instance (works as a bus)

clk

reset

enable

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Interface Modport
Clock
Generator

System
Reset

Turning Packets Into Sequence

2012 Aldec, Inc.

Design Under Test (DUT)

23

Top Level
Module
Sequencer

Sequence

Packet
Packet
Packet

Monitor

Driver

Environment

SystemVerilog Interface instance (works as a bus)

clk

reset

enable

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Interface Modport
Clock
Generator

System
Reset

Design Under Test (DUT)

Three Basic Verification Components

2012 Aldec, Inc.

24

Top Level
Module
Sequencer

Sequence

Packet
Packet
Packet

Monitor

Driver

Virtual Interface

Virtual Interface

Environment

SystemVerilog Interface instance (works as a bus)

clk

reset

enable

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Interface Modport
Clock
Generator

System
Reset

Tying Things Together

2012 Aldec, Inc.

Design Under Test (DUT)

25

Top Level
Module
Sequencer

Sequence

Packet
Packet
Packet

Monitor

Driver

Virtual Interface

Virtual Interface

Environment

SystemVerilog Interface instance (works as a bus)

clk

reset

enable

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Interface Modport
Clock
Generator

System
Reset

TEST:
run_test()

Design Under Test (DUT)

Running Test From The Initial Block

2012 Aldec, Inc.

26

Top Level
Module
Agent
Sequencer

Sequence

Packet
Packet
Packet

Monitor

Driver

Virtual Interface

Virtual Interface

Environment

SystemVerilog Interface instance (works as a bus)

clk

reset

enable

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Interface Modport
Clock
Generator

System
Reset

TEST:
run_test()

Design Under Test (DUT)

Monitor+Sequence+Driver=Agent
2012 Aldec, Inc.

27

Top Level
Module
Scoreboard

Agent
Sequencer

Sequence

Packet
Packet
Packet

Monitor

Driver

Virtual Interface

Virtual Interface

Environment

SystemVerilog Interface instance (works as a bus)

clk

reset

enable

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Interface Modport
Clock
Generator

System
Reset

TEST:
run_test()

Design Under Test (DUT)

Adding Result Checking: Scoreboard

2012 Aldec, Inc.

28

Top Level
Module
Scoreboard

Master
Agent

Sequencer

Sequence

Packet
Packet
Packet

Environment

Monitor

Driver

VI

VI

SystemVerilog Interface instance (works as a bus)

clk

reset

enable

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Interface Modport
Clock
Generator

System
Reset

TEST:
run_test()

For More Complex DUTs

2012 Aldec, Inc.

Design Under Test (DUT)

29

Top Level
Module
Scoreboard

Slave
Agent Master
Agent

Sequencer
Sequencer

Sequence

Packet
Packet
Packet

Monitor
VI

Environment
Environment

TestTest

Driver
Monitor

VI

VI

Driver
VI

SystemVerilog Interface instance (works as a bus)

clk

reset

enable

www.aldec.com

Interface Modport
Clock
Generator

System
Reset

TEST:
run_test()

Design Under Test (DUT)

Hierarchy Can Get More Complex!

2012 Aldec, Inc.

UVM Factory

One of the essential features of class-based verification

components is that they are created dynamically it is very
different from the RTL hardware models.

UVM factory lets you register object types

while you write testbench and create objects
as needed at any time during simulation.

You can also register data fields of objects

as knobs and then override (modify) them as needed during
test run.

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30

2012 Aldec, Inc.

31

UVM Phases

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UVM verification goes through several phases

with pretty much self-explanatory names.
UVM objects can contain tasks (for run phase)
and functions (for all other phases) that will
be executed during given phase.
Functions for build and connect phases are
frequently written to describe pre-simulation
behavior.
Phase called run describes objects behavior
during simulation run; its task is also present
in many UVM components.
Report phase function is a convenient spot to
display final verification results.

2012 Aldec, Inc.

build

connect
end_of_elaboration
start_of_simulation
run

extract
check
report

32

UVM Sequence Item Example

class packet extends uvm_sequence_item;

rand int pdata;

int last_item;
`uvm_object_utils_begin(packet)
`uvm_field_int(pdata, UVM_ALL_ON)
`uvm_object_utils_end
constraint dc {data >= 0 && data < 'h100; }
function new( string name="packet" );
super.new(name);
endfunction

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endclass

2012 Aldec, Inc.

packet inherits from

the library class
Data member ready
for randomization
Object registration with
UVM Factory
Knob registration
Constraint for better
randomization

33

Building Sequence
class my_seq extends uvm_sequence #(packet);
integer n_packets = 8;

`uvm_object_utils_begin(my_seq)
`uvm_field_int( n_packets, UVM_ALL_ON )
`uvm_object_utils_end
function new(string name="my_seq");
super.new(name);
endfunction

Previously defined packet

is our sequence item

Number of packets is our

knob in this sequence

Body task describes

behavior of the sequence

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virtual task body();

packet transaction;
`uvm_info("my_seq", "Starting sequence", UVM_MEDIUM)
for(int unsigned i = 0; i < n_packets; i++) begin
// create and randomize packet, wait for grant, send request, wait for done
`uvm_do( transaction )
uvm_do macro handles item creation,
end
randomization and sending
transaction.last_item = 1;
`uvm_send( transaction )
uvm_send macro does not
`uvm_info("my_seq", "Finishing sequence", UVM_MEDIUM)
create/randomize!
endtask
endclass

2012 Aldec, Inc.

34

Creating Driver
class my_drv extends uvm_driver #(packet);
virtual my_ifc vif;
`uvm_component_utils(my_drv)
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction

Virtual interface instance

(points to real interface)
Safeguard against building driver
with unconnected virtual interface

function void build_phase(uvm_phase phase);

super.build_phase( phase );
if (!uvm_config_db#( virtual aifc )::get(this, "", "vif", vif))
`uvm_fatal("NOVIF", {"virtual interface must be set for: ", get_full_name(), ".vif"});
endfunction
virtual task run_phase(uvm_phase phase);
packet req_tr;

Grants permission to send packet

and waits till sequencer sends one

forever begin
Transfers packet data
seq_item_port.get_next_item(req_tr);
to the interface
if (vif.reset=='1) wait(vif.reset=='0);
@(negedge vif.clk) vif.din = req_tr.pdata;
if (req_tr.last_item) vif.enable = '0; else vif.enable = '1;
@(posedge vif.clk);
`uvm_info("my_drv", {"Transaction Completed:\n", req_tr.sprint()}, UVM_MEDIUM);
seq_item_port.item_done();
end
Signals end of item processing
endtask

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to the sequencer

endclass

2012 Aldec, Inc.

35

Writing Monitor
class my_mon extends uvm_monitor;
virtual my_ifc vif;
int packet_count = 0;

Virtual interface instance

(points to real interface)
Analysis port instance

uvm_analysis_port#(packet) ap;
`uvm_component_utils_begin(av_mon)
`uvm_field_int(packet_count, UVM_ALL_ON)
`uvm_component_utils_end
function new (string name, uvm_component parent);
super.new(name, parent);
ap = new("ap", this);
endfunction

Safeguard against building monitor

with unconnected virtual interface

function void build_phase(uvm_phase phase);

super.build_phase( phase );
if (!uvm_config_db#(vaifc)::get(this, "", "vif", vif))
`uvm_fatal("NOVIF", {"virtual interface must be set for: ", get_full_name(), ".vif"});
endfunction

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. . .

2012 Aldec, Inc.

36

Writing Monitor cont.

. . .
virtual task run_phase(uvm_phase phase);
packet tr;
tr = packet::type_id::create("tr", this);

Declare and create packet

to be filled with interface data

Mark beginning of transaction

forever begin
@(negedge vif.clk);
(for recording purposes)
if (vif.ready=='1) begin
void'(this.begin_tr(tr));
Data transfer from the interface
tr.pdata = vif.dout;
to the transaction packet
tr.last_item = 0;
`uvm_info(get_type_name(),
$sformatf("Collected transaction:\n%s", tr.sprint()), UVM_MEDIUM)
++packet_count;

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ap.write(tr);
@(posedge vif.clk) void'(this.end_tr(tr));
end //if
end //forever
endtask

Send collected transaction

to the analysis port
Mark end of transaction

function void report_phase(uvm_phase phase);

super.report_phase( phase );
`uvm_info(get_type_name(),$sformatf(" processed %0d packets.", packet_count), UVM_LOW)
endfunction
endclass

Report phase: display number of processed

packets when simulation ends

2012 Aldec, Inc.

www.aldec.com

37

Building Environment

Instance of stock sequencer

class av_env extends uvm_env;

int num_seqs = 4;
Instances of previously defined
uvm_sequencer #(packet) my_sequencer;
sequence, driver and monitor
my_seq my_sequence;
my_drv my_driver;
my_mon my_monitor;
`uvm_component_utils_begin(av_env)
`uvm_field_int( num_seqs, UVM_ALL_ON )
`uvm_component_utils_end
Trick that enables printing of hierarchy
function new(string name, uvm_component parent = null);
of verification components
super.new(name, parent);
uvm_top.enable_print_topology = 1;
my_sequencer = new("my_sequencer", this);
Creating stock sequencer using constructor
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase( phase );
my_monitor = av_mon::type_id::create("my_monitor", this);
Creating monitor, driver and
my_driver = av_drv::type_id::create("my_driver", this);
sequence using UVM Factory
my_sequence = av_seq::type_id::create("my_sequence", this);
endfunction
Connecting driver
virtual function void connect_phase(uvm_phase phase);
my_driver.seq_item_port.connect(my_sequencer.seq_item_export);
with sequencer
endfunction
virtual task run_phase(uvm_phase phase);
DO NOT END run phase!
phase.raise_objection(this);
for ( int i = 0; i < num_seqs; ++i )
my_sequence.start(my_sqr, null);
`uvm_info("av_env", "Environment done with the sequence", UVM_MEDIUM)
phase.drop_objection(this);
endtask
OK to end run phase!
endclass

2012 Aldec, Inc.

38

Creating Top Level

module top;
timeprecision
timeunit

1ps;
1ns;

import uvm_pkg::*;
`include "uvm_macros.svh"
import my_pkg::*;
localparam CLK_PERIOD = 10;
localparam CLK_HP = CLK_PERIOD / 2.0;

logic clk;
my_ifc vif(clk);
my_env my_test;
my_dut DUT (vif);

Getting access to UVM

library and user classes
Real interface instance
Environment class instance

UUT instance
Connecting virtual and real interface

initial begin : TEST

uvm_config_db#(virtual my_ifc)::set(uvm_root::get(), "*", "vif", vif);
uvm_config_db#(int)::set(uvm_root::get(), "*", "num_seqs", 8);
my_test = new("my_test",null);
run_test();
Overriding default value of num_seqs knob
end

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initial begin : CLK_GEN

clk = 1'b0;
forever #CLK_HP clk = ~clk;
end // CLK_GEN
initial begin : INIT
vif.reset <= '1;
vif.enable = '0;
@(negedge clk) vif.reset = '0;
@(negedge clk) vif.enable = '1;
end // testing

endmodule

2012 Aldec, Inc.

Start default test !

(Or select test by name if you
compiled more than one)

39

Organizing Your Work

Successful compilation of your UVM test requires good organization

of your work. Heres a handful of well-tested suggestions:
1.
2.
3.
4.
5.

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6.

Create test package that will contain all UVM test class descriptions.
Import uvm_pkg package and include uvm_macros.svh header in the
test package.
Include all UVM test component sources in the test package
(this way you avoid placing the same headers in all individual sources).
Include DUT sources and test package in the header of your top-level
module description.
Import uvm_pkg package and include uvm_macros.svh header inside
the top-level module description.
Compile top-level module source with your simulator-specific options.
Thats it! You are ready to go!

2012 Aldec, Inc.

40

UVM in Riviera-PRO
Aldec simulator provides most recent and some archival versions of
UVM library tailored to better use tool features.
Specifying +UVM_ALDEC_RECORDING +UVM_SET_RECORDING_DETAIL
switches in simulator command line records transactions for display
in the waveform.
HDL editor has built-in templates for the majority of UVM classes.

www.aldec.com

2012 Aldec, Inc.

41

Conclusion

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UVM is like Halloween ghost it may be scary initially,

but there is never real danger .
UVM can be very useful especially when quick results are
needed
UVM promotes interoperability and reuse.
Experienced users may notice that in some specific
applications solution written from scratch is better than the
one offered by UVM.
Check our website for trainings and other resources.

2012 Aldec, Inc.

42

Q&A
Aldec, Inc.

Riviera-PRO

Corp. Headquarters N. America

Advanced Verification Platform

2260 Corporate Circle

Henderson, NV 89074 USA

Active-HDL

+1.702.990.4400
sales@aldec.com
Europe
Israel
Japan
China
India
Taiwan

sales-eu@aldec.com
sales-il@aldec.com

FPGA Design and Simulation

ALINT
Design Rule Checking

HES
Hardware Emulation Solutions

sales-jp@aldec.com
info@aldec.com.cn

DO-254-CTS

sales-in@aldec.com

FPGA Level In-Target Testing

sales-tw@aldec.com

Microsemi Prototyping
RTAX/RTSX

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News/Products/Events/Resources/Support

2012 Aldec, Inc.