THE UNIVERSITY OF MANITOBA

2012
MIDTERM EXAMINATION-2
9 NOVEMBER
DEPARTMENT & COURSE NO.: ECE 2220
TIME:
75
MINUTES
TOTAL MARKS: 100
EXAMINATION: DIGITAL LOGIC SYSTEMS
EXAMINER: E. Hossain

Closed-book exam: No printed or hand-written material and calculator are allowed. Show
all the steps in your work and label all the signals in the logic circuit clearly.
State clearly any assumptions being made.
Answer all 3 questions

10

1. (a) Design a gated D latch using NAND gates only. Draw the circuit diagram and show
its characteristic table.

20

(b) Design a 3-bit parallel access shift register using T flip-flops. It should include a
control signal called Load/Shif t. If Load/Shif t = 1, it loads the parallel inputs
into the register. If Load/Shif t = 0, it acts as a right-shift register.

20

2. (a) Design a three bit synchronous up/down counter using JK flip-flops. It should
include a control signal called U p/Down. If U p/Down = 1, it works as an up
counter. If U p/Down = 0, it works as a down counter.

20

(b) Design a synchronous modulo-13 up counter counter using D flip-flops.

3. An FSM has an input w and an output z, and it produces z = 1 when the values of w in
the preceding four clock cycles are 1001; otherwise z = 0. It is able to detect overlapping
sequences.

15

(a) Draw the state diagram for this FSM.

15

(b) Draw a state assigned table for this FSM.