Digital Electronics

Module 6 : Microprocessor- the 8085

2006 IIHT Limited

Module 6: Microprocessor- the 8085

Microprocessor- the 8085

Introduction
Intel 8085 microprocessor is the next generation of Intel 8080 CPU
family. Typical microprocessor operations include adding,
subtracting, comparing two numbers, and fetching numbers from
one area to another. These operations are the result of a set of
instructions that are part of the microprocessor design.

Topics covered in this module

Block Diagram
Pinout Diagram
Fetching and Executing Instructions

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Block Diagram

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Block Diagram

Address, Data, and Control buses

The 8-bit internal data bus carries instructions and data between
the CPU registers
The external buses are connected to memory, I/O, and so on.
The upper 8 address bits are on a separate bus and are used for
address bits. It is designated as A15-A8.
Lower 8 bits are multiplexed which means that the eight lower
bus lines are used for address bits during some time T states and
for data bits during other T states. So the bus is labeled addressdata bus, designated AD7-AD0

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Block Diagram

Accumulator
The accumulator is connected to the 8-bit internal data bus.
The bidirectional arrow between the accumulator and the bus
indicates a three state connection that allows the accumulator to
send or receive data.
Temporary Register
An input to the ALU comes from the temporary register which stores
the operands of the arithmetic logic operations.
ALU and Flags
The ALU carries out the arithmetic and logical operations. Contents
of the accumulator and the temporary register are inputs to the ALU.
The ALU result is then stored back in the accumulator.
Zero, sign, carry, and parity are four flags in 8085, which includes a
fifth flag, called the auxiliary carry flag.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Block Diagram

Instruction register and Decoder

During the fetch cycle, the op-code of an instruction is stored in the

instruction register. This op-code then drives the instruction decoder
and machine-cycle encoder.

Timing and Control

The oscillator generates the two-phase clock signals (CLK and CLK)
that synchronize all registers.
The controller-sequencer produces control signals needed for internal
and external control. The controller-sequencer has a ROM that stores
all the microroutines required to execute instructions.
Every instruction is fetched and stored in the instruction register after
which the op-code is decoded to get the starting address of the desired
microroutine.
Control signals are then sent to the internal and external data buses.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Block Diagram

CPU Registers
B, C, D, E, H and L are CPU Registers. And so are the stack pointer
program counter, and incrementer- decrementer.
Control signals select the register for read and write operation.
The CPU can either load a register from the 8-bit internal data bus or
output the register contents to this data bus.
The incrementer - decrementer can add 1 and subtract 1 from the
stack pointer or program counter contents.

Address Buffer and Address-Data buffer

The contents of the stack pointer or program counter can be loaded
into the address buffer and address-data buffer.
The output of these buffers then drives the external address bus and
address-data bus.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Block Diagram

Interrupt Control
At times the execution of the main program needs to be interrupted in
order to answer a request from an I/O device.
For instance, an I/O device may send an interrupt signal to the
interrupt control unit to show that data is ready for input.
The computer stops for that moment what it is doing, inputs the data
then returns to what it was doing.
Serial I/O Control
I/O devices at times work with serial data rather than parallel.
The serial stream from an input device must be converted to 8-bit
parallel data before the computer can use it
Similarly, the 8-bit data output of a computer must be converted to a
serial form before a serial output device can be used.
At the SID, serial input data enters the 8085. Serial data leaves the
8085 at SOD.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Pin out Diagram

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Pin out Diagram

Pins 1 and 2
In microprocessors, a crystal is used for stabilizing frequency.
The 8085 has an on chip oscillator. It does not have the required
circuitry for crystal, LC Tank, or RC network that controls the
frequency.
Pins 1 and 2 serve to connect a crystal, LC circuitry or RC
circuitry network to X1 and X2.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Pin out Diagram

Pin 3
This pin carries the RESET OUT signal.
When high it indicates that the CPU is being reset. It goes to
peripheral chips.
When powered, the 8085 and the peripheral chips are reset or
initialized.
The processing starts after RESET OUT goes LOW.
Pins 4 and 5
SOD stands for serial out data. The serial data comes out of pin
4.
SID stands for serial in data. Pin 5 is the input pin for serial data.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Pin out Diagram

Pin 6 to 11
These pins are part of the interrupt control unit.
The 8085 has five inputs for interrupt requests.
In the order of priority, the interrupts are TRAP, RST 7.5, RST6.5,
RST 5.5, and INTR.
If two or more interrupt are high at the same time, 8085 services
them in order of their importance.
Pin 11, is an output pin with a signal called the interrupt
acknowledge (INTA).
Pins 12 to 28
These pins carry the lower 8 bit address bits or the 8 data bits.
Lower half of the address bus is multiplexed with data bus to
keep count to 40.
Pin 20 (Vss) is the system ground.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Pin out Diagram

Pin 29 and 33
These two pins carry status signals which are output signals.
Labeled as S0 and S1, these status signals (and the IO/ M)
signal) indicate whether an instruction fetch, memory read,
memory write, or other operation is taking place.
Pin 30
The 8085 microprocessor requires one or more memory chips
connected to it. Every memory chip has it own address latch
which stores the incoming address from the address bus and the
address data bus.
ALE is pin 30 which goes to memory chips.
The falling edge of the ALE signal loads the address on the
address bus and address data bus into address latch of the
memory chips

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Pin out Diagram

Pin 31, 32, and 34

These pins are connected to memory and I/O chips.
A low IO/ M signal suggests a memory operation and a high IO/
M means that an I/O instruction is being executed.
The WR and RD determine if a write or a read is done. A low WR
means a write operation and low RD means a read operation.
Pin 35
Pin 35 is the READY signal. It is used to slow down 8085 for slow
peripheral devices which cannot run at the speed of 8085.
The first step in sending or receiving data from a device is to
address the device.
If device is not ready it returns a low READY bit to the 8085
which then generates a number of WAIT states. When the
peripheral device is ready it sends a high READY signal to 8085.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Pin out Diagram

Pins 36 and 37
Pin 36 is an input carrying the RESET IN signal.
This signal comes either from operator reset button or the source.
When it is low the CPU resets the program counter, instruction
register, and the other circuits.
It also sends a high RESET OUT to pin 3. The CPU remains
reset till the RESET IN signal goes high after which data
processing begins.
Pin 37 is the CLK signal. It is derived from the on chip oscillator.
CLK is the system clock. Each cycle represents one T state.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Pin out Diagram

Pin 38 to 40

The HOLD and HLDA signals (pin 39 and 38) are used in DMA
operations.
The DMA approach helps transfer large amounts of data in short
time.
Pin 40 is connected to a source + 5V.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Fetching and Executing Instructions

Mnemonic

M1

M2

M3-M5

T1

T2

T3

T4

T5

T6

T1

T2

T3

MOV
reg1,reg2

PC
OUT

PC+1
PC

INSTR
1R

reg2

TMP

--

--

FEO

TMP
reg1

--

--

MOV
reg,M
MOV
M,reg

PC
OUT

PC+1
PC

INSTR
1R

--

--

HL
OUT

MHL

reg

--

PC
OUT

PC+1
PC

INSTR
1R

reg

TMP

--

--

HL
OUT

TMP

MHL

--

MVI
reg,byte
ADD reg

PC
OUT

PC+1
PC

INSTR
1R

--

--

PC
OUT

PC+1
PC

byte
reg

--

PC
OUT

PC+1
PC

INSTR
1R

reg

TMP

--

--

FEO

A+TMP
A

--

--

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Fetching and Executing Instructions

Register Move
An example of a register-move instruction is MOV reg1, reg2.
In the first T state, Program counter contents are placed on the
address bus and address-data bus.
During the second T state, the Program counter is incremented.
In the third T state, the code for the MOV instruction is sent to the
Instruction Register.
During T4 state register 2 contents are copied into the temporary
register.
T5 and T6 are not used.
During the T2 state of M2 the temporary register contents are
copied into register 1. The instruction cycle of the register-move
instruction is thus completed.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Fetching and Executing Instructions

Indirect Memory Read

Two memory operations are required for an indirect read
instruction. One for instruction fetch and one for the data
Consider the instruction MOV reg, M
This instruction copies the addressed memory data into a
designated register.
In the second machine cycle M2, the HL register contents are
placed on the address bus and address data bus during the T1
state.
Do note that two machine cycles and seven T states are required
to fetch and execute a memory MOV instruction.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Fetching and Executing Instructions

Indirect Memory Write

Consider the instruction MOV M, reg
The first three T states are the fetch portion.
In the fourth state the designated register contents are copied to
the temporary register.
In the second machine cycle, the HL contents are put on the
address bus and address-data bus during T1 state.
During T2 and T3 of the second machine cycle, the temporary
register contents are transferred to the addressed memory
location.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Fetching and Executing Instructions

Immediate MOV
Consider the instruction MVI reg, byte.
T1, T2 and T3 are the fetch states and T4 is the decoding state.
In the second machine cycle, the program counter contents are
put on the address bus and address-data bus during T1 state.
During T2 state PC is incremented.
During this time memory is accessed and the immediate data is
read and loaded into the assigned register during T3 state.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Fetching and Executing Instructions

ADD

Consider the instruction ADD reg.

It begins with the usual fetch.
In the T4 state of machine cycle M1, the selected register
contents are loaded into the temporary register.
In the T1 state nothing actually happens.
In the T2 state the accumulator contents and temporary register
are added.
This result is stored in the accumulator.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Fetching and Executing Instructions

JMP

The unconditional jump instruction is JMP address.

The opcode is fetched and during the fourth T state it is decoded.
In the second machine cycle the program counter contents are
put on the address bus and address-data bus.
States T2 and T3 increment the program counter and the lower
byte is transferred to the Z register.
In the third machine cycle, the memory is addressed during T1 by
the program counter.
PC is incremented during T2.
During T3 state the upper byte is transferred from the memory to
register W.
It takes three machine cycles and ten T states to complete the
JMP instruction.

2006 IIHT Limited

Digital Electronics

Module 6: Microprocessor- the 8085

Conclusion

Control signals in 8085 microprocessor drive all the internal

registers.

The ALU carries out the arithmetic and logical operations.

ALE is pin 30 which goes to memory chips in 8085

microprocessor.

2006 IIHT Limited

Digital Electronics