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ESE 570 MOS INVERTERS

DYNAMIC CHARACTERISTICS

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

Usually
Cdb >> Cgd & Csb >> Cgs

extrinsic
parasitic
caps

n = fan-out 1
#

Cload = C dbn +

##
C

dbp

+ #C#

gdn

+#C#

gdp

+# C

int

+ nCgb

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

# C#

+ C dbp + Cint + n Cgb


ii
dbn

Cgb = Cgbn+ Cgbp

worst
case
2

Cload Cdbn + Cdbp + Cint + nCgb


Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

where n = fan-out 1
3

VDD

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

MOS Inverter Dynamic Performance


1. ANALYSIS (OR SIMULATION): For a given MOS inverter schematic +
Cload, estimate (or determine) the propagation delays PHL and/or PLH,
OR the rise/fall times rise and/or fall.
2. DESIGN: For given specs for the propagation delays PHL and/or PLH,
OR the rise/fall times rise and/or fall + Cload, determine the MOS inverter
schematic.
METHODS:
1. Average Current Model
PHL C load

V HL
V OH V 50%p
=C load
I avg , HL
I avg , HL

2. Differential Equation Model


i C =C load

d V out
d V out
dt=C load
dt
iC

where dt PHL
3. 1st Order RC Delay Model

Assume
Vin ideal

PHL0.69 C loadRn
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

CALCULATION OF PROPOGATION DELAY TIMES


VDD

C load V HL C load V OH V50%


50p
PHL
=
=C load R eff , HL
I avg , HL
I avg , HL

C load V LH C load V50%


50p V OL
PLH
=
=C load R eff , LH
I avg , LH
I avg , LH
t

VDD

VDD

0,

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

0,

CALCULATION OF RISE & FALL TIMES

iC = iDP - iDn

VDD

VDD

0,

0,

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

Calculating Propagation Delays By Solving


the Circuit Differential Equation
Let's assume Vin is an ideal step-input.
Two Cases
1. Vin abruptly rises => Vout falls => PHL
2. Vin abruptly falls => Vout rises => PLH

iDP - iDn

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

10

1) Vin ABRUPTLY RISES CASE -> PHL

Vin(t = t0) = 0 -> VDD

Vin(t < t0) = 0 and Vout (t < t0) = VDD


LIN V50% Vout < VDD - VT0n
i Dp0

V out =V DD V T0n

C load

d V out
d V out
i Dn dt =C load

dt
i Dn

V50%= VDD/2

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

t sat

11

CMOS Static Inverter Characteristics Recall

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

12

1) Vin ABRUPTLY RISES CASE -> PHL

Vin(t = t0) = 0 -> VDD

V50%= VDD/2

C load

d V out
d V out
i Dn dt =C load

dt
i Dn
V out =V50%
50p

t=t50%
50p

pHL=t=t dt=C load V


0

out

=V DD

dV out =C load R eff , HL


i Dn

V50%
1
1

dV out C load V V
dV out
i Dn
i Dn
tsat - t0
t50% - tsat

V DDV T0n

.=C load V

DD

t sat

nMOS SAT

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

50p

DD

T0n

nMOS LIN

= t50% - t0

13

1) Vin ABRUPTLY RISES CASE => PHL cont.

t0 < t < tsat i = k n V V 2 =i


Dn
in
T0n
C
2
kn
dV out
2
V in V T0n =C load
2
dt
VDD

for Vin = VDD and V DD V T0n V out V DD

VDD
V50%= VDD/2

dV out
dV out
=> dt =C load
i Dn=C load
i Dn
dt

t sat

tt'1sat

V DD V T0n

t dt =C load V
0

C load

tt1sat
'

t dt = k
0

2
'
1
sat

t t 0 =

DD

dV out
i Dn

V DD V T0n

V DD V T0n 2

DD

dV out

2C load V T0n
2

k n V DD V T0n

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

14

1) Vin ABRUPTLY RISES CASE => PHL cont.

tsat < t < t50%

VDD

kn
i Dn= [V in V T0n V out V 2out ]=i C
2
kn
dV out
2
[V DD V T0n V out V out ]=C load
2
dt

0
VDD
V50%= VDD/2

V out V DD V T0n

Vin = VDD and


t50%
50p

tt

t sat

'
1
sat

V50%
50p

dt=C load V

DD

V T0n

VDD

dV out
i Dn

tsat

tsat

VDD

VDD

VDD

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

VDD

Vout = V50%
VT0n
V = VVDD- V
out

DD

T0n

15

1) Vin ABRUPTLY RISES CASE => PHL cont.


Vout = V50% = VDD/2

tsat

VDD
VDD

tt t 0 =
tsat

VDD/2
VDD/2

VDD
'
1
sat

Vout = VVDDDD- VT0n

VDD

2 C load V T0n
k n V DD V T0n 2

tsat
VDD/2

VDD
VDD
VDD

VDD/2

VDD
VDD

VDD
VDD/2

Rn

where for CMOS Inverter V50% = VDD/2


Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

16

1) Vin ABRUPTLY RISES CASE PHL => cont.

VDD
VDD

VDD/2

VDD

VDD

Recall from static CMOS Inverter:


k n k 'n W / Ln n W / Ln
k R= = '
=
k p k p W / L p p W / L p

DESIGN: (1) Vth kR; (2) PHL kn; (3) kR & kn kp


Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

17

SOMETIMES USED APPROXIMATION FOR PHL

C load

tt=t
=t'50%

PHL=t=t dt
1
0

kn
V DD V T0n 2
2

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

out

=V DD

dV out

2C load 0.5V DD
k n V DD V T0n 2

PHL
t sat

V out =0.5 V DD

C load V DD
k n V DD V T0n

is less than 10%

R n C load

18

VDD = 5 V, VGSn = 5 V and VDSn 4V => iDn = iDnsat = 5mA

VDDV
V50% = 0.5 VDD = 2.5

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

19

Example 6.1 cont.

1 pF
2V
451V
.=
[
ln
1]
3
2
5V
0.625 x 10 A/V 51V 51V

1 pF
2
16
.=
[ ln 1]=0.52 ns
3
5
0.625 x 10 A/V 4 4
UNITS:

F
F
C /V
= V=
V =s
A/V A
C /s

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

20

COMPARISON WITH SOMETIMES USED


APPROXIMATION FOR PHL

= 0.52 ns

Approximation for PHL


1 x 1012 F5V
PHL
=
=0.5 ns
2
2
k n V DD V T0n
10 A
2
4
V

2
4V
C load V DD

where k n =

2 i Dnsat

10 mA
=
2
2
V DD V T0n 4 V

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

21

DD

DD

DD

DD

0.99 mA A
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

22

Example 6.2 cont.


4.04 ns

-3

0.99 x 10 A

DD

tsat

tsat

-6.25 x 10

-10

s/V Vout |

Vout = 4.0V
Vout = 4.5V

tsat
0.31 ns
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

23

Example 6.2 cont.


0.31 ns

tsat

tsat

Vin = 5 V

tsat
Vin = 5 V

3.39 ns
tsat

tsat

3.39 ns + 0.31 ns = 3.70 ns

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

24

2) Vin ABRUPTLY FALLS CASE => PLH

Vout (t < t0) = 0, Vin(t = t0) = VDD -> 0


SAT 0 < Vout - VT0p
LIN - VT0p < Vout V50%
VDD

V50%= VDD/2
i Dn0

tsat
C load

d V out
d V out
i Dp dt =C load

dt
i Dp

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

25

2) Vin ABRUPTLY FALLS CASE => PLH


VDD

V50%= VDD/2

C load

tsat

d V out
d V out
i Dp dt =C load

dt
i Dp
V out =V50%
50p

t=t 50p
50%

PLH =t=t dt=C load V


0

V T0p

.=C load 0

out

=0

1
i Dp

dV out =C load R eff , LH


V50%
50p

dV out C load V

i Dp
tsat - t0

pMOS SAT

dV out = t - t
50%
0

i Dp
t50% - tsat
T0p

pMOS LIN

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

26

2) Vin ABRUPTLY FALLS CASE PLH => cont.

VDD
VDD

VDD/2

VDD

. R p C load

VDD

Recall from static CMOS Inverter:


k n k 'n W / Ln n W / Ln
k R= = '
=
k p k p W / L p p W / L p

DESIGN: (1) Vth kR; (2) PLH kp; (3) kR & kp kn


Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

27

SOMETIMES USED APPROXIMATION FOR PLH

C load

t =t sat

PLH =t =t dt
0

kp
V DD V T0p
2

.
V50%= VDD/2

tsat

PLH

V out =0.5 V DD

V
2

out

=0

dV out

2C load 0.5V DD
2

k p V DD V T0p
C load V DD

k p V DD V T0p

R p C load

is less than 10%


Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

28

Inverter Dynamic Performance Quick Review


1. ANALYSIS (OR SIMULATION): For a given MOS inverter schematic +
Cload, estimate (or determine) the propagation delays PHL and/or PLH,
OR the rise/fall times rise and/or fall.
2. DESIGN: For given specs for the propagation delays PHL and/or PLH,
OR the rise/fall times rise and/or fall + Cload, determine the MOS inverter
schematic.
METHODS:
1. Average Current Model
PHL C load

V HL
V OH V 50%p
=C load
I avg , HL
I avg , HL

2. Differential Equation Model


d V out
d V out
i C =C load
dt=C load
dt
iC
st

3. 1 Order RC Delay Model


PHL 0.69 C load R n

Assume
Vin ideal

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

29

Quick Review PLH & PHL Differential Equation Model

CONDITIONS for Balanced CMOS Propagation Delays, i.e.


n W
W
=> L = L
p
n
p

i.e. Symmetrical Inverter


Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

30

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

31

27

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

32

ALTERNATIVE APPROXIMATE DELAY DESIGN FORMULAS


Using the approximate delay formulas on slides 16 and 26:

PHL

C load V DD
2

k n V DD V T0n

R n C load

Wn
k n =n C ox
Ln

Wn
C load V DD

L n PHL n C ox V DD V T0n 2

PLH

C load V DD
2

k p V DD V T0p

R p C load

Wp
k p = p C ox
Lp

Wp
C load V DD

L p PLH p C ox V DD V T0p2
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

33

VDD
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

34

Example 6.3 cont.

t V out =1V

V out =1V

dV out
dt=C load i lin
Dn
t V =4 V
out

V out =4V

8.11
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

35

Example 6.3 cont.


8.11

Wn = 8.11 (1 m) = 8.11 m

8.11 m = 10.81 m
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

36

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

37

Design for Propagation Delays Using More


Realistic Model for Cload
Cload ii Cdbn + Cdbp + Cint + Cgb

(Wn, Wp).

Cload ii Cdbn(Wn) + Cdbp(Wp) + Cint + Cgb


Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

38

Design for Propagation Delays Using More Realistic Model for Cload cont.

Cdbn (Wn) = [Wn (Y + xj)] Cj0n Keqn + (Wn + 2Y) Cjswn Keqn(sw)
Cdbp (Wp) = [Wp (Y + xj)] Cj0p Keqp + (Wp + 2Y) Cjswp Keqp(sw)
Cload = 0 + nWn + pWp

0 = 2YCjswnKeqn + 2YCjswpKeqp + Cint + Cgb


n = (Y + xj)Cj0nKeqn + CjswnKeqn
p = (Y + xj)Cj0pKeqp + CjswpKeqp

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

39

Design for Propagation Delays Using More Realistic Model for Cload cont.

C load
PHL = n
Wn

= 0 + (n + (W
/Wn) p)Wn
Cpload
PLH = p
and
Wp

where
Cload = 0 + nWn + pWp
n and P are set largely by process parameters and V DD.
const.

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

40

C load
PHL= n
Wn

Cload = 0 + nWn + pWp

C load
PLH = p
Wp
Cload = 0 + nWn + pWp

Multiply and divide pWp by Wn

Multiply and divide nWn by Wp

Cload = 0 + nWn + (pWp/Wn)Wn

Cload = 0 + (nWn/Wp)Wp + pWp

= 0 + [n + pR]Wn

where R = Wp/Wn = constant

PHL n

0 + [n + pR]Wn
Wn

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

= 0 + [n/R + p]Wp

1 p W p
(Recall: V th =
when Lp=Ln)
k R n W n

PLH p

0 + [n/R + p]Wp
Wp
41

Design for Propagation Delays Using More Realistic Model for Cload
cont.

PHL n

0 + [n + pR]Wn
Wn

PLH p

0 + [n/R + p]Wp

where R = aspect ratio = Wp/Wn

Wp

Hence increasing Wn and Wp will have diminishing influence on PHL and


PLH as they become large, i.e.

Limit
PHL =

limit PHL = n [n + p R]

Wn large

R = constant

Limit
PLH = limit PLH = p [n/R + p]
Wp large

R = constant

absolute
minimum
delays

0 = f(Cint, Cgb).

P avg C load V 2DD f


Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

42

Design for Propagation Delays Using More Realistic Model for Cload cont.

=
Limit
PHL

limit PHL = n [n + p R]

Wn large

R = constant

Limit
PLH = limit PLH = p [n/R + p]

absolute
minimum
delays

Wp large

R = constant

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

43

Design for Propagation Delays Using More Realistic Model for Cload cont.
1.6

1.0

VDD = 3.3 V
External load cap = 100 fF
R = Wp/Wn = 2.75

0.8

Ln = Lp = 0.8 m

1.4

PHL (ns)

1.2

0.6
0.4
0.2

Area x PHLProduct (norm)

0.0

10

15

20

25

nMOS Channel Width Wn (m)

5.0
4.5
4.0
3.5

minimum

3.0
2.5
2.0

12

16

20

nMOS Channel Width Wn (m)

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

44

Taking Into Account Non-Ideal Input Waveform


ideal Vin
non-ideal Vin
Vout to ideal Vin
Vout to non-ideal Vin

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

45

st

1 Order RC DELAY MODELS


Equivalent circuits used for MOS transistors

Ideal switch + effective ON resistance + load capacitance.


Unit nMOS has effective ON resistance Rn= Run/n & capacitance Cd.

Unit pMOS has effective ON resistance Rp = Rup/p & capacitance pCd;

where transistor scale factors n 1 and p 1, i.e. Wn = nWun, Wp = pWup

Cgb = Cg and Cdb = Csb = Cd for the unit n,pMOS transistors and scale with n, p.

NMOS and pMOS transistor at minimum gate length (L)

Capacitance directly proportional to gate width (W)


Conductance directly proportional to gate width (W)
Resistance is inversely proportional to gate width (W)

Example
Unit
Transistors

Example Unit Dimensions: L un=Lup =2 ; W un =W up =4


Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

46

1st Order RC Elmore Delay Model


VDD

PLH
PHL

PLH

Rn or Rp

V1(t)

V1(0)

Cload

V 1 0=0
V 1 0=V DD

V 1 t=V DD 1e

t / R p C load

V DD
/ R
V50%
=
=V
1e
50p
DD
2
V DD V50%
1
/ R C
50p
e
=
=
V DD
2
PLH

PLH

nu

C load

load

PLH =ln 2C load R p =0.69C load R p

(0 -> 50%)

NOTE D =R p C load (0 -> 63%) = 1 time constant


ALSO PHL =ln 2C load R n=0.69 C load R n

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

47

nMOS 1st Order RC Delay Model


ASSUME: bulk at GND
Rn = Run/n
n

nCd
ON/
OFF

nCg

nCd

Where Wn = nWun
n 1, usually n = 1

Recall:

R un

PHL

C load V DD
k n V DD V T0n

0.69 R un C load

V DD Lun
2

0.69 n C ox W un V DD V T0n

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

48

RC DELAY MODLELS - Cont.


Estimating PHL
Reff,HL = Rn
Reff,LH = Rp = Rpu/p = Rn

pCd
Rn

VDD
pCd

pCd

npCg
RnR
/nn

Rn

Cd

nCg
Rp = 2 Rn

PHL
Cd

VDD
npCg
Y

CndC

nC
nCg

Cload = n(1 + p)(Cd + Cg)

PHL 0.69C loadR n =0.691 p C d n C g R n


ELMORE DELAY MODEL

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

49

pMOS 1st Order RC Delay Model


ASSUME: bulk at VDD

VDD

W p n W n

Lp
p Ln
s

pCd
VDD

pCg

Rp = Rup/p = Run
VDD

ON/
OFF

Where Wp = pWup
p 1, usually p = n/p
R up
R p=

V DD L up
n
2
0.69 p C ox W up V DD V T0p
p

.=R nu

pCd
R up

V DD L up
2

0.69 p C ox W up V DD V T0p
V DD Lun
R un
2
0.69 n C ox W un V DD V T0n

L un=Lup
W un =W up

If |VT0p| = VT0n

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

50

st

1 Order RC DELAY MODLELS - Cont.


VDD VDD

Estimating PHL
1,p

VDD
A

p
1

VDD
Y

p
1,

n = fanout

pCd
2R
/
R =
nu R p
p

VDD

VDD
pCd

2
1

where Wn=Wunit => n=1, Rn=Run


Wp = pWunit

np Cg
Y

1,p

Cs = Cd

Rn

Cd

PHL

p = n/ p = 2
Rp = Rpu/p = Rn
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

nCg
pCg > Cg

Cd

RECALL for n = 1
Cgb = Cgbn + Cgbp = Cg(1 + p)
51

st

1 Order RC DELAY MODLELS - Cont.


Estimating PLH
Reff,LH = Rp = Rpu/p = Rn

pCd
Rn
PLH

VDD VDD

npCg

pCd

Rn

pC

npCg
Y

nC
C

Cd

Rn

VDD

nC
C g Rp = Rn/p

nC
nCg

Cload = (1 + 2p)C
Cd

PLH 0.69 C loadR n =0.691 p C d n C g R n


PHL 0.69C loadR n =0.691 p C d n C g R n

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

52

Propagation Delay Model Summary


Average
Current
Model

C load V HL C load V OH V 50 %p
PHL
=
I avg , HL
I avg , HL
C load V LH C load V 50 %
p V OL
PLH
=
I avg , LH
I avg , LH

PHL
Differential
Equation
Model PLH

APPROX: PHL
1st Order RC
Elmore
Model

C load V DD
2

k n V DD V T0n

PLH

C load V DD
2

k p V DD V T0p

PHL 0.69 C loadR n


PLH 0.69 C loadR p

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

53

CMOS Ring Oscillator

= SYM INV

t
PHL2
PHL1 PHL3
PLH3

PLH2

PLH1

SYM INV => PHL = PLH


Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

54

CMOS Ring Oscillator cont.

SYM INV => PHL = PLH = p

where

1
1
f= =
T 6 p

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

55

Estimation of Interconnect Parasitics

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

56

Estimation of Interconnect Parasitics cont.


crosstalk

Ideal FF value: FF = 1
FF -> Increase as t/h -> Increase, W/h <- Decrease and W/L Increase
FF < 200)
Actual(1FF< value:
1 < FF 20

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

57

Estimation of Interconnect Parasitics cont.


crosstalk

Cm = CoxFt = 30 af/um2, toxF = 0.6 um and Cpa = 1 to 10 pF


Cm = PP + FF

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

58

Estimation of Interconnect Parasitics cont.

0.3 m

(PP + FF)

0.9 m
0.6 m
0.6 m

C gb =1800 aF / m

0.3 m
0.6 m

0.3 m

Cm2d

0.6 m

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

59

DIGITAL CIRCUIT PATH DELAY


3
2
5
1

S1

O1
O2

S2

Delays through logic blocks


Net-related delays
Fanout to other logic blocks
Interconnect (wiring)

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

60

1st Order RC Segment Delay (Elmore Delay Model)


Step Source
PLH 1
t
0 0

V 1 0=0

V1(t)

1 = VDD

V 1 t=V DD 1e

t / R1 C 1

V DD
t / R C
V 50%p =
=V DD 1e

2
V DDV 50 %p 1
/ R C
e
=
=
V DD
2
PLH

Step Source
PHL 1
t
0 0

PLH

V 1 0=V DD

PLH =ln 2 R1 C 1=0.69 R 1 C 1 (1 -> 50%)


NOTE D =R 1 C 1

(0 -> 63%) = 1 time constant

ALSO PHL =ln 2 R 1 C 1=0.69 R 1 C 1


PLH = PHL =0.69 D
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

61

INTERCONNECT DELAY CALCULATIONS


R3

RC Tree Network

PLH

Step Source
1
t
0 0

R1

Lumped
RC Model
for a Wire
Segment

S
Step Source V1(0)
1
t
0 0

PHL

R2

V3(0)

R4

C2

V4(0)

C1
R6
V6(0)

R7

V7(0) R
8
7

C6

C7

C3
4

R5
C4

V5(0)

C5

8 V (0)
8

C8

1. Lump total wire resistance of each wire segment into single Rj between nodes in network.
2. Lump total capacitance into single node capacitor to GND.
3. Model RC tree Topology:
(a) Single input node S;
(b) All Ci between node i and GND;
4. Unique resistive path from source node S to any node k (k S).

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

62

INTERCONNECT DELAY CALCULATIONS

RC Tree Network
Step Source
1
R1
0
S

R3

R2

C3

R4

C2

C1

Elmore delay at node i

R5
C4

R6

R7
C6

R8

C7

C5

C8

PLH =0.69 Di =0.69 C k R ik where R ik = R j R j [ pathS i path S k ]


k =1

st

1 Order Time-Constant Model


for the Net @ node i.

Rik is the shared path resistance

Elmore delay at node 7


D7 = R1 C 1 R 1 C 2 R1 C 3R 1 C 4 R 1 C 5 R1 R 6 C 6 R1 R 6 R 7 C 7 R 1 R 6 R7 C 8
R78
R71
R72
R74
R75
R73
R77
R
76

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

63

INTERCONNECT DELAY CALCULATIONS


Elmore delay at node i
N

Di = C k Rik
k =1

Rik = R j R j [ path S i path S k ]

Elmore delay at node 5:


D5 =?

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

64

INTERCONNECT DELAY CALCULATIONS


Elmore delay at node i
N

Di = C k Rik
k =1

Rik = R j R j [ path S i path S k ]

Elmore delay at node 5

R55
D5 = R1 C 1 R1 R 2 C 2 R1 R2 C 3 R1 R 2 R 4 C 4 R1 R2 R4 R5 C 5
R53
R52
R51
R54
R 1 C 6 R 1 C 7 R 1 C 8
R56
R57
R58

Elmore delay at nodes 1 and 8

D1= R1 C 1 R1 C 2 R1 C 3 R1 C 4 R1 C 5 R1 C 6 R1 C 7R1 C 8
D8 = R1 C 1 R1 C 2 R1 C 3 R1 C 4 R1 C 5 R1 R6 C 6 R1 R6 R7 C 7

R1 R 6R 7 R 8 C 8
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

65

INTERCONNECT DELAY CALCULATIONS


RC Chain or Ladder Network

R1

C1

Wire Length L
R3

R2

C2

Elmore delay at node N

RN

C3

CN

k =1

j=1

k =1

DN =0.69 C k R Nk = C j R k

Let the RC Ladder Network be uniform, i.e. Ri = rL/N for all i N and Cj = cL/N
for all j N such that
N
j
2
cL
rL
L
2 N 1
DN = = 2 rc2 rc3 rc...N rc=rc L

2N
N
j=1 N k =1 N
rc L 2
For large N, as N (distributed RC line) DN
2
PLH =0.69 DN 0.35 r c L 2
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

66

Practical Interconnect Length Rule-of-Thumb


PHLinv =0.69C load R n
S

PLHwire =0.35 r c L 2

rL/N

rL/N

rL/N

rL/N

cL/N

cL/N

cL/N

cL/N

Rn, nC
Rp, pC

PLHtotal = PLHinv PLHwire =0.69 C load R n0.35 r c L2

Let the goal be for the layout to enable PLHtotal PLHinv


PLHtotal PLHinv PLHwire PLHinv
0.35 r c L 2 0.69C load R n

PLHinv
0.69 C load R n
L
=
0.35 r c
0.35 r c

1 PLHinv
1 0.69 C load R n
L
=
10 0.35 r c 10
0.35 r c

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

67

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

68

VDD

vin

vout

vin, vout

1 T
P avg = 0 v t i t dt
T
v SDp t =V DD v out t
v DSn t =v out t
dt
1 T /2
1 T
P avg 0 v DSn t i Dn t dt T /2 v SDp t i Dp t dt
T
T
dv out
dv out
i Dn t =C load
i Dp t =C load
dt
dt
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

69

d v out
d v out
1 T /2
1 T
P avg 0 v out C load
dt T /2 V DD v out C load
dt
T
dt
T
dt

vin, vout
VDD

1 0
1 V
P avg V C load v out t dv out 0 C load V DD v out t dv out
T
T
DD

DD

v out =0

v out
1
.= [C load
]
T
2 v

out

=V DD

v out =V DD

v out
1
[C load V DD v out
]
T
2 v

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

out

=0
70

v out =0

v out
1
P avg [C load
]
T
2 v

1
2
.= C load V DD
T

out

=V DD

v out =V DD

v out
1
[C load V DD v out
]
T
2 v

out

=0

P avg C load V 2DD f

f = operating frequency or switching frequency


Units calculation

P avg C load V

2
DD

Q
1
f = FV Hz= V 2s
= AV =W
In
General:
V
C load C total
Ctotal = total chip capacitance
2

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

71

P avg C load V 2DD f


EXAMPLE: Consider 0.1 m CMOS chip with a clock rate of 100 MHz, VDD =
2V and an average Cload = 3 fF per gate.
(a). What is the dynamic power dissipation per gate?
(b). If the chip incorporates 200,000 gates, what is the power dissipation for the
chip?
(a).

P avg / gate3 x 10
(b).

15

F
2
6 1
4V 100 x 10 s =1.2 W / gate
gate

P avg = P avg / gate200,000 gates1.2 W / gate2 x 105 gates=0.24 W


PESSIMISTIC -> NOT ALL 200,000 GATES SWITCH AT THE SAME TIME
OR AT 100 MHZ!

C EFF =C load
P avg C EFF V 2DD f
CEFF = effective capacitance -> avg. capacitance switched per cycle at f Hz.

e.g. if = 0.2, Pavg = 0.24 W -> 48 mW


Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

72

Super-Buffer to Drive Large CLOAD


standard
CMOS
logic on
die

INV1

CLOAD
VDD

PROBLEM: A minimum sized inverter drives a


large load CLOAD, leading to excessive delay, even
with a large buffer (large W/L).
CLOAD SOLUTION: Insert N inverter stages in cascade
with increasing W/L between INV1 and load
CLOAD. The total delay through N smaller stages
will be less than the delay through a single large
stage driving CLOAD.

VDD

N=3
CLOAD

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

73

Super-Buffer to Drive Large CLOAD cont.


INV1

Stage-0

CLOAD
NOTE for CMOS INV:

Cd = Cdbn + Cdbp
Cg = Cgbn + Cgbp

cascade
a -> stage scale factor > 1

Wni = aiWn0, Lni = Ln0 and Wpi = aiWp0, Lpi = Lp0 for i = 0, 1, 2, ..., N
Stage load capacitances Cloadi are also scaled by a
Cloadi = ai Cload0 = ai (Cd + aCg) for i = 0, 1, 2, .., N
when i = N: CloadN = aN Cload0 = aN (Cd + aCg) => let CLOAD = aN(aCg) = aN+1Cg
N+1

CLOAD/Cg = a

ln C LOAD / C g
=> N =
1
ln a

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

N is rounded up to nearest
integer value.
74

Super-Buffer to Drive Large CLOAD cont.

CLOAD

CLOAD

NOTE: ALL inverters Stage-0 through Stage-N have the same gate delay
PHL PLH C LOAD
d =

2
W
Let 0 = gate delay for INV1 (with a = 1) in a ring oscillator with load Cload0 = Cd + Cg
Cd a C g
Cdda C g
d0
C load0 /W 0
C
C
For Stage-0:
=
=
d0 =0
Cdd C g /W or
Cdd C g
0 C
Cdd C g
0
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

75

Super-Buffer to Drive Large CLOAD cont.

d0
C load0 /W 0
C dd a C g
C dd a C g
=
=
d0 =0
For Stage-0:
Cdd C g /W 0 orC dd C g
0 C
Cdd C g

Cdd a C g
d1
C load1 /a W 0
a Cdd a 2 C g /a
C
For Stage-1:
=
=
d1=0
=d0
C
C
C
/W
C
C
C
C
C
0
d
g
0
g
g
d
dd
dd
dN C load1 /a N W 0 a N C
Cdd a N 1 C g /a N
C dd a C g
=
=
dN = 0
=d0
For Stage-N:
C
C
C
/W
C
C
C
C
0
g
0
g
g
dd
dd
dd
Cdd a C g Choose N and a
TOTAL DELAY total = N 1d0 = N 10 C
C ddC g to minimize
total

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

76

Super-Buffer to Drive Large CLOAD cont.


Cdd a C g
C
total = N 10
Cdd C g
C
ln C LOAD / C g
N 1=
ln a

Cd a C g
ln C LOAD /C g
C
total =
0
ln a
C dd C g

Wni = aiWn0

Wpi = aiWp0

TO MINIMIZE total:
d total
C LOAD 1/a CCdda C g
Cg
1
=0 ln
[

]=0
2
Cdd C g ln a CCddC g
da
Cg
ln a C
=0
Cdd
aopt [ln a opt 1]=
Cg
Cd
ln a opt =1 a opt =e 1 =2.718
ln C
/C g
is rounded
up to nearest
Since Cd > Cg, Cd =N0=is onlyLOAD
an academic
special
case.
1 N
integer value.
ln aopt
Since Cd > Cg, then Cd = 0 is only an academic special case.

aaopt
e=2.718
opt e=2.718
Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

77

Super-Buffer to Drive Large CLOAD cont.


EXAMPLE: Design a Buffer using a scaled cascade of inverters to achieve
minimum total delay ttotal when CCLOAD
= 100 CCgg. Consider the case where
LOAD 100
Cd = 2Cg.
Cd = 2Cg => plot aopt as function of Cd/Cg: aopt = 4.35 => ln aopt = 1.47
ln C LOAD /C g
ln aopt
4.61
ln C LOAD /C g
N=
1=2.13 N =3
1.47

Plot using Excel, MathCad, MatLab.

N 1=

a opt =4.35

i
1
Cd/Cg = 2

e
Cdd

Cg

=aopt [ln aopt 1]

C LOAD 41.47
e Suitable
=100

e Design?
=365
Sub-Optimum
Cg
Wni/Wn0
Wpi/Wp0
(aopt)1 = 4.35
(aopt)1 = 4.35
3.131.47

(aopt)2 = 18.92

(aopt)2 = 18.92

(aopt)3 = 82.31

(aopt)3 = 82.31

rd

N+1 with little impact.


3 stageCcan be/Celiminated
NOTE:
=
a
= 82 for N = 2
LOAD g
= 358 >> 100 for N = 3

Kenneth R. Laker, University of Pennsylvania, updated 25Feb14

78