MUX

4:1 MUX
module mux4to1(y, s, i);
output reg y;
input [1:0]s;
input [3:0]i;
always@(s or i)
begin
case(s)
2'b00 : y=i[0];
2'b01 : y=i[1];
2'b10 : y=i[2];
2'b11 : y=i[3];
endcase
end
endmodule

2:1 MUX

module mux2to1(y, s, i);

input s;
input [1:0]i;
output reg y;
always@ (s or i)
y=s?i[1]:i[0];

endmodule
MUX 8:1

module mux8to1(y, i, s);

output y;
input [7:0]i;
input [2:0]s;
wire [1:0]w;
mux4to1 m1(w[0],s[1:0],i[3:0]);
mux4to1 m2(w[1],s[1:0],i[7:4]);
mux2to1 m3(y,s[2],w);
endmodule