8085 Interrupts

Hardware & Software

Interrupts

Interrupts
Interrupt means requesting processor to pay

its attention temporarily to some other

issues i.e.
When requested processor should temporarily

suspend its normal execution.

Processor should execute a subroutine called

Interrupt service subroutine (ISS) to answer the

request.
It should resume its normal execution exactly

from the same point where it has left (in first

Step).

Interrupts (Contd.)
A processor can normally be interrupted by
two methods, either by an instruction or by
hardware. Accordingly the interrupts may
be classified as
Software Interrupts
Execution of an instruction causes an interrupt to
processor.

Hardware Interrupts
Application of an appropriate logic status (HIGH/LOW)
on a hardware pin of processor causes an interrupt to
processor.

Software Interrupts
8085 has an special instruction RST n
that can be used as software interrupt.
RST n means Restart (RST) execution from a
memory location addressed by the integer n.
n is an integer that can vary from 0 to 7.
Memory address given by n can be calculated as,
Address = n * 8.
E.g. RST 3 Address = 3 * 8 = 24D = 18H =
0018H. So RST 3 means restart execution from
memory location 0018H.

Software Interrupt (Contd.)

RST n is normally used as Software Breakpoint
Interrupt.
Such interrupts can be used to store status of
program which is many times useful for debugging.
Recall the use of RST 5 in Lab
In order for processor to resume exactly from the
same point where it has left it is necessary that last
instruction of ISS should be RET.

RST n
RST n
E.g. RST 3
Calculate address for RST 3 i.e. 0018H

(SP-1) PCH
(SP-2) PCL
SP SP 2

PC 0018H

PUSH Return
Address into
the Stack

RST n (Contd.)
Execution of RST n takes 3 Machine cycles namely,
Opcode Fetch, Memory Write and Memory Write.
Opcode Fetch takes 6 T-States, since it not only
fetches & decode the instruction, but also calculates
the address for n.
Rest of the two write cycles stores return address
into the stack so that processor can resume its
normal execution sequence.

RST n (Contd.)
It is clear that, RST 3 means Restart (RST)
execution from memory location 0018H after storing
return address in stack.
RST 3 can equivalently be said CALL 0018H.
Hence, RST n is sometimes, also called as 1-byte
CALL instruction.

RST n (Contd.)
Restart address 0018H for RST 3 is also called
Vector Address for RST 3 i.e. Interrupt Vector
Address for RST 3 is 0018H.
In the similar analogy the restart number n, in
RST n, is called Interrupt Vector.
Since both the Interrupt Vector and Interrupt
Vector Address represents same thing, the memory
address, the two terms are used synonymously.

RST n (Contd.)
A table comprising all
the vector addresses
for instruction RST n
(n=0 to 7) is called
Interrupt Vector Table
and is shown next.

Vector
RST n
(n)
Instruction

Vector
Address

RST 0

0000H

RST 1

0008H

RST 2

0010H

RST 3

0018H

RST 4

0020H

RST 5

0028H

RST 6

0030H

RST 7

0038H

Hardware Interrupts
8085

has

several

hardware

pins

through which, an interrupt request

can

be

lodged.

Below

are

list

interrupt signals offered by 8085

TRAP (RST 4.5)
RST 7.5
RST 6.5
RST 5.5
INTR & INTA

of

Hardware Interrupts (Contd.)

Vectored

Interrupts

&

Non-Vectored

Interrupts
Edge Triggered Interrupts & Level Triggered
Interrupts
Maskable
Interrupts.

Interrupts

&

Non-Maskable

Interrupt Structure

ORGANIZATION OF TRAP

Interrupt Vector Table

Vector addresses for
hardware
interrupts
are in boldface. Non
boldface addresses are
for software interrupts.
Note that only 4-byte
memory
space
is
available between RST
4.5 & RST 5 and so on.

Vector
RST n
(n)
Instruction

Vector
Address

RST 0

0000H

RST 1

0008H

RST 2

0010H

RST 3

0018H

RST 4

0020H

4.5

TRAP
RST 4.5

0024H

RST 5

0028H

5.5

RST 5.5

002CH

RST 6

0030H

6.5

RST 6.5

0034H

RST 7

0038H

Interrupts Response of 8085

Assume, initially all the interrupts are enabled
Any of the hardware interrupt is activated.
8085

finishes

the

currently

executing

instruction.
It stores return address in stack through stack
pointer.
It disables the INTE F/F to avoid multiple
interrupts from the same source. Programmer
should enable INTE F/F in ISS.

Interrupts Response (Contd.)

It loads the Interrupt vector address in program
counter and starts execution of ISS.
In ISS, last instruction should be RET so that
processor can resume its execution sequence
which it was carrying before interrupt.
It is recommended to save registers & PSW in the
beginning of ISS if they are critical in normal
execution sequence.
These status should be retrieved from stack
before RET.

Interrupts Instructions
EI Enable INTE Flip-Flop i.e. Enable
Interrupt structure of 8085
E.g. EI
It applies a logic 1 on the S input of INTE F/F,
thereby, enabling interrupts.

DI Disable INTE Flip-Flop i.e. Disable

Interrupt structure of 8085
E.g. DI
It applies a logic 1 on the R input of INTE F/F,
thereby, disabling interrupts.

Interrupts Instructions - SIM

SIM Set Interrupt Mask i.e. Mask or
Unmask (i.e. Enable or Disable) individual
maskable interrupts.
E.g. SIM
Take the binary word stored in accumulator and
use it to set interrupt mask.
The word stored in accumulator is called SIM
word whose format follows in next slide.
A SIM word should be prepared accordingly and
stored in accumulator before execution of SIM.

SIM WORD
SOD SOE

RST
MSE M 7.5 M 6.5 M 5.5
7.5

SOE Serial Output Enable

i.e. enable SOD bit in SIM.
SOD Serial Output Data Bit
SOE

SOD

OPERATION

SOD Line
Unaffected

Output 0 on
SOD Line

Output 1 on
SOD Line

RST 7.5 Reset RST 7.5. If set to

1, RST 7.5 F/F will be reset.

Mask for RST 7.5, RST

6.5, RST 5.5. Put 1 to
mask the interrupt and put
0 to unmask the interrupt.
Mask Set Enable Enable the
masking bits M 7.5, M 6.5 and
M 5.5.
If MSE is 1 individual interrupts
can
be
masked/
unmasked
through Masking bits. If MSE is 0
any status of masking bits will not
affect interrupts.

A Simple Program
Write an 8085 routine to enable INTE F/F and to unmask
RST 6.5 and RST 5.5.
SIM Word
SOD SOE X
0

RST
7.5

MSE

M
7.5

M
6.5

M
5.5

MVI A, 1CH ; Hex value for SIM

SIM ; Enable RST 6.5 & RST 5.5
EI ; Enable Interrupts of 8085
RET ; Back to Caller Program

1CH

Interrupts Instructions - RIM

RIM Read Interrupt Mask i.e. Read status of
maskable interrupts and pending interrupts.
E.g. RIM
Read status of all the maskable interrupts that
weather they are masked or not.
Read status of all the pending interrupts (i.e.
interrupt requests lodged but still not served).
All the status are compiled as 8-bit binary word,
called RIM word (shown in next slide).
Execution of RIM stores RIM word in accumulator.

RIM Word
SID

I
7.5

I
I
6.5 5.5

SID Serial Input

Data bit.

Interrupt Pending Status If a

bit
is
1
the
corresponding
interrupts is pending otherwise it
is not pending.

IE

M 7.5 M 6.5 M 5.5

Mask Status for RST 7.5,

RST 6.5, RST 5.5. If a bit
is 1 the corresponding
interrupts
is
masked
otherwise unmasked.

Interrupt Enable Flag If this

bit is 1, it indicates that INTE FlipFlop is SET i.e. interrupt structure
of 8085 is enabled otherwise the
interrupt structure is disabled.

A Simple Program
Write an 8085 routine to check if RST 5.5 is pending?
Store 0 at 2500 if it is not pending otherwise store 1.

SID

I
7.5

I
6.5

I
5.5

IE

M
7.5

M
6.5

M
5.5

RIM

; Read RIM word in Accumulator.

10H

ANI 10H ; Check status of I 5.5.

JZ DN1 ; Is Status 0? YES, Go to DN1 as A=00
MVI A, 01
DN1:
RET

; NO, Load 1 in Accumulator i.e. A=01.

STA 2500H ; Store status.

; Back to Caller Program.

Example of Interrupt Program

Write an 8085 ALP that will wait for RST 6.5,
continuously. It is required that every occurrence
of RST 6.5 should add two data items stored at
2500 and 2501 and store the result at 2502.
Enable INTE F/F and RST 6.5 in main program.
An ISS should be written to read and add the data
In order to wait continuously for RST 6.5 we can
use unconditional JMP.
Vector address for RST 6.5 is 0034H.
ISS can not be stored at 0034H since vector
address for 0038H giving us only 4-byte for ISS.

Interrupt Program (Contd.)

We decide to store ISS at address 2400H.
We can store JMP 2400H at 0034H, which takes
only 3-bytes.
So, every occurrence of RST 6.5 will execute an
ISS at location 2400H.

RST 6.5
Pin

0034H C3
0035H 00

JMP
2400H

0036H 24H
0037H

--

--

2400H

ISS

2401H

Interrupt Program (Contd.)

MAIN

ISS at 2400H

P
M
J

Enable
Interrupts

Wait for
Interrupt

.5
6
T
RS

H
0
0
4
2

Execute ISS

0034H
Return to MAIN

Interrupt Program (Contd.)

; Main Program at 2000
MVI A, 1DH

; Hex value for SIM

SIM

; Enable RST 6.5.

EI

; Enable Interrupts of 8085.

HERE: JMP HERE

; Wait for interrupt.

SIM Word to enable RST 6.5

SOD SOE X
0

RST
7.5

MSE

M
7.5

M
6.5

M
5.5

1DH

Interrupt Program (Contd.)

At vector address 0034
0034 JMP 2400

; Go to ISS at 2400.

;ISS at 2400
LDA 2500
MOV B,A

; Get first number in B.

LDA 2501

; Get second number in A.

ADD B

; Add the numbers.

STA 2502

; Store the result.

EI

; Re-enable INTE F/F.

RET

; Back to main program.

INTR & INTA

Generation of RST 7 for INTR