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3. Draw the truth table and state diagram of SR flip-flop. (N/D 2015)
State diagram
Truth table
(Dec 2011)
In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K
and Qp make eight possible combinations, as shown in the conversion table below. D is
expressed in terms of J, K and Qp.
The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing
the conversion from D to JK are given in the figure below.
(Dec 2010)
11. How many flipflops are required to build a binary counter that counts from 0 to 1023.
(May 2013)
Number of flip-flops is given as 2n count +1, where n is the number of flipflops.
Therefore, 2n 1023 +1 , i.e., 2n 1024. It implies , n = 10
Hence, 10 flip-flops are required to build a binary counter that counts form 0 to 1023.
12. Define : Latches.
(Nov 2013)
The flip-flops that operate with signal levels are referred as latches. Latch is a memory cell
which is capable of storing one bit of information , ie. Logic 1 or logic 0. Latches are
controlled by enable signals and they are level sensitive devices. Latches are basic building
blocks of flip-flops.
13. Sketch the logic diagram of a clocked SR flip flop.
(May 2014)
17. Mention any two differences between the edge triggering and level triggering.
(May2010,May2012)
Edge Triggering
Level Triggering
Flip-flop changes its state either at positive When the clock pulse goes high the flip-flop is
edge or negative edge of the clock pulse and is said to be level triggered flip-flop.
sensitive to its inputs only at this transition of When flip-flop, changes its state by applying
the clock.
COUNTERS
18. What is meant by programmable counter? Mention its application.
A counter that divides an input frequency by a number which can be programmed is called
programmable counter. Applications: Frequency division, digital clock, stop watch and
programmable logic controller.
2. Compare the logics of synchronous counter and ripple counter.
Synchronous counter
Ripple ( Asynchronous counter)
In Synchronous counter, no connection exists Here flip-flops are connected in such a way
between output of first flip-flop and clock that output of first flip-flop drives the clock
input of next flip-flop.
If the "clock" pulses are applied to all the
such
counter
is
called
as
synchronous counter.
Circuit is simple.
High speed counters.
3. What is a ripple counter?
Circuit is complex.
Low speed is the drawback.
A ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop
drives the clock input of the following flip-flop. A ripple counter is also called as asynchronous
counter or a serial counter, as the clock input is applied only to the first flip-flop, also called the
input flip-flop in the cascaded arrangement.
4. Explain Modulo N counter (MOD-N counter).
In general, an n-bit ripple counter is called as modulo-N counter. Where, MOD number = 2 n. For
example, the 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as
MOD-8 counter.
Type of modulus
Mealy Machine
Its output is a function of present state as well
as present input.
Input changes does not affect the output.
Input changes may affect the output of the
circuit.
It requires more number of states for It requires less number of states for
implementing the same function.
implementing the same function.
STATE DIAGRAM -STATE REDUCTION AND STATE ASSIGNMENT
22. State the rules for state assignment. .(A/M 2015)
Assignment of values to state variables is called state assignment. A binary value is assigned to
each of the states
23. What is state reduction?
The reduction of number of states in a state table is called as state reduction .By state
reduction the number of flip-flops in a sequential circuit is reduced.
24. What is a state diagram?
25.