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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

ECEN 651
MICROPROGRAMMED CONTROL OF DIGITAL SYSTEMS

FINAL PROJECT
IMPLEMENTATION OF A 32 BIT PIPELINED MIPS CPU

PROJECT REPORT
SUBMITTED BY
SWAPNIL S. LOTLIKAR
UIN: 218009104
DATE: 26th NOVEMBER 2008

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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

TABLE OF CONTENTS

1. PROBLEM STATEMENT .....................................................................................................4


2. DESIGN SPECIFICATIONS.................................................................................................4
3. MODULE SPECIFICATIONS ...............................................................................................7
3.1. INST_FETCH ...................................................................................................................7
3.1.1. BLOCK DIAGRAM ........................................................................................................7
3.1.2. FUNCTIONS .................................................................................................................7
3.1.3. PIN INTERFACE...........................................................................................................8
3.2. INST_DECODE ................................................................................................................9
3.2.1. BLOCK DIAGRAM ........................................................................................................9
3.2.2. FUNCTIONS .................................................................................................................9
3.2.3. PIN INTERFACE.........................................................................................................10
3.3. REGISTER FILE ............................................................................................................11
3.3.1. BLOCK DIAGRAM ......................................................................................................11
3.3.2. FUNCTIONS ...............................................................................................................11
3.3.3. PIN INTERFACE.........................................................................................................11
3.4. INSTRUCTION EXECUTE .............................................................................................12
3.4.1. BLOCK DIAGRAM ......................................................................................................12
3.4.2. FUNCTIONS ...............................................................................................................12
3.4.3. PIN INTERFACE.........................................................................................................13
3.5. ALU CONTROLLER .......................................................................................................14
3.5.1. BLOCK DIAGRAM ......................................................................................................14
3.5.2. FUNCTIONS ...............................................................................................................14
3.5.3. PIN INTERFACE.........................................................................................................14
3.6. ALU ................................................................................................................................16
3.6.1. BLOCK DIAGRAM ......................................................................................................16
3.6.2. FUNCTIONS ...............................................................................................................16
3.6.3. PIN INTERFACE.........................................................................................................16
3.7. MEMORY_ACC..............................................................................................................17
3.7.1. BLOCK DIAGRAM ......................................................................................................17
3.7.2. FUNCTIONS ...............................................................................................................17
3.7.3. PIN INTERFACE.........................................................................................................17
3.8. MEMORY .......................................................................................................................19
3.8.1. BLOCK DIAGRAM ......................................................................................................19
3.8.2. FUNCTIONS ...............................................................................................................19
3.8.3. PIN INTERFACE.........................................................................................................19
3.9. CNTL_PATH ..................................................................................................................20
3.9.1. BLOCK DIAGRAM ......................................................................................................20
3.9.2. FUNCTIONS ...............................................................................................................20
3.9.3. PIN INTERFACE.........................................................................................................20
4. RTL CODE.........................................................................................................................22
4.1. INST_FETCH.V ..............................................................................................................22
4.2. INST_DECODE.V ..........................................................................................................26
4.3. REG_FILE.V ..................................................................................................................31
4.4. INST_EXECUTE.V .........................................................................................................33
4.5. ALU_CONTROLLER.V...................................................................................................38
4.6. ALU.V.............................................................................................................................40
4.7. MEMORY_ACC.V ..........................................................................................................44
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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


4.8. MEMORY.V ....................................................................................................................47
4.9. DATA_PATH.V ...............................................................................................................49
4.10. CNTL_PATH.V ...............................................................................................................53
4.11. CONSTANTS.V ..............................................................................................................62
4.12. MIPS_TOP.V..................................................................................................................64
5. TEST BENCH CODE .........................................................................................................66
6. MAIN CODE ......................................................................................................................68
7. FINAL REGISTER FILE CONTENTS.................................................................................70
8. FINAL DATA MEMORY CONTENTS .................................................................................71
9. CONCLUSION ...................................................................................................................72
10.
FUTURE IMPROVEMENTS ...........................................................................................72
11.
WAVEFORMS AND SCHEMATICS ...............................................................................72

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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

1. PROBLEM STATEMENT
The goal of the project is to design and implement a subset of a 32-bit pipelined MIPS
processor using verilog hardware description language. The design has to be tested using a set
of assembly language instructions. Finally the MIPS Processor will be synthesized using the
Synopsys Design Compiler.

2. DESIGN SPECIFICATIONS
In this project we implement a 32-bit MIPS processor using the standard 5-stage pipeline. The
basic block diagram for the processor is given in the figure below:

The MIPS Processor implementation basically has the following components:


1. Instruction Memory This memory is used to hold the instructions to be executed. The
instructions are written to the memory in hexadecimal format. In the current
implementation the instruction memory is 64 Words deep.
2. Instruction Register The Instruction register is used to hold the instruction read out
from the instruction memory. The size of this register is 32-bits. This register sits in the
IF/ID series of pipeline registers.

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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


3. Program Counter The program counter is used to hold the address of the current
instruction being executed. The program counter is directly used as the address to the
Instruction memory. The size of this register is 32-bits.
4. Register File The current MIPS implementation has a 32 Registers each of 32 bits.
The register file has two read ports and a single write port.
5. Register A and Register B These two 32-bit registers are used to hold the value of the
registers read from the register file. These registers will be used for processing by the
Arithmetic Logical Unit. These registers sit along with the ID/EX series of pipeline
registers.
6. Sign Extension Unit This module basically sign extends a 16 bit value to a 32 bit value.
7. Left Shifter This module is basically used to left shift a signal by 2 (i.e. multiply the
number by four). This module will be basically used to generate offsets for the control
instructions like jump and branch.
8. Arithmetic Logical Unit (ALU) This is one of the most important modules in the MIPS
Architecture. This module implements most of the functionality related to the arithmetic
and the logical processing required on the data. The functions implemented by this
module will be explained in a latter section.
9. ALU Out Register This 32-bit register is used to hold the result produced by the
arithmetic and the logical processing unit. This register sits along with the EX/MEM
series of pipeline registers.
10. ALU Controller The controller is used to generate the appropriate control signals to the
ALU based on certain fields in the instruction.
11. Data Memory This memory is used to store data required by the instructions. In the
current implementation this memory is also 64-Words deep. It has one read port and one
write port.
12. Memory Data Out Register This 32-bit register is used to hold the data read from the
Data memory. This register sits along with the MEM/WB series of pipeline registers.
13. Controller The controller generates the appropriate control signals to the various
modules in the data path mentioned above based on the type of the instruction getting
executed.
Note: In this implementation of the MIPS processor all the registers are Positive Edge Triggered
registers.
The MIPS processor implementation follows the standard 5-stage pipeline. The pipeline stages
can be divided as follows:
1. Instruction Fetch This stage fetches the next instruction from instruction memory using
the address in Program Counter (PC) and stores the instruction In the Instruction
Register (IR).
2. Instruction Decode This stage decodes the instructions stored in the Instruction
Register (IR) and reads any operands required from the Register File. In the current
implementation the Jump Register instruction also gets resolved by the end of this stage
3. Instruction Execute This stage executes the instruction. All the ALU operations are
done in this stage. In the current implementation the Branch instruction also gets
resolved by the end of this stage.
4. Memory Access This stage performs any memory accesses required by the current
instruction. This stage is exercised only by the load and store instructions. For load
instructions data memory is read and for store instructions write is performed to the data
memory.

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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


5. Register Writeback For instructions that generate a result to be written into a
destination register, the write back writes the result back to the register file.
Pipelining has significant advantage over the normal multi cycle implementation interms of the
number of cycles required for execution of the instruction. In multi-cycle implementation the
instruction execution does not overlap like in the case of pipelined implementation. That is to
say, a new instruction is fetched only after the old instruction is completely executed.

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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3. MODULE SPECIFICATIONS
This section describes each of the individual modules in a little more detail, listing the functions
performed by each module, block diagram and the pin interface of each module. The modules
are listed below:

3.1. INST_FETCH
3.1.1.

BLOCK DIAGRAM
IF/ID
JMP OFFSET
CALCULATION

ADDER

BRANCH OFF
JR INST OFF

MUX

JUMP OFF

PC REG

INSTRUCTION
MEMORY

PC+4

PC_SOURCE

3.1.2.

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FUNCTIONS
Implements the mux to select the new value to be loaded in the PC Register (The
new value can be either PC+4, Jump Offset, Jump register offset or Branch offset)
Reads the Instruction memory and stores the result in the Instruction Register (IR)
Implements the adder to generate PC+4
Implements the left shifter to generate the jump offset.
Implements the PC register in the IF/ID stage

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3.1.3.

PIN INTERFACE

PIN NAME
clk
resetn
Jr_inst
Jr_offset
Br_cond
Branch_offset
Data_out_31_26
Data_out_25_21
Data_out_20_16
Data_out_15_0
If_id_pc_reg
Inst_opcode
Inst_funct

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TYPE WIDTH
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT

1
1
1
32
1
32
6
5
5
16
32
6
6

DESCRIPTION
Clock signal to the module
Active low reset signal
Jump register instruction indication
Jump register instruction offset
Branch condition indication
Branch instruction offset
Opcode field of instruction
rs field of instruction
rt field of instruction
rd/imm field of instruction
Pipeline register for PC
Instruction opcode field (not a registered output)
Instruction function field (not a registered output)

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3.2. INST_DECODE
3.2.1.

BLOCK DIAGRAM
ID/EX

Jr_offset
Inst_read_reg_addr1
Inst_read_reg_addr2

reg_file_rd_data1
A

rt
Reg_wr_addr

REGISTER
FILE

rd

reg_file_rd_data2
B

5d31
Reg_wr_data

Reg_dst
Alu_data_out
mdr_data_out
SIGN EXT
Mem_to_reg

LEFT
SHIFT

Inst_imm_field

3.2.2.

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FUNCTIONS
Implements the write address select mux (selects either rt ,rd fields or 30(overflow
bit register) or 31(JAL instruction return address) as write back address to the
register file during register write back stage)
Implements the write data select mux (selects either the alu data out or memory data
out or overflow indication as the write back data for the register file during write back
stage)
Generates the sign extended immediate and sign extended left shifted immediate
registers to be used in the instruction execute stage of the pipeline. These are used
for Load/Store and some I-Type Instructions
Generates the 32 bit immediate register without sign extension by concatenating
zeros to the 16 bit immediate field from the instruction. This is used for I-Type
instructions

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3.2.3.

Reads the register file with rs and rt as read addresses on its two read ports and
stores the read data in the reg_A and reg_B registers respectively for use by the
ALU in instruction execution stage.
Implements the ID/EX pipeline registers for Program Counter(PC), Instruction
Function field, Instruction Opcode and rt (To be passed on till the write back stage)
Generates the Jump Register instruction indication by sampling the opcode and
function bits of the instruction
Generates the jump register offset by using the contents read from register rs of the
register file

PIN INTERFACE

PIN NAME
Clk
Resetn
Inst_read_reg_addr_1
Inst_read_reg_addr_2
Inst_wr_addr_1
Inst_wr_addr_2
Mdr_data_out
Alu_data_out
Reg_file_wr_en
Reg_dst
Mem_to_reg
Inst_imm_field
If_id_pc_reg
If_id_inst_31_26
Mem_wb_overflow
Reg_A
Reg_B
Imm_fld_wo_sign_ext
Sign_ext_imm
Sign_ext_ls_imm
Id_ex_pc_reg
Id_ex_inst_5_0
Id_ex_inst_31_26
Id_ex_inst_20_16
Jr_inst
Jr_offset

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TYPE WIDTH
IN
IN

1
1

IN

IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

5
5
32
32
1
2
1
16
32
6
1
32
32
32
32
32
32
6
6
5
1
32

DESCRIPTION
Clock signal to the module
Active low reset signal
rs field of the instruction connected to read port 1
of register file
rt field of the instruction connected to read port 2
of register file
Rt field of the instruction
Rd field of the instruction
Read data from memory
Alu result to be written to the memory
Write enable to the register file
Select line to the write address select mux
Select line to the write data select mux
Immediate field of the instruction
IF/ID Pipeline register for PC
IF/ID Pipeline register for instruction opcode
Overflow indication pipeline register
Data fetched from register rs
Data fetched from register rt
Original immediate field without sign extension
Immediate field with sign extension
Immediate field with sign extension and left shift
ID/EX pipeline register for PC
ID/EX pipeline register for instruction funct bits
ID/EX pipeline register for instruction opcode bits
ID/EX pipeline register for instruction rt field
JR instruction indication
Jump offset for JR instruction

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3.3. REGISTER FILE


3.3.1.

BLOCK DIAGRAM

clk
resetn
Reg_rd_data1

Reg_rd_addr1
REG

Reg_rd_addr2

FILE
Reg_wr_en

Reg_rd_data1

Reg_wr_addr
Reg_wr_data

3.3.2.

3.3.3.

FUNCTIONS
Implements the 32 Word deep General Purpose register bank.
Implements two read ports and one write port to the register bank
Initializes all GPRs to 0 under reset

PIN INTERFACE

PIN NAME
Clk
Resetn
Reg_rd_addr_1
Reg_rd_addr_2
Reg_wr_en
Reg_wr_addr
Reg_wr_data
Reg_rd_data1
Reg_rd_data2

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TYPE WIDTH
IN
IN
IN
IN
IN
IN
IN
OUT
OUT

1
1
5
5
1
5
32
32
32

DESCRIPTION
Clock signal to the module
Active low reset signal
Read address to port 1 of the register file
Read address to port2 of the register file
Write enable to the register file
Write address to the register file
Write data to the register file
Read data from port 1
Read data from port 2

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3.4. INSTRUCTION EXECUTE


3.4.1.

BLOCK DIAGRAM
PC

Branch_offset

Sign_ext_ls_imm

Br_cond
opcode

Reg_A_data
Alu_res
ALU

Reg_B_data

overflow

Sign_ext_imm
Imm_fld_wo_sign_ext

Alu_cntl_ip
funct
opcode

ALU
CONTROLLER

EX/MEM

Alu_op

3.4.2.

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FUNCTIONS
Implements the ALU input A select mux
Implements the ALU input B select mux
Instantiates the ALU and the ALU Controller modules
Generates branch condition indicator for branch instructions
Generates branch offset for the branch instructions using sign extended left shifted
immediate generated in the Instruction Decode stage. This along with branch
indication is used by the pc select mux in the instruction fetch module
Generates the overflow indication for signed addition and subtraction instructions
Implements alu_out register to store the alu output
Implements the EX/MEM Pipeline registers

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3.4.3.

PIN INTERFACE

PIN NAME
Clk
Resetn
Pc_reg
Reg_A_data
Reg_B_data
Sign_ext_imm
Sign_ext_ls_imm
Imm_field_wo_sign_ext
Inst_reg_5_0
Inst_opcode
Alu_src_A
Alu_src_B
Alu_op

TYPE WIDTH
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

1
1
32
32
32
32
32
32
6
6
1
3
2

Id_ex_inst_20_16
Alu_out
Ex_mem_reg_B_data
Ex_mem_inst_5_0
Ex_mem_inst_31_26
Ex_mem_inst_20_16
Ex_mem_inst_15_11

IN
OUT
OUT
OUT
OUT
OUT
OUT

5
32
32
6
6
5

Ex_mem_overflow
Br_cond
Branch_offset

OUT
OUT
OUT

1
1
32

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DESCRIPTION
Clock signal to the module
Active low reset signal
ID/EX pipeline register for PC
Read data from Register A
Read data from Register B
Sign extended immediate number
Immediate field with sign extension and left shift
Original immediate field without sign extension
ID/EX pipeline register for instruction funct bits
ID/EX pipeline register for instruction opcode
Select line for the ALU Input A select Mux
Select line for the ALU Input B select Mux
Select line used to select the type of ALU
operation required. This is given as an input to the
alu controller.
ID/EX pipeline register for rt field of instruction
Alu output register
EX/MEM pipeline register for the register B data
EX/MEM pipeline register for instruction funct bits
EX/MEM pipeline register for instruction opcode
EX/MEM pipeline register for rt field of instruction
EX/MEM pipeline register for rd field of
instruction
EX/MEM pipeline register for overflow indication
Branch condition indicator
Branch offset for the branch instruction

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3.5. ALU CONTROLLER


3.5.1.

BLOCK DIAGRAM
funct
ALU
CONTROLLER

opcode

Alu_cntl_ip

Alu_op

3.5.2.

3.5.3.

FUNCTIONS
Generates the control inputs to the ALU based on the instruction opcode, instruction
function bits and the alu_op field

PIN INTERFACE

PIN NAME
Inst_reg_5_0
Alu_op
Inst_opcode
Alu_cntl_ip

TYPE WIDTH
IN
IN
IN
OUT

6
2
6
4

DESCRIPTION
Instruction function field
Type of alu operation required
Instruction opcode field
Control lines to the ALU

The relationship between function field, alu_op, instruction opcode and alu_cntl_ip is
shown in the table below:
ALU_OP FUNCT OPCODE
ALU_CNTL_IP
0
X
X
4h2 Signed addition
1

4h4 Signed subtraction

6h04
6h06
6h20
6h21
6h22
6h23
6h24
6h25
6h26
6h27
6h2A
6h2B

X
X
X
X
X
X
X
X
X
X
X
X

4h0 Logical shift left


4h1 Logical shift right
4h2 Signed addition
4h3 Unsigned addition
4h4 Signed subtraction
4h5 Unsigned subtraction
4h6 Bitwise AND
4h7 Bitwise OR
4h8 Bitwise XOR
4h9 Bitwise NOR
4hA Set if less then signed
4hB set if less then unsigned

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DESCRIPTION
Used for Load/Store
class of Instructions
Used
for
Branch
Instructions

Used for R-Type


instructions (Alu
operation decided by the
function field of the
instruction)

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


ALU_OP FUNCT OPCODE
ALU_CNTL_IP
X
6h08
4h2 Signed addition
X
6h09
4h3 Unsigned addition
X
6h0C
4h6 Bitwise AND
X
6h0D
4h7 Bitwise OR
3
X
6h0E
4h8 Bitwise XOR
X
6h0A
4hA Set if less then signed
X
6h0B
4hB set if less then unsigned
X
6h03
4hC Operand A + 0

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DESCRIPTION
Used for I-Type
Instructions(Alu
operation decided by the
opcode field of the
instruction)

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3.6. ALU
3.6.1.

BLOCK DIAGRAM
Zero, not_equal,
ls_then,
gr_then,
ls_then_eq

ALU

Alu_out
overflow

B
Alu_cntl_ip

3.6.2.

3.6.3.

FUNCTIONS
Implements all the Arithmetic, Logical and Shift operations
Detects overflow for signed addition and subtraction operations
Generates conditions required for detecting branches like zero, not_equal_to,
less_then, greater_then and less_then_equal

PIN INTERFACE

PIN NAME

TYPE WIDTH

A
B
Alu_cntl_ip
Alu_res
Zero
Not_equal
Ls_then
Gr_then
Ls_then_eq
overflow

IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT

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32
32
4
32
1
1
1
1
1
1

DESCRIPTION
Operand A input to the ALU
Operand B input to the ALU
ALU control input from the ALU Controller
Result of the ALU Operation
Indicator for reg_A == reg_B
Indicator for reg_A != reg_B
Indicator for reg_A < reg_B
Indicator for reg_A > reg_B
Indicator for reg_A <= reg_B
Overflow Indicator for signed addition/subtraction

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3.7. MEMORY_ACC
3.7.1.

BLOCK DIAGRAM

Mem_addr
Data_out
Mem_rd
DATA MEMORY

D
R

Mem_wr
Data_in

Alu_out
overflow

MEM/WB

3.7.2.

3.7.3.

FUNCTIONS
Performs read to the Data memory for Load Instructions
Performs write to the Data memory for Store Instructions
Implements the MEM/WB pipeline registers for alu_out, rt/rd instruction fields and
overflow
Implements the memory data register which stores the read data from data memory

PIN INTERFACE

PIN NAME
Clk
resetn
Alu_out
Mem_rd
Mem_wr
Mem_wr_data
Ex_mem_inst_20_16
Ex_mem_inst_15_11
Ex_mem_overflow
Mdr_data_out
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TYPE WIDTH
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT

1
1
32
1
1
32
5
5
1
32

DESCRIPTION
Clock signal to the module
Active low reset signal
Effective memory address from ALU
Read signal to the data memory
Write signal to the data memory
Write data to the data memory
EX/MEM pipeline register for rt instruction field
EX/MEM pipeline register for rd instruction field
EX/MEM pipeline register for overflow indication
Memory data output register

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

PIN NAME
Mem_wb_alu_out_reg
Mem_wb_inst_20_16
Mem_wb_inst_15_11
Mem_wb_overflow

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TYPE WIDTH
OUT
OUT
OUT
OUT

32
5
5
1

DESCRIPTION
MEM/WB pipeline register for alu_out
MEM/WB pipeline register for rt instruction field
MEM/WB pipeline register for rd instruction field
MEM/WB pipeline register for overflow indication

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3.8. MEMORY
3.8.1.

BLOCK DIAGRAM

clk
resetn
Data_out

Mem_addr
DATA MEMORY
Mem_rd
Mem_wr
Data_in

3.8.2.

3.8.3.

FUNCTIONS
This is a generic module and is instantiated for both instruction as well as data
memories
Implements a memory array

PIN INTERFACE

PIN NAME

TYPE WIDTH

Clk
resetn
Mem_addr
Mem_rd
Mem_wr
Data_in
Data_out

IN
IN
IN
IN
IN
IN
OUT

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1
1
32
1
1
32
32

DESCRIPTION
Clock signal to the module
Active low reset signal
Read address to the memory
Read signal to the memory
Write signal to the memory
Write data to the memory
Read data from memory

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

3.9. CNTL_PATH
3.9.1.

BLOCK DIAGRAM

Id_ex_alu_src_A

clk

Id_ex_alu_src_B
Id_ex_alu_op

resetn

Ex_mem_data_mem_rd
CONTROLLER
Inst_opcode

Ex_mem_data_mem_wr
Mem_wb_reg_file_wr_en
Mem_wb_reg_dst

Inst_funct

Mem_wb_mem_to_reg

3.9.2.

3.9.3.

FUNCTIONS
Generate the control signals to the various modules in the data path based on the
instruction opcode and the instruction function field
Implements the pipeline registers in the control path for the control signals

PIN INTERFACE

PIN NAME

TYPE WIDTH

Clk
resetn
Inst_opcode
Inst_funct
Id_ex_alu_src_A

IN
IN
IN
IN
OUT

Id_ex_alu_src_B

OUT

Id_ex_alu_op

OUT

1
1
6
6
1
3
2

Ex_mem_data_mem_rd

OUT

Ex_mem_data_mem_wr

OUT

Mem_wb_reg_file_wr_en

OUT

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1
1
1

DESCRIPTION
Clock signal to the module
Active low reset signal
Instruction opcode field
Instruction Function field
Select line for the ALU Input A select Mux
required in instruction execute stage
Select line for the ALU Input B select Mux
required in the instruction execute stage
Select line used to select the type of ALU
operation required. This control signal is required
in the instruction execution stage
Read signal to the data memory. This control
signal is required in the memory access stage
write signal to the data memory. This control
signal is required in the memory access stage
Register file write enable. This control signal is
required in the register writeback stage

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

PIN NAME

TYPE WIDTH

Mem_wb_reg_dst
OUT

OUT

Mem_wb_mem_to_reg

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DESCRIPTION
Select line to the write address select mux. This
control signal is required in the register writeback
stage
Select line to the write data select mux. This
control signal is required in the register writeback
stage.

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

4. RTL CODE
This section gives the RTL Code for each of the modules used in the design of the 32-bit
pipelined MIPS Processor

4.1. INST_FETCH.V
//-------------------------------------------------------------------//VERILOG CODE FOR INSTRUCTION FETCH CYCLE
//MODULE : inst_fetch,memory
//FILE NAME : inst_fetch.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 11 November 2008
//CODE TYPE : Behavioural
//DESCRIPTION : This Module fetches the Instruction from Instruction
//
memory using PC as address and stores the fetched inst
//
in the Instruction register. In addition it also
//
implements the PC Select MUX
//-------------------------------------------------------------------module inst_fetch (
clk
,
resetn
,
jr_inst
,
jr_offset ,
br_cond
,
branch_offset ,
data_out_31_26 ,
data_out_25_21 ,
data_out_20_16 ,
data_out_15_0 ,
if_id_pc_reg ,
inst_opcode ,
inst_funct
);
//Inputs
input
clk
; //Clk signal
input
resetn
; //active low reset signal
input
jr_inst ; //indication of jr instruction
input [31:0] jr_offset ; //jump offset for jr instruction
input
br_cond ; //branch condition indicator
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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


input [31:0] branch_offset; //branch offset for branch instruction
//Outputs
output [5:0] data_out_31_26 ; //Inst opcode
output [4:0] data_out_25_21 ; //rs field from instruction
output [4:0] data_out_20_16 ; //rt field from instruction
output [15:0] data_out_15_0 ; //imm field frm instruction
output [31:0] if_id_pc_reg ; //pc pipeline register
output [5:0] inst_opcode ; //Instruction opcode field - non registered used
//by the controller
output [5:0] inst_funct ; //Function field of instruction - non registered
reg [31:0] if_id_pc_reg ;
//Internal signals
wire [31:0] pc_c
; //contains pc+4
reg [31:0] pc_r
; //pc register-points to the current instruction
reg [31:0] ir_r
; //instruction register
wire [31:0] data_out_c ; //instruction memory read data
reg [31:0] npc
; //pc value after the pc select mux
wire [31:0] jmp_offset_c ; //jmp offset for jump instruction
reg [1:0] pc_source_c ; //Select line for the pc select mux
//generate pc+4
assign pc_c = pc_r + 32'd4;
//generate the jump offset by concatenating left shifted
//version of memory data[25:0] with msb 4 bits of pc
assign jmp_offset_c = {pc_r[31:28],(data_out_c[25:0] << 2)};
//generate pc_source_c
always @(br_cond or jr_inst or data_out_c)
begin
if(br_cond == 1'b1)
pc_source_c <= 2'b00;
else if(jr_inst == 1'b1)
pc_source_c <= 2'b01;
else if(data_out_c[31:26] == `J_TYPE || data_out_c[31:26] == `J_TYPE_JAL)
pc_source_c <= 2'b10;
else
pc_source_c <=2'b11;
end
//Generate the pc_select mux
always @(pc_source_c or pc_c or jmp_offset_c or branch_offset or jr_offset)
begin
case (pc_source_c)
2'd0: npc <= branch_offset ; //select the branch specified offset as new pc
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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


2'd1: npc <= jr_offset ; //select jr specified offset as the new pc
2'd2: npc <= jmp_offset_c ; //select jump specified offset as the new pc
2'd3: npc <= pc_c
; //select npc = pc+4
default : npc <= pc_c;
endcase
end
//update pc with new value
always @(posedge clk)
begin
if(!resetn)
begin
pc_r
<= 32'b0;
if_id_pc_reg <= 32'b0;
end
else
begin
pc_r
<= npc;
if_id_pc_reg <= pc_c; //update the pipeline register
end
end
//Implement the instruction register
always @(posedge clk)
begin
if(!resetn)
begin
ir_r <= 32'b0;
end
else
begin
ir_r <= data_out_c;
end
end
//assign instruction reg data to outputs
assign data_out_31_26 = ir_r[31:26];
assign data_out_25_21 = ir_r[25:21];
assign data_out_20_16 = ir_r[20:16];
assign data_out_15_0 = ir_r[15:0];
//Instantiate the memory
//Word address is give to the instruction memory
//read is always tied to '1' because new inst is fetched every cycle
//write is tied to zero because there are no writes to instruction memory
memory memory_inst (
.clk (clk)
,
.resetn (resetn)
,
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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


.mem_addr({2'b00,pc_r[31:2]}),
.mem_rd (1'b1)
,
.mem_wr (1'b0)
,
.data_in (32'b0)
,
.data_out(data_out_c)
);
//assign inst_opcode. This will be used by the controller
assign inst_opcode = data_out_c[31:26];
assign inst_funct = data_out_c[5:0] ;
endmodule

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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

4.2. INST_DECODE.V
//-------------------------------------------------------------------//VERILOG CODE FOR A INSTRUCTION DECODE MODULE
//MODULE : inst_decode,reg_file
//FILE NAME : inst_decode.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 12 November 2008
//CODE TYPE : Behavioral
//DESCRIPTION : This module decodes the instruction and reads the reg
//
file to fetch the operands. This modules also generates
//
the jr instruction offset required in the instruction
//
fetch module. Sign extended imm are also generated in
//
this module. During the register write back stage this
//
module performs a writeback to the register file
//-------------------------------------------------------------------//Define module
module inst_decode (
clk
resetn

,
,

inst_read_reg_addr1 ,
inst_read_reg_addr2 ,
inst_wr_addr_1 ,
inst_wr_addr_2 ,
mdr_data_out
,
alu_data_out
,
reg_file_wr_en ,
reg_dst
,
mem_to_reg
,
inst_imm_field ,
if_id_pc_reg
,
if_id_inst_31_26 ,
mem_wb_overflow

reg_A
,
reg_B
,
imm_fld_wo_sign_ext ,
sign_ext_imm
,
sign_ext_ls_imm ,
id_ex_pc_reg
,
id_ex_inst_5_0 ,
id_ex_inst_31_26 ,
id_ex_inst_20_16 ,

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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


jr_inst
jr_offset

);
//Inputs
input clk
input resetn

; //Clock signal
; //active low reset signal

input [4:0] inst_read_reg_addr1; //Read address1 to the register file


input [4:0] inst_read_reg_addr2; //Read address2 to the register file
input [4:0] inst_wr_addr_1 ; //Write address 1 to the wr addr mux
input [4:0] inst_wr_addr_2 ; //Write address 2 to the wr addr mux
input [31:0] mdr_data_out
; //data from memory data register
input [31:0] alu_data_out
; //Data from Alu out register
input
reg_file_wr_en ; //Write enable to the register file
input [1:0] reg_dst
; //used to select the destination register address
input
mem_to_reg
; //used to select the write data going to register
input [15:0] inst_imm_field ; //Immediate field of the instruction
input [31:0] if_id_pc_reg
; //pipeline register for pc register
input [5:0] if_id_inst_31_26 ; //pipeline register for instruction opcode
input
mem_wb_overflow ; //pipeline register for overflow indication
//Outputs
output [31:0] reg_A
; //Register A used by ALU
output [31:0] reg_B
; //Register B used by ALU
output [31:0] sign_ext_imm
; //Sign extended immediate number
output [31:0] sign_ext_ls_imm ; //Sign extended immediate number with left shift
output [31:0] imm_fld_wo_sign_ext ; //Immediate number without sign extension
output [31:0] id_ex_pc_reg
output [5:0] id_ex_inst_5_0
output [5:0] id_ex_inst_31_26
output [4:0] id_ex_inst_20_16
output
jr_inst
output [31:0] jr_offset

; //pipeline register for pc


; //pipeine register for instruction function field
; //pipeine register for instruction opcode field
; //pipeline register for the rs field of instruction

; //Indicator of jump instruction


; //Combinational Jump register inst offset

reg [31:0] reg_A;


reg [31:0] reg_B;
reg [31:0] sign_ext_imm;
reg [31:0] sign_ext_ls_imm;
reg [31:0] imm_fld_wo_sign_ext;
reg [31:0] id_ex_pc_reg ;
reg [5:0] id_ex_inst_5_0 ;
reg [5:0] id_ex_inst_31_26;
reg [4:0] id_ex_inst_20_16;
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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


//reg

jr_inst

//Internal signals
reg [4:0] wr_addr_sel_mux_c ;
reg [4:0] wr_addr_sel_mux2_c ;
wire [31:0] wr_data_sel_mux_c ;
reg [31:0] wr_data_sel_mux2_c ;
wire [31:0] sign_ext_imm_c
;
wire [31:0] reg_file_rd_data1_c ;
wire [31:0] reg_file_rd_data2_c ;
wire
jr_inst_c
;
//Select the write address to the register file
//if reg_dst = 1 then wr_addr_sel_mux = inst_wr_addr_2
//else if reg_dst = 0 then wr_addr_sel_mux = inst_wr_addr_1
//else if reg_dst = 2 then wr_addr_sel_mux = 5'd31-for selecting r31 during jal
always @(inst_wr_addr_1 or inst_wr_addr_2 or reg_dst)
begin
case (reg_dst)
2'd0 : wr_addr_sel_mux_c <= inst_wr_addr_1 ;
2'd1 : wr_addr_sel_mux_c <= inst_wr_addr_2 ;
2'd2 : wr_addr_sel_mux_c <= 5'd31
;
default : wr_addr_sel_mux_c <= 0
;
endcase
end
//generate the wr_addr_sel_mux2_c which muxes between the above selected
//wr address and the overflow register write address(i.e. r30)
always @(mem_wb_overflow or wr_addr_sel_mux_c)
begin
if(mem_wb_overflow == 1'b1)
wr_addr_sel_mux2_c <= 5'd30;
else
wr_addr_sel_mux2_c <= wr_addr_sel_mux_c;
end
//Select the write data to the register file
//if mem_to_reg = 1 then wr_data_sel_mux_c = data from memory data reg
//
else wr_data_sel_mux_c = data from alu output reg
assign wr_data_sel_mux_c = mem_to_reg ? alu_data_out : mdr_data_out ;
//generate the wr_data_sel_mux2_c which muxes between the above selected
//wr data and the overflow indication to the register file
always @(mem_wb_overflow or wr_data_sel_mux_c)
begin
if(mem_wb_overflow == 1'b1)
wr_data_sel_mux2_c <= 32'b1;
else
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wr_data_sel_mux2_c <= wr_data_sel_mux_c;
end
//Generate the sign extended immediate number
assign sign_ext_imm_c = inst_imm_field[15:15] ? {16'hFFFF,inst_imm_field} :
{16'h0000,inst_imm_field};
//Instantiate and port map the register file
reg_file reg_file_inst (
.clk
(clk)
,
.resetn (resetn)
,
.reg_rd_addr1(inst_read_reg_addr1) ,
.reg_rd_addr2(inst_read_reg_addr2) ,
.reg_wr_en (reg_file_wr_en) ,
.reg_wr_addr (wr_addr_sel_mux2_c) ,
.reg_wr_data (wr_data_sel_mux2_c) ,
.reg_rd_data1(reg_file_rd_data1_c) ,
.reg_rd_data2(reg_file_rd_data2_c)
);
//Generate clocked outputs
always @(posedge clk)
begin
if(!resetn)
begin
reg_A
<= 32'b0;
reg_B
<= 32'b0;
sign_ext_imm
<= 32'b0;
sign_ext_ls_imm <= 32'b0;
imm_fld_wo_sign_ext <= 32'b0;
id_ex_pc_reg
<= 32'b0;
id_ex_inst_5_0 <= 6'b0 ;
id_ex_inst_20_16 <= 5'b0 ;
end
else
begin
reg_A
<= reg_file_rd_data1_c ;
reg_B
<= reg_file_rd_data2_c ;
sign_ext_imm
<= sign_ext_imm_c
;
sign_ext_ls_imm <= (sign_ext_imm_c << 2) ;
imm_fld_wo_sign_ext <= {16'h0000,inst_imm_field};
id_ex_pc_reg
<= if_id_pc_reg
;
id_ex_inst_5_0 <= inst_imm_field[5:0] ;
id_ex_inst_31_26 <= if_id_inst_31_26
;
id_ex_inst_20_16 <= inst_read_reg_addr2 ;
end
end

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//detect a "jr" type instruction
assign jr_inst_c = (if_id_inst_31_26 == `R_TYPE && inst_imm_field[5:0] == `FUNC_JR) ?1'b1:1'b0;
assign jr_offset = reg_file_rd_data1_c;
assign jr_inst = jr_inst_c;
endmodule

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4.3. REG_FILE.V
//-------------------------------------------------------------------//VERILOG CODE FOR A REGISTER FILE
//MODULE : reg_file
//FILE NAME : reg_file.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 12 November 2008
//CODE TYPE : Behavioral
//DESCRIPTION : This module implements the 32 General Purpose Registers
//
for the 32-bit pipelined MIPS processor. Each Register
//
is 32 Bits wide. This register bank has two read ports
//
and a single write port
//-------------------------------------------------------------------//Define module
module reg_file (
clk
,
resetn
,
reg_rd_addr1 ,
reg_rd_addr2 ,
reg_wr_en ,
reg_wr_addr ,
reg_wr_data ,
reg_rd_data1 ,
reg_rd_data2
);
//Inputs
input clk;
input resetn;
input [4:0] reg_rd_addr1 ; //Register file read address 1
input [4:0] reg_rd_addr2 ; //Register file read address 2
input reg_wr_en
; //Write enable to the register file
input [4:0] reg_wr_addr ; //Register file write address
input [31:0] reg_wr_data ; //Register file write data
//Outputs
output [31:0] reg_rd_data1; //Register file read data
output [31:0] reg_rd_data2; //Register file read data
//Define register array
reg [31:0] register_file[0:31];
//Internal signals
integer i;
//Write Process for Register file
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always @(posedge clk)
begin
if(!resetn)
begin
//Under reset initialize the register file
//to all zeros
for(i=0;i<=31;i=i+1)
begin
register_file[i] <= 32'b0;
end
end
else
begin
//If write is enabled then write the
//reg_wr_data into the register file
if(reg_wr_en == 1'b1)
begin
register_file[reg_wr_addr] <= reg_wr_data;
end
end
end
//Read data from the register file corresponding to
//addresses reg_rd_addr1 and reg_rd_addr2 and assign
//it to the ouput data
assign reg_rd_data1 = register_file[reg_rd_addr1];
assign reg_rd_data2 = register_file[reg_rd_addr2];
endmodule

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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

4.4. INST_EXECUTE.V

//-------------------------------------------------------------------//VERILOG CODE FOR A INSTRUCTION EXECUTE MODULE


//MODULE : inst_execute,alu_controller,alu
//FILE NAME : inst_execute.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 12 November 2008
//CODE TYPE : Behavioral
//DESCRIPTION : This module instantiates the ALU and the ALU Controller
//
It also implements the select Muxes for the ALU Inputs.
//
This module generates the branch instruction indication
//
and also the corresponding branch offset to be used in
//
Instruction fetch module.
//-------------------------------------------------------------------//Define module
module inst_execute (
clk
,
resetn
,
pc_reg
,
reg_A_data
,
reg_B_data
,
sign_ext_imm
,
sign_ext_ls_imm ,
imm_fld_wo_sign_ext ,
inst_reg_5_0
inst_opcode
alu_src_A
alu_src_B
alu_op

,
,
,
,
,

id_ex_inst_20_16 ,
alu_out
,
ex_mem_reg_B_data ,
ex_mem_inst_5_0 ,
ex_mem_inst_31_26 ,
ex_mem_inst_20_16 ,
ex_mem_inst_15_11 ,
ex_mem_overflow ,
br_cond
,
branch_offset
);
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//Inputs
input clk
; //clock signal
input resetn
; //active low reset signal
input [31:0] pc_reg
; //Value from Program Counter Register
input [31:0] reg_A_data
; //Register A data from inst decode
input [31:0] reg_B_data
; //Register B data from inst decode
input [31:0] sign_ext_imm
; //Sign ext immediate number from instruction
input [31:0] sign_ext_ls_imm ; //Sign ext left shifted imm number
input [31:0] imm_fld_wo_sign_ext ; //Non sign extended immediate field
input [5:0] inst_reg_5_0
; //function field from instruction
input [5:0] inst_opcode
; //Opcode field in the instruction
input
alu_src_A
; //select line for src A of ALU
input [2:0] alu_src_B
; //select line for src B of ALU
input [1:0] alu_op
; //Type of ALU Op required from Main controller
input [4:0] id_ex_inst_20_16 ; //Pipeline register for rt field of instruction
//Outputs
output [31:0] alu_out
; //Registered ALU result
output [31:0] ex_mem_reg_B_data ; //pipeline register for reg_B data
output [5:0] ex_mem_inst_5_0 ; //pipeline register for inst funct field
output [5:0] ex_mem_inst_31_26 ; //pipeline register for the inst opcode field
output [4:0] ex_mem_inst_20_16 ; //Pipeline register for rt field of instruction
output [4:0] ex_mem_inst_15_11 ; //pipeline register for rd field of instruction
output
ex_mem_overflow ; //Overflow detected indication
output
br_cond
; //indicator for branch instruction
output [31:0] branch_offset ; //offset for branch instruction
reg
reg
reg
reg
reg
reg
reg

[31:0] alu_out
;
[31:0] ex_mem_reg_B_data ;
[5:0] ex_mem_inst_5_0 ;
[5:0] ex_mem_inst_31_26 ;
[4:0] ex_mem_inst_20_16 ;
[4:0] ex_mem_inst_15_11 ;
ex_mem_overflow ;

wire
br_cond
;
wire [31:0] branch_offset

//Internal Signals
wire [31:0] alu_src_A_mux_c ; //Muxed value for input A of ALU
reg [31:0] alu_src_B_mux_c ; //Muxed value for input B of ALU
wire [3:0] alu_cntl_ip_c ; //Control input for the ALU
wire [31:0] alu_res_c
; //Result from ALU operation
wire
zero_c
; //branch condition for beq
wire
not_equal_c ; //branch condition for bne
wire
ls_then_c
; //branch condition for bltz
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wire
wire
wire
wire

gr_then_c
; //branch condition for bgtz
ls_then_eq_c ; //branch condition for blez
br_cond_c
; //cumulative branch condition
overflow_c ; //Overflow detected indication

reg signed [31:0] signed_pc_reg


; //signed pc_reg used for signed addition
reg signed [31:0] signed_sign_ext_ls_imm; //signed sign_ext_ls_imm for signed addition
reg signed [31:0] branch_offset_c
; //branch offset
//Implement ALU Input A mux
//if alu_src_A = 1 then give reg A data to Alu
//
else give pc reg data to alu
assign alu_src_A_mux_c = alu_src_A ? reg_A_data : pc_reg ;
//Implement ALU Input B mux
//Some inputs to mux are redundant - they were used in non pipelined implementation
always @(alu_src_B or reg_B_data or sign_ext_imm or sign_ext_ls_imm or imm_fld_wo_sign_ext)
begin
case (alu_src_B)
3'd0 : alu_src_B_mux_c <= reg_B_data ; //Select reg B data
3'd1 : alu_src_B_mux_c <= 32'd4
; //Give 4 as input to Alu
3'd2 : alu_src_B_mux_c <= sign_ext_imm ; //Select sign extended immediate
3'd3 : alu_src_B_mux_c <= sign_ext_ls_imm ; //select sign extended left shifted imm
3'd4 : alu_src_B_mux_c <= imm_fld_wo_sign_ext ; //Non sign extended immediate field
default : begin
alu_src_B_mux_c <= 0;
end
endcase
end
//Instantiate the ALU controller
alu_controller alu_controller_inst (
.inst_reg_5_0(inst_reg_5_0),
.alu_op (alu_op) ,
.inst_opcode (inst_opcode) ,
.alu_cntl_ip (alu_cntl_ip_c)
);
//Instantiate the ALU
alu alu_inst (
.a
(alu_src_A_mux_c),
.b
(alu_src_B_mux_c),
.alu_cntl_ip(alu_cntl_ip_c) ,
.alu_res (alu_res_c) ,
.zero
(zero_c)
,
.not_equal (not_equal_c) ,
.ls_then (ls_then_c) ,
.gr_then (gr_then_c) ,
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.ls_then_eq (ls_then_eq_c) ,
.overflow (overflow_c)
);
//Generate the ALU OUT register
always @(posedge clk)
begin
if(!resetn)
begin
alu_out
<= 32'b0 ;
ex_mem_reg_B_data <= 32'b0 ;
ex_mem_inst_5_0 <= 6'b0 ;
ex_mem_inst_31_26 <= 6'b0 ;
ex_mem_inst_20_16 <= 5'b0 ;
ex_mem_inst_15_11 <= 5'b0 ;
ex_mem_overflow <= 1'b0 ;
end
else
begin
alu_out
<= alu_res_c
;
ex_mem_reg_B_data <= reg_B_data
;
ex_mem_inst_5_0 <= inst_reg_5_0
;
ex_mem_inst_31_26 <= inst_opcode
;
ex_mem_inst_20_16 <= id_ex_inst_20_16
;
ex_mem_inst_15_11 <= imm_fld_wo_sign_ext[15:11];
ex_mem_overflow <= overflow_c
;
end
end
//generate cumulative branch condition based on individual conditions
assign br_cond_c = (zero_c
& inst_opcode == `B_TYPE_EQ ) |
(not_equal_c & inst_opcode == `B_TYPE_NEQ) |
(ls_then_c & inst_opcode == `B_TYPE_LTZ) |
(gr_then_c & inst_opcode == `B_TYPE_GTZ) |
(ls_then_eq_c & inst_opcode == `B_TYPE_LEZ);
//assign combinational values to branch indicator and branch offset
assign br_cond
= br_cond_c;
assign branch_offset = branch_offset_c;
//generate signed reg type for pc_reg and signed
//sign_ext_ls_imm to perform signed addition
always @(pc_reg or sign_ext_ls_imm)
begin
signed_pc_reg
<= pc_reg
;
signed_sign_ext_ls_imm <= sign_ext_ls_imm;
end

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//generate the branch offset by adding sign extended word aligned


//immediate to the new pc
always @(signed_pc_reg or signed_sign_ext_ls_imm)
begin
branch_offset_c <= signed_pc_reg + signed_sign_ext_ls_imm;
end
endmodule

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4.5. ALU_CONTROLLER.V
//-------------------------------------------------------------------//VERILOG CODE FOR AN ALU CONTROLLER
//MODULE : alu_controller
//FILE NAME : alu_controller.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 12 November 2008
//CODE TYPE : Behavioral
//DESCRIPTION : This module generates the alu control inputs based on
//
instruction opcode, instruction function bits and the
//
alu operation field provided by the main controller
//-------------------------------------------------------------------//Define the module
module alu_controller (
inst_reg_5_0,
alu_op ,
inst_opcode ,
alu_cntl_ip
);
//Inputs
input [5:0] inst_reg_5_0 ; //Bits 5 to 0 from inst reg
input [1:0] alu_op
; //type of Alu op fm main controller
input [5:0] inst_opcode ; //Opcode field from the instruction
//Outputs
output [3:0] alu_cntl_ip ; //Control lines to the ALU
reg [3:0] alu_cntl_ip ;
//Generate the alu control input lines
//based on funct field and alu_op
always @(alu_op or inst_reg_5_0 or inst_opcode)
begin
case (alu_op)
2'b00 : alu_cntl_ip <= `ALU_ADD; //Perform Add for LW/SW operations
2'b01 : alu_cntl_ip <= `ALU_SUB; //Perform Sub for branch operatios
2'b10 :
begin
//alu ops implemented based on funct field of inst
case (inst_reg_5_0)
`FUNC_SLLV : alu_cntl_ip <= `ALU_SLLV ;
`FUNC_SRLV : alu_cntl_ip <= `ALU_SRLV ;
`FUNC_ADD : alu_cntl_ip <= `ALU_ADD ;
`FUNC_ADDU : alu_cntl_ip <= `ALU_ADDU ;
`FUNC_SUB : alu_cntl_ip <= `ALU_SUB ;
`FUNC_SUBU : alu_cntl_ip <= `ALU_SUBU ;
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`FUNC_AND : alu_cntl_ip <= `ALU_AND ;
`FUNC_OR : alu_cntl_ip <= `ALU_OR ;
`FUNC_XOR : alu_cntl_ip <= `ALU_XOR ;
`FUNC_NOR : alu_cntl_ip <= `ALU_NOR ;
`FUNC_SLT : alu_cntl_ip <= `ALU_SLT ;
`FUNC_SLTU : alu_cntl_ip <= `ALU_SLTU ;
default : alu_cntl_ip <= `ALU_ADD ;
endcase
end
2'b11 :
begin
//Alu operation implemented based on the instruction opcode
//This case is used to implement imm operations
case (inst_opcode)
`I_TYPE_ADDI : alu_cntl_ip <= `ALU_ADD ;
`I_TYPE_ADDIU : alu_cntl_ip <= `ALU_ADDU ;
`I_TYPE_ANDI : alu_cntl_ip <= `ALU_AND ;
`I_TYPE_ORI : alu_cntl_ip <= `ALU_OR ;
`I_TYPE_XORI : alu_cntl_ip <= `ALU_XOR ;
`I_TYPE_SLTI : alu_cntl_ip <= `ALU_SLT ;
`I_TYPE_SLTIU : alu_cntl_ip <= `ALU_SLTU ;
`J_TYPE_JAL : alu_cntl_ip <= `ALU_ADD_ZERO ;
default : alu_cntl_ip <= `ALU_ADD ;
endcase
end
default : alu_cntl_ip <= `ALU_ADD;
endcase
end
endmodule

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4.6. ALU.V
//-------------------------------------------------------------------//VERILOG CODE FOR AN ALU
//MODULE : alu
//FILE NAME : alu.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 12 November 2008
//CODE TYPE : Behavioral
//DESCRIPTION : This module performs the arithmetic, logical and shift
//
operations. In addition it generates the overflow indi
//
for signed add and sub operations. It also generates
//
branch indicators like zero, not_equal, ls_then etc.
//-------------------------------------------------------------------//Define the module
module alu (
a
,
b
,
alu_cntl_ip,
alu_res ,
zero
,
not_equal ,
ls_then ,
gr_then ,
ls_then_eq ,
overflow
);
//Inputs
input [31:0] a
; //Input A to the ALU
input [31:0] b
; //Input B to the ALU
input [3:0] alu_cntl_ip ; //ALU control i/p used to sel operation
//Outputs
output [31:0] alu_res ; //Result of ALU Operation
output
zero ; //branch condition result
output
not_equal ; //set when rs!=rt, used in bne inst
output
ls_then ; //set when rs<0, used in bltz inst
output
gr_then ; //set when rs>0, used in bgtz inst
output
ls_then_eq; //set when rs<=0, used in blez inst
output
overflow ; //overflow detected indication
//Internal Signals
reg signed [31:0] alu_res_c ; //signed alu result
reg signed [31:0] signed_a ; //signed b input
reg signed [31:0] signed_b ; //Signed a input
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reg

overflow_c ; //Overflow detected indication

//assign signed values to signed_a and signed_b


always @(a or b)
begin
signed_a <= a;
signed_b <= b;
end
//Implement the ALU operations
always @(a or b or alu_cntl_ip or signed_a or signed_b)
begin
case (alu_cntl_ip)
`ALU_SLLV : alu_res_c <= b << a
; //Logical Shift Left operation
`ALU_SRLV : alu_res_c <= b >> a
; //logical shift right operation
`ALU_ADD : alu_res_c <= signed_a + signed_b ; //signed addition
`ALU_ADDU : alu_res_c <= a + b
; //unsigned addition
`ALU_SUB : alu_res_c <= signed_a - signed_b ; //Signed subtraction
`ALU_SUBU : alu_res_c <= a - b
; //unsigned subtraction
`ALU_AND : alu_res_c <= a & b
; //Bitwise AND
`ALU_OR : alu_res_c <= a | b
; //Bitwise OR
`ALU_XOR : alu_res_c <= a ^ b
; //Bitwise XOR
`ALU_NOR : alu_res_c <= ~(a | b)
; //Bitwise NOR
`ALU_SLT : begin
//Set if less then
if(signed_a<signed_b)
begin
alu_res_c <= 1;
end
else
begin
alu_res_c <= 0;
end
end
`ALU_SLTU : begin
//Set if less then unsigned
if(a<b)
begin
alu_res_c <= 1;
end
else
begin
alu_res_c <= 0;
end
end
`ALU_ADD_ZERO : alu_res_c <= a
; //Alu result = reg_A + 0, used in JAL
default : alu_res_c <= 0;
endcase
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end
//overflow indication generation
//For addition overflow is set when both a and b are of same sign and the
//result is of the opposite sign
//For subtraction overflow occurs when both a and b are of different signs
//and the result has sign different from that of the first operand(a)
always @(alu_cntl_ip or signed_a or signed_b or alu_res_c)
begin
case (alu_cntl_ip)
`ALU_ADD : begin
if(signed_a >= 0 && signed_b >= 0 && alu_res_c < 0)
begin
overflow_c <= 1'b1;
end
else if(signed_a < 0 && signed_b < 0 && alu_res_c >= 0)
begin
overflow_c <= 1'b1;
end
else
begin
overflow_c <= 1'b0;
end
end
`ALU_SUB : begin
if(signed_a >= 0 && signed_b < 0 && alu_res_c < 0)
begin
overflow_c <= 1'b1;
end
else if(signed_a < 0 && signed_b >= 0 && alu_res_c >= 0)
begin
overflow_c <= 1'b1;
end
else
begin
overflow_c <= 1'b0;
end
end
default : overflow_c <= 1'b0;
endcase
end
//Assign outputs
assign alu_res = alu_res_c;
assign zero
= (alu_res_c == 0) ? 1'b1 : 1'b0 ; //if result of alu op is zero set "zero"
assign not_equal = (alu_res_c != 0) ? 1'b1 : 1'b0 ; //If reg_A != reg_B set not_equal
assign ls_then = (alu_res_c < 0) ? 1'b1 : 1'b0 ; //If reg_A < reg_B set ls_then used for bltz
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assign gr_then = (alu_res_c > 0) ? 1'b1 : 1'b0 ; //If reg_A > reg_B set gr_then used for bgtz
assign ls_then_eq = (alu_res_c <= 0) ? 1'b1 : 1'b0 ; //If reg_A <= reg_B set ls_then_eq used for blez
assign overflow = overflow_c ;
endmodule

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4.7. MEMORY_ACC.V
//-------------------------------------------------------------------//VERILOG CODE FOR MEMORY ACCESS MODULE
//MODULE : memory
//FILE NAME : memory.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 11 November 2008
//CODE TYPE : Behavioural
//DESCRIPTION : This module implements the accesses to the data mem
//
It does a data memory read for load operations and a
//
data memory write for store operations. It also imple
//
ments the memory data register to store the data read
//
from the data memory
//-------------------------------------------------------------------//Define the module
module memory_acc (
clk
,
resetn
,
alu_out
,
mem_rd
,
mem_wr
,
mem_wr_data
,
ex_mem_inst_20_16 ,
ex_mem_inst_15_11 ,
ex_mem_overflow ,
mdr_data_out ,
mem_wb_alu_out_reg,
mem_wb_inst_20_16 ,
mem_wb_inst_15_11 ,
mem_wb_overflow
);
//Inputs
input
clk
; //Clock signal
input
resetn
; //Active low reset signal
input [31:0] alu_out
; //effective Memory address for data memory
input
mem_rd
; //Memory read signal
input
mem_wr
; //Memory write signal
input [31:0] mem_wr_data ; //Memory write data
input [4:0] ex_mem_inst_20_16; //Pipeline register for rt instruction field
input [4:0] ex_mem_inst_15_11; //pipeline register for rd instruction field
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input

ex_mem_overflow ; //Pipeline register for overflow indication

//Outputs
output [31:0] mdr_data_out
; //Memory read data output register
output [31:0] mem_wb_alu_out_reg ; //pipeline register for alu_out register
output [4:0] mem_wb_inst_20_16 ; //Pipeline register for rt instruction field
output [4:0] mem_wb_inst_15_11 ; //pipeline register for rd instruction field
output
mem_wb_overflow ; //pipeline register for overflow indication
reg
reg
reg
reg
reg

[31:0] mdr_data_out_r ;
[31:0] mem_wb_alu_out_reg ;
[4:0] mem_wb_inst_20_16 ;
[4:0] mem_wb_inst_15_11 ;
mem_wb_overflow ;

//Internal signals
wire [31:0] data_out_r

//Instantiate the data memory


memory memory_inst (
.clk (clk)
,
.resetn (resetn) ,
.mem_addr({2'b00,alu_out[31:2]}) ,
.mem_rd (mem_rd) ,
.mem_wr (mem_wr) ,
.data_in (mem_wr_data),
.data_out(data_out_r)
);
//Implement registers
always @(posedge clk)
begin
if(!resetn)
begin
mdr_data_out_r <= 32'b0;
mem_wb_alu_out_reg <= 32'b0;
mem_wb_inst_20_16 <= 5'b0 ;
mem_wb_inst_15_11 <= 5'b0 ;
mem_wb_overflow <= 1'b0 ;
end
else
begin
mdr_data_out_r <= data_out_r
;
mem_wb_alu_out_reg <= alu_out
;
mem_wb_inst_20_16 <= ex_mem_inst_20_16;
mem_wb_inst_15_11 <= ex_mem_inst_15_11;
mem_wb_overflow <= ex_mem_overflow ;
end
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end
//assign memory data reg data to output
assign mdr_data_out = mdr_data_out_r;
endmodule

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4.8. MEMORY.V
//-------------------------------------------------------------------//VERILOG CODE FOR A MEMORY
//MODULE : memory
//FILE NAME : memory.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 11 November 2008
//CODE TYPE : Behavioural
//DESCRIPTION : This module implements a generic memory having one
//
read and one write port.It has a depth of MEM_DEPTH,
//
address width of MEM_ADDR_WIDTH and data width of
//
MEM_DATA_WIDTH
//-------------------------------------------------------------------module memory (
clk ,
resetn ,
mem_addr ,
mem_rd ,
mem_wr ,
data_in ,
data_out
);
//Inputs
input
clk ; //Clock Signal
input
resetn ; //active low reset signal
input [`MEM_ADDR_WIDTH-1:0] mem_addr ; //address to the memory
input
mem_rd ; //memory read signal
input
mem_wr ; //memory write signal
input [`MEM_DATA_WIDTH-1:0] data_in ; //write data to memory
//Outputs
output [`MEM_DATA_WIDTH-1:0] data_out ; //read data
//Memory Array
reg [`MEM_DATA_WIDTH-1:0] mem [0:`MEM_DEPTH-1];
always @(posedge clk)
begin
if(!resetn)
begin
end
else
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begin
//if write is given write the data to the memory
if(mem_wr == 1'b1)
begin
mem[mem_addr] <= data_in;
end
end
end
//read dat is always assigned based on the input rd address
assign data_out = mem[mem_addr];
endmodule

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4.9. DATA_PATH.V
//-------------------------------------------------------------------//VERILOG CODE FOR DATAPATH TOP
//MODULE : inst_fetch,inst_decode,inst_execute,memory_acc
//FILE NAME : data_path.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 12 November 2008
//CODE TYPE : Structural
//DESCRIPTION : This module instantiates all the modules from the data
//
path and performs the port mapping. This module will be
//
instantiated in the mips_top.v
//-------------------------------------------------------------------//Define module
module data_path (
//Clock and Reset Signals
clk,
resetn,
//Control signals to the inst decode module
reg_file_wr_en,
reg_dst
,
mem_to_reg ,
//Control signals to the inst execute module
alu_src_A,
alu_src_B,
alu_op ,
//Control signals to the memory_acc module
data_mem_rd,
data_mem_wr,
inst_opcode ,
inst_funct
);
//Inputs
input
clk
; //Clock signal
input
resetn
; //Active low reset signal
input
reg_file_wr_en ; //Register File write enable signal
input [1:0] reg_dst
; //used to select the destination register address
input
mem_to_reg ; //used to select the write data going to register
input
alu_src_A
; //select line for src A of ALU
input [2:0] alu_src_B
; //select line for src B of ALU
input [1:0] alu_op
; //Type of ALU Op required from Main controller
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input
input

data_mem_rd ; //Data Memory read signal


data_mem_wr ; //Data Memory write signal

//Outputs
output [5:0] inst_opcode ; //Instruction opcode field from instruction
output [5:0] inst_funct ; //Function field of the instruction
//Internal Signals
wire [31:0] alu_out_c
;
wire [31:0] reg_B_c
;
wire [31:0] reg_A_c
;
wire [5:0] data_out_31_26_c ;
wire [4:0] data_out_25_21_c ;
wire [4:0] data_out_20_16_c ;
wire [15:0] data_out_15_0_c ;
wire [31:0] mdr_data_out_c
;
wire [31:0] sign_ext_imm_c
;
wire [31:0] sign_ext_ls_imm_c ;
wire [31:0] imm_fld_wo_sign_ext_c;
wire
jr_inst_c
;
wire [31:0] jr_offset_c
;
wire
br_cond_c
;
wire [31:0] branch_offset_c ;
wire [31:0] if_id_pc_reg_c
;
wire [31:0] id_ex_pc_reg_c
;
wire [5:0] id_ex_inst_5_0_c ;
wire [5:0] id_ex_inst_31_26_c ;
wire [31:0] ex_mem_reg_B_data_c ;
wire [31:0] mem_wb_alu_out_reg_c ;
wire [5:0] ex_mem_inst_5_0_c ;
wire [5:0] ex_mem_inst_31_26_c ;
wire [5:0] inst_opcode_c
;
wire [5:0] inst_funct_c
;
wire [4:0] id_ex_inst_20_16_c ;
wire [4:0] ex_mem_inst_20_16_c ;
wire [4:0] mem_wb_inst_20_16_c ;
wire [4:0] ex_mem_inst_15_11_c ;
wire [4:0] mem_wb_inst_15_11_c ;
wire
ex_mem_overflow_c ;
wire
mem_wb_overflow_c ;
//Instantiate the Instruction Fetch Module
inst_fetch inst_fetch_inst(
.clk
(clk)
,
.resetn
(resetn)
,
.jr_inst
(jr_inst_c)
,
.jr_offset (jr_offset_c) ,
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.br_cond
(br_cond_c)
,
.branch_offset (branch_offset_c) ,
.data_out_31_26(data_out_31_26_c) ,
.data_out_25_21(data_out_25_21_c) ,
.data_out_20_16(data_out_20_16_c) ,
.data_out_15_0 (data_out_15_0_c) ,
.if_id_pc_reg (if_id_pc_reg_c) ,
.inst_opcode (inst_opcode_c) ,
.inst_funct (inst_funct_c)
);
//Instantiate the Instruction Decode Module
inst_decode inst_decode_inst (
.clk
(clk)
,
.resetn
(resetn)
,
.inst_read_reg_addr1(data_out_25_21_c) ,
.inst_read_reg_addr2(data_out_20_16_c) ,
.inst_wr_addr_1 (mem_wb_inst_20_16_c) ,
.inst_wr_addr_2 (mem_wb_inst_15_11_c) ,
.inst_imm_field (data_out_15_0_c) ,
.reg_file_wr_en (reg_file_wr_en)
,
.mdr_data_out
(mdr_data_out_c)
,
.alu_data_out
(mem_wb_alu_out_reg_c) ,
.reg_dst
(reg_dst)
,
.mem_to_reg
(mem_to_reg)
,
.if_id_pc_reg
(if_id_pc_reg_c)
,
.if_id_inst_31_26 (data_out_31_26_c) ,
.mem_wb_overflow (mem_wb_overflow_c) ,
.reg_A
(reg_A_c)
,
.reg_B
(reg_B_c)
,
.sign_ext_imm
(sign_ext_imm_c)
,
.sign_ext_ls_imm (sign_ext_ls_imm_c) ,
.imm_fld_wo_sign_ext(imm_fld_wo_sign_ext_c),
.id_ex_pc_reg
(id_ex_pc_reg_c)
,
.id_ex_inst_5_0 (id_ex_inst_5_0_c) ,
.id_ex_inst_31_26 (id_ex_inst_31_26_c) ,
.id_ex_inst_20_16 (id_ex_inst_20_16_c) ,
.jr_inst
(jr_inst_c)
,
.jr_offset
(jr_offset_c)
);
//Instantiate the Intruction Execute Module
inst_execute inst_execute_inst (
.clk
(clk)
,
.resetn
(resetn)
,
.pc_reg
(id_ex_pc_reg_c)
.reg_A_data
(reg_A_c)
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,
,

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


.reg_B_data
(reg_B_c)
,
.sign_ext_imm
(sign_ext_imm_c)
,
.sign_ext_ls_imm (sign_ext_ls_imm_c) ,
.imm_fld_wo_sign_ext(imm_fld_wo_sign_ext_c),
.inst_reg_5_0
(id_ex_inst_5_0_c) ,
.inst_opcode
(id_ex_inst_31_26_c) ,
.alu_src_A
(alu_src_A)
,
.alu_src_B
(alu_src_B)
,
.alu_op
(alu_op)
,
.id_ex_inst_20_16 (id_ex_inst_20_16_c) ,
.alu_out
(alu_out_c)
,
.ex_mem_reg_B_data (ex_mem_reg_B_data_c) ,
.ex_mem_inst_5_0 (ex_mem_inst_5_0_c) ,
.ex_mem_inst_31_26 (ex_mem_inst_31_26_c) ,
.ex_mem_inst_20_16 (ex_mem_inst_20_16_c) ,
.ex_mem_inst_15_11 (ex_mem_inst_15_11_c) ,
.ex_mem_overflow (ex_mem_overflow_c) ,
.br_cond
(br_cond_c)
,
.branch_offset (branch_offset_c)
);
//Instantiate the memory_acc module
memory_acc memory_acc_inst (
.clk
(clk)
,
.resetn
(resetn)
,
.alu_out
(alu_out_c)
,
.ex_mem_inst_20_16 (ex_mem_inst_20_16_c) ,
.ex_mem_inst_15_11 (ex_mem_inst_15_11_c) ,
.ex_mem_overflow (ex_mem_overflow_c) ,
.mem_rd
(data_mem_rd)
,
.mem_wr
(data_mem_wr)
,
.mem_wr_data
(ex_mem_reg_B_data_c) ,
.mdr_data_out (mdr_data_out_c) ,
.mem_wb_alu_out_reg(mem_wb_alu_out_reg_c),
.mem_wb_inst_20_16 (mem_wb_inst_20_16_c) ,
.mem_wb_inst_15_11 (mem_wb_inst_15_11_c) ,
.mem_wb_overflow (mem_wb_overflow_c)
);

//assign outputs
assign inst_opcode = inst_opcode_c;
assign inst_funct = inst_funct_c;//ex_mem_inst_5_0_c;
endmodule

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4.10. CNTL_PATH.V
//-------------------------------------------------------------------//VERILOG CODE FOR CONTROL PATH
//MODULE : cntl_path
//FILE NAME : cntl_path.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 13 November 2008
//CODE TYPE : behavioral
//DESCRIPTION : This module generates the control signals required by
//
various modules in the data path based on the inst opc
//
and inst function bits
//-------------------------------------------------------------------//Define module
module cntl_path (
//Clock and Reset Signals
clk,
resetn,
//Control signals to the inst execute module
id_ex_alu_src_A ,
id_ex_alu_src_B ,
id_ex_alu_op
,
//Control signals to the memory_acc module
ex_mem_data_mem_rd ,
ex_mem_data_mem_wr ,
//control signals to the write back module
mem_wb_reg_file_wr_en,
mem_wb_reg_dst
,
mem_wb_mem_to_reg ,
//Outputs of data path
inst_opcode ,
inst_funct
);
//Inputs
input
clk
; //Clock signal
input
resetn ; //Active low reset signal
input [5:0] inst_opcode ; //Instruction opcode field from instruction
input [5:0] inst_funct ; //Function field in an R-Type instruction
//Outputs
output
id_ex_alu_src_A
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; //select line for src A of ALU

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output [2:0] id_ex_alu_src_B
; //select line for src B of ALU
output [1:0] id_ex_alu_op
; //Type of ALU Op required from Main controller
output
ex_mem_data_mem_rd ; //Read to the Data memory
output
ex_mem_data_mem_wr ; //write to the data memory
output
mem_wb_reg_file_wr_en ; //Register File write enable signal
output [1:0] mem_wb_reg_dst
; //used to select the destination register address
output
mem_wb_mem_to_reg ; //used to select the write data going to register
reg
id_ex_alu_src_A
;
reg [2:0] id_ex_alu_src_B
;
reg [1:0] id_ex_alu_op
;
reg
ex_mem_data_mem_rd
reg
ex_mem_data_mem_wr
reg
mem_wb_reg_file_wr_en
reg [1:0] mem_wb_reg_dst
;
reg
mem_wb_mem_to_reg

;
;
;
;

//Internal Signals
reg
if_id_alu_src_A_c ;
reg [2:0] if_id_alu_src_B_c ;
reg [1:0] if_id_alu_op_c
;
reg
if_id_data_mem_rd_c ;
reg
if_id_data_mem_wr_c ;
reg
if_id_reg_file_wr_en_c ;
reg [1:0] if_id_reg_dst_c
;
reg
if_id_mem_to_reg_c ;
reg [13:0] cntl_signals_bus

//Pipeline registers for control


//signals are defined below these signals
//are not given to the output. Only the
//signals required by the individual
//modules in the data path are provided at
//the output
reg
if_id_alu_src_A_r ;
reg [2:0] if_id_alu_src_B_r ;
reg [1:0] if_id_alu_op_r
;
reg
if_id_data_mem_rd_r ;
reg
if_id_data_mem_wr_r ;
reg
if_id_reg_file_wr_en_r ;
reg [1:0] if_id_reg_dst_r
;
reg
if_id_mem_to_reg_r ;
reg
id_ex_data_mem_rd_r ;
reg
id_ex_data_mem_wr_r ;
reg
id_ex_reg_file_wr_en_r ;
reg [1:0] id_ex_reg_dst
;
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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


reg

id_ex_mem_to_reg_r

reg
ex_mem_reg_file_wr_en_r ;
reg [1:0] ex_mem_reg_dst_r
;
reg
ex_mem_mem_to_reg_r ;
//Generate the control signals based on the instruction opcode
always @(inst_opcode or inst_funct)
begin
case (inst_opcode)
`R_TYPE
: begin
if(inst_funct == `FUNC_JR)
begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b10 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
else if(inst_funct == `NOP)
begin
if_id_alu_src_A_c <= 1'b0 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b00 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
else
begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b10 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b01 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
end
`L_TYPE

55 | P a g e

: begin
if_id_alu_src_A_c

<= 1'b1 ;

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


if_id_alu_src_B_c <= 3'b010 ;
if_id_alu_op_c
<= 2'b00 ;
if_id_data_mem_rd_c <= 1'b1 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
`S_TYPE

: begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b010 ;
if_id_alu_op_c
<= 2'b00 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b1 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end

`J_TYPE

: begin
if_id_alu_src_A_c <= 1'b0 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b00 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end

`J_TYPE_JAL : begin
if_id_alu_src_A_c <= 1'b0 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b10 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`B_TYPE_EQ : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b01 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
`B_TYPE_NEQ : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b01 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
`B_TYPE_LTZ : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b01 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
`B_TYPE_GTZ : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b01 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
`B_TYPE_LEZ : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b01 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

`I_TYPE_ADDI : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b010 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`I_TYPE_SLTI : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b010 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`I_TYPE_ADDIU : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b010 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`I_TYPE_ANDI : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b100 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`I_TYPE_ORI : begin
if_id_alu_src_A_c
if_id_alu_src_B_c
58 | P a g e

<= 1'b1 ;
<= 3'b100 ;

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`I_TYPE_XORI : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b100 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`I_TYPE_SLTIU : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b100 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
default

: begin
if_id_alu_src_A_c <= 1'b0 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b00 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end

endcase
end

//generate the registers for the control signals


always @(posedge clk)
begin
59 | P a g e

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


if(!resetn)
begin
if_id_alu_src_A_r
<= 0 ;
if_id_alu_src_B_r
<= 0 ;
if_id_alu_op_r
<= 0 ;
if_id_data_mem_rd_r <= 0 ;
if_id_data_mem_wr_r <= 0 ;
if_id_reg_file_wr_en_r <= 0 ;
if_id_reg_dst_r
<= 0 ;
if_id_mem_to_reg_r <= 0 ;
id_ex_alu_src_A
<= 0 ;
id_ex_alu_src_B
<= 0 ;
id_ex_alu_op
<= 0 ;
id_ex_data_mem_rd_r <= 0 ;
id_ex_data_mem_wr_r <= 0 ;
id_ex_reg_file_wr_en_r <= 0 ;
id_ex_reg_dst
<= 0 ;
id_ex_mem_to_reg_r <= 0 ;
ex_mem_data_mem_rd <= 0 ;
ex_mem_data_mem_wr <= 0 ;
ex_mem_reg_file_wr_en_r <= 0 ;
ex_mem_reg_dst_r
<= 0 ;
ex_mem_mem_to_reg_r <= 0 ;
mem_wb_reg_file_wr_en <= 0 ;
mem_wb_reg_dst
<= 0 ;
mem_wb_mem_to_reg
<= 0 ;
end
else
begin
if_id_alu_src_A_r
<= if_id_alu_src_A_c ;
if_id_alu_src_B_r
<= if_id_alu_src_B_c ;
if_id_alu_op_r
<= if_id_alu_op_c
;
if_id_data_mem_rd_r <= if_id_data_mem_rd_c ;
if_id_data_mem_wr_r <= if_id_data_mem_wr_c ;
if_id_reg_file_wr_en_r <= if_id_reg_file_wr_en_c ;
if_id_reg_dst_r
<= if_id_reg_dst_c
;
if_id_mem_to_reg_r <= if_id_mem_to_reg_c ;
id_ex_alu_src_A
<= if_id_alu_src_A_r ;
id_ex_alu_src_B
<= if_id_alu_src_B_r ;
id_ex_alu_op
<= if_id_alu_op_r
;
id_ex_data_mem_rd_r <= if_id_data_mem_rd_r ;
id_ex_data_mem_wr_r <= if_id_data_mem_wr_r ;
id_ex_reg_file_wr_en_r <= if_id_reg_file_wr_en_r ;
id_ex_reg_dst
<= if_id_reg_dst_r
;
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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


id_ex_mem_to_reg_r

<= if_id_mem_to_reg_r

ex_mem_data_mem_rd <= id_ex_data_mem_rd_r ;


ex_mem_data_mem_wr <= id_ex_data_mem_wr_r ;
ex_mem_reg_file_wr_en_r <= id_ex_reg_file_wr_en_r ;
ex_mem_reg_dst_r
<= id_ex_reg_dst
;
ex_mem_mem_to_reg_r <= id_ex_mem_to_reg_r ;
mem_wb_reg_file_wr_en <= ex_mem_reg_file_wr_en_r ;
mem_wb_reg_dst
<= ex_mem_reg_dst_r
;
mem_wb_mem_to_reg
<= ex_mem_mem_to_reg_r ;
end
end
endmodule

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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

4.11. CONSTANTS.V
//-------------------------------------------------------------------//VERILOG CODE FOR CONTROL PATH
//MODULE : //FILE NAME : constants.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 13 November 2008
//CODE TYPE : //DESCRIPTION : This module defines all the constants used in the RTL
//-------------------------------------------------------------------//Constants
`define MEM_ADDR_WIDTH 32
`define MEM_DATA_WIDTH 32
`define MEM_DEPTH 64
//Instruction Function encoding
`define FUNC_SLLV 6'h04
`define FUNC_SRLV 6'h06
`define FUNC_ADD 6'h20
`define FUNC_ADDU 6'h21
`define FUNC_SUB 6'h22
`define FUNC_SUBU 6'h23
`define FUNC_AND 6'h24
`define FUNC_OR 6'h25
`define FUNC_XOR 6'h26
`define FUNC_NOR 6'h27
`define FUNC_SLT 6'h2A
`define FUNC_SLTU 6'h2B
`define FUNC_JR 6'h08
`define NOP
6'h00
//Alu control line constants
`define ALU_SLLV 4'h0
`define ALU_SRLV 4'h1
`define ALU_ADD 4'h2
`define ALU_ADDU 4'h3
`define ALU_SUB 4'h4
`define ALU_SUBU 4'h5
`define ALU_AND 4'h6
`define ALU_OR 4'h7
`define ALU_XOR 4'h8
`define ALU_NOR 4'h9
`define ALU_SLT 4'hA
`define ALU_SLTU 4'hB
`define ALU_ADD_ZERO 4'hC
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//Instruction Type Opcode Constants


`define R_TYPE
6'h00
`define L_TYPE
6'h23
`define S_TYPE
6'h2B
`define J_TYPE
6'h02
`define J_TYPE_JAL 6'h03
`define B_TYPE_EQ 6'h04
`define B_TYPE_NEQ 6'h05
`define B_TYPE_LTZ 6'h01
`define B_TYPE_GTZ 6'h07
`define B_TYPE_LEZ 6'h06
`define I_TYPE_ADDI 6'h08
`define I_TYPE_ADDIU 6'h09
`define I_TYPE_ANDI 6'h0C
`define I_TYPE_ORI 6'h0D
`define I_TYPE_XORI 6'h0E
`define I_TYPE_SLTI 6'h0A
`define I_TYPE_SLTIU 6'h0B

63 | P a g e

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

4.12. MIPS_TOP.V
//-------------------------------------------------------------------//VERILOG CODE FOR MIPS TOP
//MODULE : data_path,cntl_path
//FILE NAME : mips_top.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 13 November 2008
//CODE TYPE : Structural
//DESCRIPTION : This module instantiates the data_path and the cntl_path
//
and performs the port mapping between then. This is the
//
top most module in the hierarchy
//-------------------------------------------------------------------//define the module
module mips_top (
clk,
resetn
);
//Inputs
input clk;
input resetn;
//Internal Signals
wire [1:0] pc_source_c
;
wire
mem_wb_reg_file_wr_en_c ;
wire [1:0] mem_wb_reg_dst_c
;
wire
mem_wb_mem_to_reg_c ;
wire
id_ex_alu_src_A_c
;
wire [2:0] id_ex_alu_src_B_c
;
wire [1:0] id_ex_alu_op_c
;
wire
ex_mem_data_mem_rd_c ;
wire
ex_mem_data_mem_wr_c ;
wire [5:0] inst_opcode_c
;
wire [5:0] inst_funct_c
;
wire
wire

pc_wr_cond_c
br_cond_true_c

;
;

//Instantiate the Data Path


data_path data_path_inst (
//Clock and Reset Signals
.clk(clk),
.resetn(resetn),
//Control signals to the inst decode module
64 | P a g e

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


.reg_file_wr_en(mem_wb_reg_file_wr_en_c),
.reg_dst(mem_wb_reg_dst_c)
,
.mem_to_reg(mem_wb_mem_to_reg_c) ,
//Control signals to the inst execute module
.alu_src_A(id_ex_alu_src_A_c),
.alu_src_B(id_ex_alu_src_B_c),
.alu_op(id_ex_alu_op_c) ,
//Control signals to the pcsel_mux
.data_mem_rd(ex_mem_data_mem_rd_c),
.data_mem_wr(ex_mem_data_mem_wr_c),
//Outputs of data path
.inst_opcode(inst_opcode_c),
.inst_funct(inst_funct_c)
);
//Instantiate the Control Path
cntl_path cntl_path_inst (
//Clock and Reset Signals
.clk(clk),
.resetn(resetn),
//Control signals to the inst execute module
.id_ex_alu_src_A(id_ex_alu_src_A_c) ,
.id_ex_alu_src_B(id_ex_alu_src_B_c) ,
.id_ex_alu_op(id_ex_alu_op_c)
,
//Control signals to the memory_acc module
.ex_mem_data_mem_rd(ex_mem_data_mem_rd_c) ,
.ex_mem_data_mem_wr(ex_mem_data_mem_wr_c) ,
//control signals to the write back module
.mem_wb_reg_file_wr_en(mem_wb_reg_file_wr_en_c),
.mem_wb_reg_dst(mem_wb_reg_dst_c)
,
.mem_wb_mem_to_reg(mem_wb_mem_to_reg_c) ,
//Outputs of data path
.inst_opcode(inst_opcode_c) ,
.inst_funct(inst_funct_c)
);
Endmodule

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ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

5. TEST BENCH CODE


This section gives the Test Bench code for the 32-Bit Pipelined MIPS processor:
//-------------------------------------------------------------------//VERILOG CODE FOR MIPS TOP TEST BENCH
//MODULE : mips_top_tb,mips_top
//FILE NAME : mips_top_tb.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 13 November 2008
//CODE TYPE : TestBench
//DESCRIPTION : This module is the test bench for the mips RTL. This
//
module instantiates the RTL, generates clk and resetn
//
signals, Load and Dumps memories and monitors the outputs
//-------------------------------------------------------------------//define module
module mips_top_tb ();
//Signals
reg clk;
reg resetn;
//Instantiate the RTL
mips_top mips_top_inst (
.clk(clk),
.resetn(resetn)
);
//Clock Generation
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end //end of initial
//Reset Generation
initial
begin
#0 resetn = 1'b0;
#20 resetn = 1'b1;
end //end of initial
//Load/Dump the Instruction/Data Memories and Register File
initial
begin
//Load Instruction/Data Memories and Register File after Reset
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#21
$readmemh("Instruction_Mem_Load.dat",mips_top_tb.mips_top_inst.data_path_inst.inst_fetch_inst.m
emory_inst.mem);
$readmemh("Data_Mem_Load.dat"
,mips_top_tb.mips_top_inst.data_path_inst.memory_acc_inst.memory_inst.mem);
$readmemh("Register_File_Load.dat"
,mips_top_tb.mips_top_inst.data_path_inst.inst_decode_inst.reg_file_inst.register_file);
//Dump Instruction/Data Memories and Register file after execution
//of hex code is complete
#500
$writememh("Instruction_Mem_Dump.txt",mips_top_tb.mips_top_inst.data_path_inst.inst_fetch_inst.
memory_inst.mem);
$writememh("Data_Mem_Dump.txt"
,mips_top_tb.mips_top_inst.data_path_inst.memory_acc_inst.memory_inst.mem);
$writememh("Register_File_Dump.txt"
,mips_top_tb.mips_top_inst.data_path_inst.inst_decode_inst.reg_file_inst.register_file);
end//end of initial
//Display Statements
initial
begin
$monitor($time,"
NEW
INST
FETCHED
OPCODE
%h",mips_top_tb.mips_top_inst.data_path_inst.inst_fetch_inst.data_out_31_26," FUNCT
%h",mips_top_tb.mips_top_inst.data_path_inst.inst_fetch_inst.data_out_15_0[5:0]);
end
always @(posedge mips_top_tb.mips_top_inst.resetn)
begin
if(mips_top_tb.mips_top_inst.resetn == 1'b1)
$display($time," SYSTEM OUT OF RESET");
end
endmodule //End of Test bench

67 | P a g e

BITS

=
=

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

6. MAIN CODE
This section gives the original contents in the instruction memory as present in the
Instruction_Mem_Load.dat file. These contents correspond to the assembly language Test
Code provided as a part of the project. Please note that the instruction memory is 64 Words
Deep.
ASSEMBLY CODE
addiu r1 ,r0 ,#0x0004
slt r4 ,r2 ,r3
sllv r6 ,r7 ,r5
sub r9 ,r8 ,r10
xor r13,r11,r12
beq r14,r15,#0x0004 (LOOP1)
nop
nop
addu r18,r16,r17
sltu r21,r19,r20
LOOP1:addiu r23,r22,#0xFFFF
jr
r25
Nop
addi r2 ,r2 ,#0x0004
xori r27,r26,#0x006C
bltz r8 , #0x0003 (LOOP2)
nop
nop
addi r6 ,r5 ,#0xFF21
LOOP2:addi r4 ,r3 ,#0x007F
lw r7 ,r0 ,#0x0004
jal
#0x0017 (LOOP3)
sub r15,r13,r14
LOOP3:bne r11,r12,#0x0006 (LOOP4)
Nop
Nop
sw r16,r28,#0x0007
blez r0 , #0x0003 (LOOP5)
Nop
nop
LOOP4:sltu r19,r17,r18
LOOP5:slti r21,r20,#0x0008
j
#0x0022 (LOOP6)
sllv r23,r25,r24
LOOP6:sltiu r25,r26,#0x0016
bgtz r27, #0x0004 (LOOP7)
nop
nop
68 | P a g e

HEX CODE
24010004
0043202a
00a73004
010a4822
016c6826
11cf0004
00000000
00000000
02119021
0274a82b
26d7ffff
03200008
00000000
20420004
3b5b006c
05000003
00000000
00000000
20a6ff21
2064007f
8c070004
0c000017
01ae7822
156c0006
00000000
00000000
af900007
18000003
00000000
00000000
0232982b
2a950008
08000022
0319b804
2f590016
1f600004
00000000
00000000

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR


xori r2 ,r1 ,#0x0023
sub r6 ,r4 ,r5
LOOP7:xor r9 ,r7 ,r8

38220023
00853022
00e84826

Since the implementation is with pipelining NOP instructions have to be inserted after every
Jump Register and Branch instruction in order to avoid control hazards. Branch instructions get
resolved by the end of execution stage. Therefore two NOP instructions are required after
every branch instruction. Jump Register instruction gets resolved by the end of Instruction
Decode stage when the Register File contents have been read. Therefore one NOP is
required after JR instruction. Normal Jump (J and JAL) Instructions however do not require any
following NOP instructions because the jump offset gets calculated by the end of Instruction
Fetch stage itself. Dedicated hardware has been put in the Instruction fetch stage to calculate
the Jump offset.

69 | P a g e

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

7. FINAL REGISTER FILE CONTENTS


This section gives the contents of the register file after the hexadecimal code mentioned in
section 6 has been executed
REGISTER NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

70 | P a g e

CONTENTS
00000000
00000004
00000027
fffffffe
0000007d
00000004
00000079
04050607
0ffffe14
0bfaf813
ffffffec
ffff1111
ffff1111
00000000
0ff00ff0
0ff00ff0
0facfe67
00089076
1a2b3c4d
00000018
ffffeefe
00000001
fe243567
fe243566
00080022
00000000
ffffff6c
ffffff00
00000001
00ef11ff
00000000
00000058

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

8. FINAL DATA MEMORY CONTENTS


This section gives the final contents of the data memory after the hexadecimal code mentioned
in section 6 is executed.
DATA MEMORY
LOCATION
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
71 | P a g e

DATA MEMORY
CONTENTS
xxxxxxxx
04050607
0facfe67
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx

ECEN651 PROJECT : 32-BIT PIPELINED MIPS PROCESSOR

9. CONCLUSION
 32-Bit MIPS CPU was designed and implemented using the standard 5-Stage pipeline
 The Given assembly code was executed using the above implementation and the results
were compared to the execution on a non pipelined machine
 No of Cycles required to implement the given Assembly code on a non pipelined 32-Bit
MIPS CPU = 108 Cycles
 No of Cycles required to implement the same Assembly code on a standard 5-Stage
pipelined 32-Bit MIPS CPU = 39 Cycles
 5-Stage Pipelined implementation of the 32-Bit MIPS CPU gives a considerable
improvement in terms of the number of cycles required to execute a set of instructions
as compared to the non pipelined MIPS multicycle CPU executing the same set of
instructions. For the given assembly code an improvement of 69 clock cycles is achieved
by pipelining the CPU
 In the pipelined implementation instructions get executed almost at the rate of one
instruction per cycle, except for the first one. The First instruction takes more cycles
because of the pipeline fill up time.
 In the current implementation of the 32-Bit Pipelined MIPS CPU, NOP instructions had
to be inserted after every branch and jump register instructions in order to avoid control
hazards.

10.

FUTURE IMPROVEMENTS

 Static Branch prediction schemes like flushing, Predict Branch taken, Predict Branch not
taken, Branch Delay slots can be implemented to avoid control hazards
 Dynamic branch prediction schemes can also be implemented to avoid control hazards
 Early branch prediction scheme can be implemented to reduce the penalty for branch
instructions.
 Forwarding can be implemented to avoid data hazards
 Floating point operations can be implemented. It may be a little tough but we can
definitely give it a try
 More instructions can be added to the instruction set
 Automation can be done to generate the hexadecimal code by directly parsing the
assembly language instructions

11.

WAVEFORMS AND SCHEMATICS

The waveforms and synthesized gate level schematic are attached along with this report.

72 | P a g e