DIFFERENT TYPES OF MODELING & TEST BENCH:

DIFFERENT TYPES OF MODELING & TEST BENCH

MODELING IN VHDL:
MODELING IN VHDL In VHDL, the term Modeling refers to the type of description
styles i.e. code that can be written on the basis of logical structure, functionality, behavior of
the design or it can be a combination of these three styles. Hence on the basis of this there are
different type of modeling in VHDL.

DATAFLOW MODELING:
DATAFLOW MODELING A dataflow modeling specifies the functionality of the entity
without explicitly specifying its structure. This functionality shows the flow of information
through the entity,which is expressed using concurrent signal assignment statements. An
architecture body can contain any number of concurrent signal assignment statements.
Conditional statement can also be used in dataflow modeling. e.g. WHEN conditional
statement. Dataflow modeling is used when the user knows the exact expressions for the
desired outputs. Statements are declared in the architecture after the keyword BEGIN. :

Slide 5:
Library IEEE; use IEEE.STD_LOGIC_1164. all ; entity halfadder is port ( A,B :in bit ;S,C
:out bit ); end halfadder ; architecture ha_ar of ha_en is begin S <= A xor B; C <= A and B ;
End architecture ha_ar ; Dataflow Code for 4:1 multiplexer using conditional statement
WHEN: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;
ENTITY mux4to1 IS port (I: in std_logic_vector(0 to 3); s:in std_logic)vector(0 to 1);y:out
std_logic); END ENTITY mux4to1; ARCHITECTURE mux4to1 OF mux4to1 IS BEGIN
Y<= I(0) when s=00 else Y<= I(1) when s=01 else Y<= I(2) when s=10 else Y<= I(3)
when s=11 ; END ARCHITECTURE mux4to1; Dataflow Code for half adder without
using conditional statement:

ADVANTAGES OF DATAFLOW MODELING:

ADVANTAGES OF DATAFLOW MODELING Does not need truth table or behavioral
information. Does not need any structural information. Code become compressed for simple
design. DISADVANTGES OF DATAFLOW MODELING Code become very lengthy for
complex design. It will be difficult to write the dataflow code as the number of input and
output increases. Sequential statements can not be used in data flow modeling .

STRUCTURAL MODELING:

STRUCTURAL MODELING In structural style of modeling, the entity is described as a set

of interconnected components. The component instantiation statement is the primary
mechanism used for describing such a model of an entity. Implicit definition of I/O
relationship is done through particular structure. There is no need of sequential or conditional
statements in this type of modeling. A list of components and there connections in any
language is used in this type of modeling which is also sometimes called netlist. The behavior
of the entity is not explicitly apparent from its model

In structural modeling architecture body is composed of two parts : :

In structural modeling architecture body is composed of two parts : 1. Component declaration
Component declaration is done after the keyword architecture and before the keyword begin.
A component declaration declares the name and the interface of a component. The interface
specifies the mode and the type of ports. e.g. of a two input nor gate as a component
declaration: component nor_gate port (a,b: in bit; c: out bit); end component; Signals: signals
are the interconnecting wires b/w two components that cannot be declared in entity as input
port or output port. 2. Component instantiation A component instantiation statement defines a
subcomponent of the entity in which it appears . It associates the signals in the entity with the
port of that subcomponent. A format of a component instantiation statement is: Componentlabel: component-name[port map(association-list)];

Slide 9:
library IEEE ; use IEEE . STD_LOGIC_1164 . all ; entity fa_en is port ( A , B , Cin : in bit ;
SUM , CARRY : out bit ); end fa_en ; architecture fa_ar of fa_en is component ha_en port ( A
, B : in bit ; S , C : out bit ); end component ; Component or2 Port( a,b:in bit: y: out bit); End
component; signal C1 , C2 , S1 :bit ; begin HA1 : ha_en port map ( A , B , S1 , C1 ); HA2 :
ha_en port map ( S1 , Cin , SUM , C2 ); o1:or2 port map (c1,c2,carry); end fa_ar ; VHDL
code of full adder using two half adder and an OR gate using structural modeling:

ADVANTAGES OF STRUCTURAL MODELING:

ADVANTAGES OF STRUCTURAL MODELING Does not need truth table or behavioral
information. Code become compressed for simple design. No need of any logical equation.
No need of sequential or conditional statements. DISADVANTGES OF STRUCTURAL
MODELING It is difficult to write structural code for complex design. It is more time
consuming as compare to other two types of modelings. Complete structure should be known
to the user.

BEHAVIORAL MODELING:
The behavioral modeling specifies the behavior of an entity as a set of statements that are
executed sequentially in the specified order. This set of sequential statements , which are
specified inside a process statement , do not explicitly specify the structure of the entity but
merely its functionality. Behavioral code cannot be written without a process statement. A

process statement is a concurrent statement that can appear within an architecture body.
Architecture body can have any number of processes . A process statement also has
declarative part (before the keyword begin) and a statement part (between the keywords
begin and end process ). The statements appearing within the process statement are sequential
statements and executed sequentially. A variable is declared within the process statement
unlike the signal which is declared outside. A variable is different from a signal in that it is
always assigned a value instantaneously, and the assignment operator used is the:=
compound symbol; contrast this with a signal that is assigned a value always after a certain
delay. BEHAVIORAL MODELING

PROCESS STATEMENT:
PROCESS STATEMENT A process statement contains sequential statements that describe
the functionality of a portion of an entity in sequential terms. Process statement is declared
after a keyword architecture and before the keyword begin. All types of sequential statements
can be used within the process statement. e.g. if-statement case-statement loop-statement etc.
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY
mux4to1 IS port (I: in std_logic_vector(0 to 3); s:in std_logic)vector(0 to 1);y:out std_logic);
END ENTITY mux4to1; ARCHITECTURE beh OF mux4to1 IS BEGIN Process ( s,I ) begin
z<=((not s0)and(not s1)and I(0))or((not s0)and s1 and I(1))or(s0 and(not s1 )and I(2) )or (s0
and s1 and I(3)); END ARCHITECTURE beh ; Behavioral code for 4:1 multiplexer without
any sequential statements

Behavioral code for 4:2 priority encoder using if statement:

Behavioral code for 4:2 priority encoder using if statement LIBRARY ieee; USE
ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY pr_encode IS port( I:in
std_logic_vector(0 to 3);y:out std_logic_vector(0 to 1);v:out std_logic); END ENTITY
pr_encode ; ARCHITECTURE pr_beh OF pr_encode IS BEGIN process (I) begin if I(0)='1 '
then y<="00" ; elsif I(1)='1' then y<="01" ; elsif I(2)='1' then y<="10"; else Y<="11"; end if;
if I="0000" then v<='0'; else v<='1'; end if; end process; END ARCHITECTURE pr_beh ;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY
mux8x1_beh IS port (I: in std_logic_vector(0 to 7); s : in std_logic_vector(0 to 2); y : out
std_logic); END ENTITY mux8x1_beh; ARCHITECTURE data_mux OF mux8x1_beh IS
BEGIN process (I,S) begin case s is when "000" =>y<= I(0); when "001" =>y<= I(1); when
"010" =>y<= I(2); when "011" =>y<= I(3); when "100" =>y<= I(4); when "101" =>y<= I(5);
when "110" =>y<= I(6); when "111" =>y<= I(7); when others =>y<= I(0); end case; end
process; END ARCHITECTURE data_mux ; Behavioral code for 8:1 multiplexer using
case statement

ADVANTAGES OF BEHAVIORAL MODELING:

ADVANTAGES OF BEHAVIORAL MODELING Code become compressed for complex
design. No need of any logical equation. Sequential or conditional statements can be used. No
need of structural information. Less time consuming. User can write behavioral code for any
design. It is fastest to simulate out of these three modelings. DISADVANTGES OF

BEHAVIORAL MODELING Behavior of the design should be known to the user . Hence for
industry purposes also behavioral modeling is best and mostly used also.

MIXED MODELING:
It is possible to mix the three modeling styles that we have seen so far in a single architecture
body. Within an architecture body , we can use :- MIXED MODELING Here first d latch is
declared as component i.e. using structural modeling. clock of second latch assigned value
using dataflow modeling. And final output is achieved using behavioral modeling. component
instantiation statements( that represent structure ), concurrent signal assignment (that
represent dataflow) and process statements (that represent behavior). Example of a mixed
modeling:

ADVANTAGES OF MIXED MODELING:

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all ; ENTITY d_latch
IS por t( d,clk:in std_logic;q1,q1b: out std_logic); END ENTITY d_latch ; ARCHITECTURE
latch OF d_latch IS Component latch1 Por t( d,c:in std_logic;q : inout std_logic); (structural
modeling) End component ; BEGIN L1: latch1 port map (d, clk ,q); C1<=not clk ; (data flow
modeling) process (d,c1) begin if (c1='1') then (behavioral modeling) q1<=d; q1b<= not (d);
end if; end process; END ARCHITECTURE latch; Vhdl Code for master slave d-flip flop
using mixed modeling ADVANTAGES OF MIXED MODELING Code become easier for
complex design. Code can be written block wise.. Sequential or conditional statements can be
used. Less time consuming.

TEST BENCH:
TEST BENCH A test bench is a model that is used to verify the correctness of a hardware
model. A vhdl test bench consists of an architecture body containing an instance of the
component to be tested and process that generate sequences of values on signals connected to
the component instance. The expressive power of the VHDL language provides us with the
capability of writing test bench models in the same language.

Slide 18:
To generate stimulus for simulation(waveform). To apply this stimulus to the entity under test
or design under test and collect the output responses. To compare output responses with
expected values. A test bench has three main purposes or we can say that there are three steps
to verify a design: Now if the output responses are same as expected values we can say that
design is correct otherwise not correct.

Example of a test bench for full adder::

Example of a test bench for full adder: Library ieee; Use ieee.std_logic_1164.all; Test bench
full_adder is End test bench ; Architecture test_fulladder of full_adder is Component
full_adder Port (A,B,C: in std_logic; SUM,CARRY: out std_logic); End component; Signal
A,B,C,SUM,CARRY:std_logic ; Begin Process Begin A<= 0; B<=0; C<=0; Wait for 5ns
; A<=0; B<=0; C<=1; Wait for 5ns; A<= 0; B<=1; C<=1; Wait for 5ns; A<= 1;
B<=1; C<=1; Wait ; End process; End architecture ;

Slide 20:
Advantages or Industry application of Test Bench It prevents wastage of time in
programming the same design again and again. Most Designs are tested using test bench in
industries.

Slide 21:
thank you