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A Project Report

on
Analysis of gate underlap channel double gate MOS transistor
For electrical detection of biomolecules.

Submitted in the Partial Fulfillment of the Requirements


for the award of
Bachelor of Technology
in
Electronics & Communication Engineering
By
Krishna Kumar Verma [20128036]
Kapil Garg [20126035]
Under the guidance of
Dr. Santosh Kumar Gupta
Assistant Professor

Department of Electronics & Communication Engineering


Motilal Nehru National Institute of Technology Allahabad
Allahabad INDIA

Department of Electronics & Communication Engineering


Motilal Nehru National Institute of Technology
Allahabad India

CERTIFICATE

This is to certify that the work contained in this project titled ANALYSIS OF GATE
UNDERLAP

DOUBLE

DETECTION

OF

GATE

MOS

BIOMOLECULES,

TRANSISTOR
submitted

by

FOR

ELECTRICAL

Krishna

Kumar

Verma[20128036], Kapil Garg[20126035] in the partial fulfillment of the final year project
for the award of Bachelor of Technology in Electronics and Communication Engineering to
the Electronics and Communication Engineering Department, Motilal Nehru National
Institute of Technology, Allahabad, is a bonafide work of the students carried out under my
supervision.

Date: 27-04-2016

Dr. Santosh Kumar Gupta

Place: Allahabad

(Asst. Professor)
ECE Department
MNNIT, Allahabad

Acknowledgement
We are thankful to our mentor Dr. Santosh Kumar Gupta whom we are very proud to
work under, and without whose guidance we wouldnt have been able to complete this
project.
We would like to express our sincere thanks to Prof. P. K. Chakrabarti, Director, Prof. V.K
Srivastava, HOD (Electronics and Communication Engg.) MNNIT, Allahabad for giving us this
opportunity of undertaking this project.
We thank all the staff members of the department for their cooperation which led to the
completion of our project work.
We also wish to express our indebtedness to our parents as well as our family members whose
blessings and support always helped us to face the challenges ahead.
We are thankful to our friends and peers who gave us valuable suggestions, supported and
helped us.

Date: 27-04-2016

Krishna Kumar Verma (20128036)

Place: Allahabad

Kapil Garg (20126035)

ABSTRACT

In this Project, an analytical model for gate drain underlap channel Double-Gate MetalOxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical
detection of biomolecules has been proposed.
The conformal mapping technique has been used to derive the expressions for surface
potential, lateral electric eld, energy bands (i.e.conduction and valence band) and threshold
voltage (Vth).
Subsequently a full drain current model to analyze the sensitivity of the biosensor has been
developed.
The shift in the threshold voltage and drain current (after the biomolecules interaction with
the gate underlap channel region of the MOS transistor) has been used as a sensing metric.
The tool which had been used throughout the project work is SILVACO TCAD ATLAS 3D
(DESIGN AND SIMULATION).

TABLE OF CONTENTS

CHAPTER 1: INTRODUCTION

1.1: Cramming more no. of Transistors

1.2: Making the device smaller

1.2: Increasing no. of Gates

1.3: Need of Multi-gate Device

1.5: Short Channel Effects

1.5.1: Drain Induced Barrier Lowering (DIBL)

1.5.2: Leakage Current

1.5.3: Change in Sub-threshold Slope

1.5.4: Velocity Saturation

10

1.5.5: Hot Electrons

11

CHAPTER 2: DOUBLE GATE MOS TRANSISTOR

12

CHAPTER 3: FET SENSORS FOR DETECTION


OF BIOMOLECULES

16

3.1: Introduction

17

3.2: Dielectric Modulated FET

17

CHAPTER 3: MOTIVATION

18

CHAPTER 4: LITERATURE REVIEW

21

CHAPTER 5: SIMULATION TOOLS

25

5.1: Introduction

26

5.2: TCAD Simulation Software

26

5.3: Key Features

27

5.4: Deck Build: Interactive Deck Development & Runtime Environment

27

5.5: Tonyplot: 2D/3D Interactive Visualization Tools

28

CHAPTER 6: SIMULATION MODELS

29

CHAPTER 7: SIMULATION DETAILS

32

7.1: Control Parameters

33

7.2: Values of the Parameters

34

7.3: Base Program

34

7.4: 3-D Structure generated by the Program

37

CHAPTER 8: SIMULATION RESULTS & DISCUSSIONS

38

8.1: Variation in parameters with respect to Concentration

39

8.2: Variation in parameters with respect to Fin length

40

8.3: Variation in parameters with respect to Height of the Fin

41

8.4: Variation in parameters with respect to Fin Width

42

8.5: Variation in parameters with respect to Oxide Thickness

43

8.6: Variation in parameters with respect to Buried Oxide Thickness

44

8.7: Variation in parameters with respect to Underlap Channel Length

44

8.8: Variation of Surface Potential and Electric Field w.r.t Underlap Channel-

52

-length
8.9: Drain Current Vs Gate Voltage Variations

54

8.10: Drain Current Vs Drain Voltage Variations

55

CHAPETR 9: CONCLUSIONS & FUTURE SCOPE

56

References

59

List of Figures

Figure

Page

Fig. 1.1 Evolution of no. of transistors per Processors up to 2010

Fig. 1.2 Increasing complexity in manufacturing technology of planar

MOSFETs as the device dimension shrinks.


Fig. 1.3 Bulk MOSFETs & FD-SOI

Fig. 1.4 FD-SOI tailor made for (a) high performance

(b) low performance


Fig. 1.5 Different Multi-gate Devices

Fig. 1.6 Effect of VDS on Threshold Voltage (VT) in a Single MOSFET

Fig. 1.7 DIBL in Bulk, FD-SOI & DG-MOSFET

Fig. 1.8 Sub-threshold Slope as property of VGS Vs ID graph

Fig. 1.9 Short Channel Devices Suffer from Velocity Saturation

10

Fig. 2.1 Birds eye view of a Fin-FET

14

Fig. 2.2 Cross-Sectional view of a Fin-FET

15

Fig. 5.1 Block Diagram of Silvaco Software

27

Fig. 5.2 Flow Chart of ATLAS working module

28

Fig. 7.1 2-D Structure of a Double Gate DMFET

33

Fig. 8.1 ID -VGS graph for different Concentrations

39

Fig. 8.2 ID -VGS graph for different Fin-lengths

40

Fig. 8.3 ID -VGS graph for different Fin-heights

41

Fig. 8.4 ID -VGS graph for different Fin-widths

42

Fig. 8.5 ID -VGS graph for different Oxide thickness

43

Fig. 8.6 Variation in Sub-threshold Slope with respect to Channel length

45

Fig. 8.7 Variation in DIBL with respect to Channel length

46

Fig. 8.8 Variation in Trans-conductance with respect to Channel length

46

Fig. 8.9 Variation in ION/IOFF with respect to Channel length

47

Fig. 8.10 Variation in O/P Trans-conductance w.r.t VDS for different underlap

48

Length (VGS=0.6V)
Fig. 8.11 Variation in TGF w.r.t VGS for different underlap length (VDS=1V)

49

Fig. 8.12 Variation in Early Voltage w.r.t VGS for different length (VDS=1V)

50

Fig. 8.13 Variation in Intrinsic Gain (AV) w.r.t VGS for different length (VDS=1V) 50
Fig. 8.14 Variation in fT w.r.t VGS for different underlap channel length (VDS=1V) 52
Fig. 8.15 Variation of Surface potential with Channel

53

Fig. 8.16 Variation of Electric Field w.r.t Channel

53

Fig. 8.17 ID Vs VGS variation for two different values of VDS

54

Fig. 8.18 ID Vs VGS variation for two different underlap length

55

List of Tables

Table

Page

Table 2.1: Advantages of Fin-FET Technology

13

Table 7.1: Values of the Parameters

34

CHAPTER 1
INTRODUCTION

The hotspot of research and development in the VLSI industry is the design of newer devices
which have better performance in terms of speed and power dissipation. A prominent reason
for this quest for research and development is the growing need for faster computers that
require very less power. Several digital logic families have been developed and tested but
CMOS has emerged as the choice of the industry, because it offers the least static and
dynamic power dissipation while in operation. At the heart of CMOS lies the MOSFET.
MOSFETs that are used presently for a large no. of general devices have single gate and are
planar in structure. Further, they are made up mainly of silicon, which makes them unfit for
high frequency applications. The planar structure of MOSFET with single gate cannot be
scaled down beyond a certain limit with the conventional scaling techniques. Reduction of
the threshold voltage, which is known as voltage scaling is limited by the increased leakage
current. Further, the requirement of high channel doping degrades mobility, increases band to
band tunneling (BTBT) and causes threshold voltage fluctuations. Thus, newer devices with a
paradigm shift in the design and scaling techniques have to be formed. One such design
methodology is Double Gate MOSFET (DGMOS). DGMOS is a member of a general multi
gate technology designed specially to improve the short channel effects encountered in the
scaled version of the conventional single gate MOSFET. Further, the hetero structure, as
discussed in this report enables the transistor to operate and a frequency range of
microwaves, thus making MOS suitable for the high frequency operations.
1.1 Cramming more number of transistors: Moores law
The co-founder of Intel, Gordon Moore in 1965, published a paper Cramming more devices
onto Integrated Circuit, with a bold prediction that the number of transistors per chip will
quadruple every three years. This prediction is famously called as Moores law. In 1975 he
modified the law by stating that the doubling time of transistors on an IC will be two years.
However, the period is often quoted as 18 months because the chip performance, which
depends on the combined effect of more number of transistors and they being faster, doubles
in every 18 months .Little did the world knew, that even after 50 years, the law will remain
valid in the semiconductor industry, with a minor modification.
Moores law has been the driving force in the industry to fit in more and more no of
functional units in a single integrated circuit, to make devices extra powerful and fast. But
there has to be a limit on the numbers imposed by the very virtue of the law that is we never
cram infinite no. of transistors. The numbers have to saturate at some level if the VLSI
2

technology is not changed. It is this quest to keep pace with Moores law has kept the
research in the design and fabrication technology alive.
Now, International Technology Roadmap for Semiconductors (ITRS) issues reports to
describe the type of technology, design tools, equipment and metrology tools that have to be
developed in order to make newer, faster and more capable devices. These reports make a
guideline and provide a direction along which the industry develops to acquire the desired
devices.

Fig. 1.1: Evolution of number of transistors per processor up to 2010.

1.2 Making the device smaller


Making a device smaller by scaling it down brings to us several advantages. They are:
a. Enhanced speed: When the device dimensions shrunk, the effective channel length is
reduced. Since mobility of electrons is independent of the device dimension, it
remains constant. Further, the electric field density in the channel region also
increases, as the area is significantly reduced. This leads to an enhanced speed as
more number of electrons flow in a relatively shorter channel.
3

b. Low power consumption: A scaled down device requires that the voltage supply, must
also be brought down, to ensure that the electric field created in the channel region
must not lead to an avalanche breakdown or punch through. So, when the voltage
supply is reduced, the power consumption is also reduced.
However, as the following picture indicates, scaling down a planar single gate MOSFET is
not an easy task. As, we know a lot of steps are required from designing to final fabrication of
a device, adjustments are required at each stage. For example, even if we simulate a device of
very small channel length properly in any simulator, taking into considerations all the device
physics, still modifications at the higher stages, will pose a big challenge. We need to develop
altogether new sets of masks, photolithographic techniques, etching methods and epitaxial
growth techniques. Thus, it is perfectly clear that whenever the device dimension goes down,
a lot of effort is required at every processing step from mask preparation to final device
fabrication. At every stage of downscaling the complexity of manufacturing technology goes
on increasing. At a channel length of 20nm, the bulk MOSFET manufacturing technology
becomes so complex that it becomes non-sustainable. Thus a whole new set of technology is
required for reducing complexity in processing of these short channel devices.

Fig. 1.2: Increasing complexity in manufacturing technology of planar MOSFET as the device dimension shrinks.

1.3 Increasing number of gates in MOSFET


In the previous section we saw, that it is not easy to scale down a planar MOSFET device.
MOSFET cant be scaled down arbitrarily. Proper ratio of channel length to width has to be
maintained. Further, not only the silicon bulk is reduced in dimension, with it the other
material dimensions like thickness of oxide, thickness of electrode material, proper choice of
electrode has also need to be taken care of. Doping concentrations pose yet another challenge
in the downscaling as high doping concentration leads to mobility degradation. So a lot of
second order effects arise like short channel effects as a result of reduced channel length and
shrunken dimensions and to effectively control them without compromising with the reduced
size is the main objective. The biggest drawback associated with a short channel length
device is that, the control of gate electrode on the electric field inside the channel is reduced.
Thus the current in the channel no longer remains a function of gate voltage only or a
combined function of gate vs source voltage and drain vs source voltage as in single gate
planar MOSFETs. Several other factors like drain potential, band to ban tunneling, random
fluctuations in threshold voltage levels also begin to modulate the current through the
channel.
Thus, the problem itself hints a paradigm shift in the technology of manufacturing of short
channel devices. The new technology has to be the multi gate technology, in which there are
more than one gate, surrounding the channel between drain and source from more than one
side. More number of gate electrodes ensures that the behavior of parameters in the channel
like threshold voltage, leakage current etc., remain under the control of gate voltage only.
This in turn results in the considerable reduction of short channel effects, a big menace to
shorter devices. Though multi gate devices is one solution to one of the many problems of
short channel effects, several different technologies have been proposed which can help
reduce or eliminate the other problems grouped under the short channel effects to a great
extent at sub-micrometer dimensions and have moderate manufacturing complexity. These
technologies include: Fully Depleted- Silicon on Insulator devices (FD-SOI), Double Gate
Fully Depleted- SOI (DG FD-SOI), Triple Gate devices, Double and Triple gate Fin-FET
devices, Cylindrical gate devices, Gate All Around (GAA) etc. Each of them has its own sets
of advantages and disadvantages and each of them handles the problem of short channel
devices in fundamentally similar ways. The recent trend is however towards increasing use of
gate all around devices (GAA) as they not only provide the best performance but also are
easier to fabricate due to their inherent geometry.
5

1.4 Need of Multi-gate Device


Planar transistors have been the core of integrated circuits for several decades, during which
the size of the individual transistors has steadily decreased. As the size decreases, planar
transistors increasingly suffer from the undesirable short-channel effect, especially "off-state"
leakage current, which increases the idle power required by the device. So this problem is
overcome by a multi-gate device, in this:1. The channel is surrounded by several gates on multiple surfaces. It thus provides a better
electrical control over the channel, allowing more effective suppression of "off-state" leakage
current.
2. Multiple gates also allow enhanced current in the "on" state, also known as drive current.
3. Multi-gate transistors also provide a better analog performance due to a higher intrinsic
gain and lower channel length modulation. Non-planar devices are also more compact than
conventional planar transistors, enabling higher transistor density which translates to smaller
overall microelectronics.

Fig. 1.3:Bulk MOSFET and FD-SOI .

Fig. 1.4 FD-SOI tailor made for a) high performance and


b) low power .

Fig. 1.5: Different Multi Gate devices.

Having said so much about the short channel effects, it is worth in place to discuss about
them in detail.
1.5 Short Channel Effects
A MOSFET device is considered to be short when the channel length is of the same order of
the depletion width of the source and drain junction. A single gate electrode cannot effectively
control the flow of electrons in the channel, and several other factors also begin to operate in
the channel as a consequence of SCEs.
There are in general six types of SCEs:
a. Drain Induced Barrier Lowering
b. Leakage Current
c. Change in Sub- threshold Slope
d. Velocity Saturation
e. Surface Scattering
f. Hot Electrons
1.5.1 Drain Induced Barrier Lowering (DIBL)
In a long channel MOS, the inversion layer formation is solely dependent on the gate
electrode potential. That means, once the voltage at the gate electrode crosses the threshold
voltage of the device, the channel will form and the device starts to conduct. The drain to
7

source voltage (VDS) has no effect at all on the threshold voltage. Not only the threshold
voltage, increasing VDS does not affect the sub-threshold slope and it increases the on and off
current by the same amount. However, as the device dimensions shrink, the depletion regions
at drain and source junctions began to interact, which causes a degradation in device
performance during on state. As a result, a control is established in by the drain to source
voltage (VDS) over the barrier potential. The result is that even the application of this voltage,
without the application of gate voltage causes the inversion layer to form and leads to the
flow of electrons from Source to Drain. Thus, the threshold voltage gets controlled by V DS
also.

Fig. 1.6: Effect of Drain to Source voltage (VDS) on Threshold voltage (VT) in Single gate MOSFET device.

Fig. 1.7: DIBL in bulk, FD-SOI and DG MOSFET.

1.5.2 Leakage Current:


Short Channel MOS devices are hard to turn off. Even, when no gate voltage is applied, there
is still some leakage current, due to Electric field interaction between Drain and Source
depletion regions. This interaction is quite significant at channel length of 20 nm. The planar
single gate MOS is not capable to deal with these leakage current which is also known as subthreshold current. They can be reduced by terminating some of those electric field lines
produced by depletion regions in buried oxide layer (BOX).
1.5.3 Change in Sub- threshold Slope:
Sub- threshold slope is a property of drain current vs gate to source voltage characteristic.
When the gate voltage is below the threshold value, there seems to be no current in the
channel. But as soon as the gate voltage crosses the threshold value, current begins to rise
exponentially. The seemingly zero current in off state-when the gate voltage is below
threshold voltage-Ioff is actually not zero. It begins to build up as soon as the gate voltage
reaches near the threshold value and the log of the drain current in off state has a steep slope,
which indicate that the drain current builds up very rapidly. This slope is known as
subthreshold slope and its expression is given as: S

. In short channel length device

the sub- threshold slope changes as compared to its ideal value. This reason being an
increased Ioff current due to leakage and high doping concentrations.

Fig. 1.8: Sub threshold slope is a property of VG vs ID graph

1.5.4 Velocity Saturation:

Fig. 1.9: Short channel devices suffer from velocity saturation.

The electron velocity is related to the electric field via a parameter called mobility. The drift
velocity of the electrons is defined as

where

is called the mobility, and E is the

electric field in the channel. The mobility itself is a function of the electric field and remains
constant only if the electric field value is less than 10 3 V/cm in an n-type silicon. For electric
field lying in the range 103 to 104 V/cm, mobility varies as E(-1/2) and for still higher values,
mobility varies inversely with the electric field. Thus as a result, when the electric field
reaches a critical value, (1.5x 106 V/m) the velocity of the carriers tend to saturate because at
one hand electric field is increasing while at the other hand the mobility is decreasing at the
same rate at which the electric field is increasing. Now as we know, in the channel, E depends
on VDS. For, a long channel device, the critical value of electric field is reached at a voltage
VDS = VG VT, i.e. in the case of saturation of the MOSFET. But for a short channel device,
the critical value of electric field is reached at a much lower value of V DS. Thus, velocity
saturation occurs earlier in short channel device. This is not desirable at all, because it defies
the very purpose of making short channel devices, i.e. enhanced speed.

10

1.5.5 Hot Electrons:


Electric field density increases greatly at very small device dimension. As a result, electrons
become highly energetic and result in various hot carrier effects. In one of the effect the hot
electrons tunnel through the barrier and enter the oxide layer. This results in trapped oxide
charges causing thereby a change in VT and I-V characteristic of MOSFET. Thus, the high
energy electrons can enter the oxide, where they can be trapped, giving rise to oxide charging
that can accumulate with time and degrade the device performance by increasing Vt and affect
adversely the gates control on the drain current.

11

CHAPTER-2
DOUBLE GATE MOS TRANSISTOR

12

2.1 INTRODUCTION
A double gate MOSFET is patterned either as a planar structure or a 3D gate structure, much
like a FinFET but the oxide thickness on the upper surface is much high to prevent any effect
of that gate on the channel region of the device. Thus the upper gate effectively applies no
influence on potential and Electric field inside the device, which are solely determined by the
front and the back gate. Generally, the latter structure for the double gate MOSFET is chosen
to reduce the problems of misalignment associated with the patterning of a planar double gate
MOSFET. But the former structure has its own advantage in terms of lesser material required
for fabrication as well as, lesser complexity. If the device of interest has channel length upto
40 nm length, the former structure is preferred. This is because all the masking and patterning
schemes have well been developed for the channel length in that regime.

Fig 2.1: A general double gate MOSFET

Fig 2.2: A double gate Fin-FET device.

13

We have seen earlier that double gate hetero structure MOSFET is a multi-gate device, which
effectively controls the short Channel effects and corner effects, which other multi-gate devices find
difficult to handle. This ability of double gate hetero structure MOSFET lies in its structure itself.
There are two electrodes each for source and drain.The height of electrodes is called the height of
the fin, and the width of electrodes is called the width of the fin.Channel as usual, lies between the
source and the drain and is surrounded by gate electrode at most from three sides. The channel has a
vertical structure. Still, in contrast to the vertical MOS (VMOS) the current in double gate hetero
structure MOSFET flows horizontally. In addition to the removal of the problem of SCEs, the
double gate hetero structure MOSFET structure also ensures that the front gate and the back gates
are not misaligned.
There are two varieties: planar and vertical structures. The former group contains ground
plane and back-gate devices, which are derivatives of the SOI device. A Planar Dual-GateSiliconOn-Insulator (DGSOI) structure consists, basically, of a silicon slab sandwiched between two
oxide layers. A metal or a poly silicon film contacts each oxide. Each of these films acts as a gate
electrode (front and back gate), which can generate an inversion region near the Si-SiO2
interfaces if an appropriate bias is applied. Thus, we would have two MOSFETs sharing the
substrate, source and drain. The outstanding feature of these structures lies in the concept of
volume inversion. If the silicon film is thicker than the sum of the depletion regions induced by
the two gates, no interaction is produced between the two inversion layers. The operation
of this device is similar to that of two conventional MOSFETs connected in parallel. The
vertical structure differs from the fin structure in the sense that the direction of current flow in the
vertical MOSFET is vertical but in double gate hetero structure MOSFET even though the
structure seems vertical the direction of current flow is still horizontal, and hence the channel
length is not across the body of the device instead it is along the body of the device.
The choice of materials used for hetero structure devices depend solely on the application
14

areas the device will be used in. However, most generally we go for the hetero structure
devices only in high frequency applications where normal devices fail to operate
satisfactorily. The primary area of application includes oscillators and amplifiers circuits in
microwave range. Thus the materials used for the heterostructure devices include compound
semiconductors like GaAs, InAlAs, InP, AlInN, GaN etc. The GaN/GaAs material generally
form the channel, while InAlAs forms the barrier layer. While the channel is lightly or
negligibly doped, the barrier layers are heavily doped. During the operation, the charges in
the barrier layer are attracted by the GaAs layer in the channel due to the high electron
affinity of the Gallium Arsenide. Thus, this leads to a formation of high mobility electron
cloud at the interface which is the reason behind these HEMTs.

15

CHAPTER 3
FIELD EFFECT TRANSISTOR SENSORS
FOR DETECTION OF BIOMOLECULES.

16

3.1 Introduction:
A lot of research interest has been shown by the researchers in the area of FET based
biosensors in last few decades, due to their numerous advantages, such as compatibility with
the

standard

Complementary

Metal-Oxide-Semiconductor

(CMOS)

technology,

miniaturization, cost effective mass production, high sensitivity and label free detection
process. There are many other compatible structures with the standard CMOS process such as
Fin-FET, G4-FET, and SOI. The first FET based sensor i.e., ion-sensitive field-effect
transistors (ISFET) was investigated by Bergveld in 1970.
The basic structural difference between an ISFET and conventional Metal-Oxide-Semiconductor
Field-Effect Transistor (MOSFET) is that the metal gate is replaced by an ion-sensitive membrane,
an electrolyte solution and a reference electrode. The working principle of an ISFET depends on the
change in electrical properties i.e. conductance, threshold voltage or current, due to the presence of
charged biomolecules between the gate dielectric and ionic solution. It has some significant
advantages i.e, 1) high input impedance and low output impedance, 2) small size and weight, 3) fast
response and high sensitivity, 4) low cost mass production. Besides, there exists some drawbacks
also, such as, it lacks in the detection of neutral biomolecules and compatibility with the standard
CMOS process.
3.2 Dielectric Modulated Field Effect Transistor (DM-FET):
In order to overcome these problems, a modified architecture of FET based sensor was
proposed in the form of dielectric modulated field-effect transistor (DM-FET), where the
insulator layer is etched to carve out a vertical nano-gap underneath the gate material DMFET is capable of detecting the neutral biomolecules as well and shows great compatibility
with standard CMOS process. The working principle of DM-FET involves the change in gate
capacitance due to immobilized biomolecules in the cavity region, resulting in the change of
electrical parameters such as, threshold voltage and current. Thus, either absence or presence
or other properties of the biomolecules (such as its charge) results in variation of electrical
parameters which can be quantified in terms of sensitivity of biosensor. In absence of
biomolecules, cavity region is filled with air i.e. dielectric constant of cavity region is unity
and thus gate capacitance is low.
When biomolecules are present in the cavity region the threshold voltage, Vth of DM-FET
decreases due to the change of dielectric constant of the cavity from unity to a higher value.
17

However, DM-FET has few limitations, such as, low binding probability in carved cavity
region and low structural stability stemming from the mechanically suspended nano-gap
structure. Recently a gate underlap DM-FET architecture has been reported, where both gate
material as well as the insulation layer is etched out to make the gate underlap region which
is useful for binding of biomolecules. Its working principle is similar as that of the
conventional DM-FET. The underlap DM-FET structure provides additional opportunities for
biomolecules to bind on the sensing area. Since underlap DM-FET has open cavity instead of
closed cavity as present in the conventional DM-FET structure, the change in the electrical
properties, threshold voltage and drain current is more for underlap DM-FET in comparison
to conventional DM-FET. Furthermore, the gate underlap DM-FET can be fabricated by
following the process steps; the channel region of the underlap DM-FET is masked by
photoresist and arsenic ion implantation is performed to form the n-type source and drain
region. Subsequently the gate dielectric layer is grown on the channel region by thermal
oxidation. Thereafter aluminum is deposited as a gate electrode. Gate underlap region is
formed by etching the gate material and the insulating layer from the channel end near the
drain side.
Present work focuses on the development of an analytical model for gate drain underlap DG
MOSFET working as the bio-transistor. The device electrostatics is developed using the
conformal mapping technique and thereafter complete drain current characteristics are
evaluated. Subsequently, the impact of underlap length on device sensing parameters i.e.
threshold voltage has also been studied.
It is important to notice that dry environment condition is assumed for the detection purpose
because of the following advantages of dry environment over the watery environment (a) The
dry environment can provide high degree of freedom for various structures that may improve
the sensor characteristics, (b) The electrical signal of the biosensor does not depend on the
Debye length, which is the function of ionic concentration of the sample solution[4]and (c)
The interaction potential between the receptors and analyzes that causes the conductance to
change in FET based sensor is partially screened by strong ionic strength of the buffer
solution. This screening directly depends on Debye-Huckel length. Therefore, Debye
screening-free sensing is another advantage of the biosensors which are working under the
dry environment.

18

CHAPTER 3
MOTIVATION
19

20

There are two primary motivations behind the project. The first being the removal of the short
channel effects faced by the smaller, sub micrometer range devices. The second and the major
motivation is to make the device suitable for detection of neutral biomolecules along with the
charged ions, keeping into consideration the improved carrier transport efficiency in the
channel. The DM-FETS has been developed to overcome the problems faced by a
conventional IS-FETS. It is a one-for-all solution to the problems of detection of neutral
biomolecules, and shows great compatibility with standard CMOS processes.
Double gate MOSFET attempts to overcome the worst types of short-channel effect
encountered by deep submicron transistors, such as drain-induced barrier lowering (DIBL).
These effects make it harder for the voltage on a gate electrode to deplete the channel
underneath and stop the flow of carriers through the channel, in other words, to turn the
transistor off. By raising the channel above the surface of the wafer instead of creating the
channel just below the surface, it is possible to wrap the gate around up to two of its sides,
providing much greater electrostatic control over the carriers within it.
We go for hetero structure if we need high speed applications. A hetero structure is formed
when two semiconductor materials are grown into a sandwich. One material is used for outer
layers, and the other which has lower band gap is used for inner layer. There must be two
boundaries to form a double hetero structure device.
Dual material in gate is a new concept to improve the carrier transport efficiency inside the
channel. There are two different metals used in the gate electrode. The metal nearer to the
source has higher work function, than the metal closer to the drain. This ensures a constant
electric field inside the channel as opposed to single material gate, hence the electrons do not
scatter away from the desired path in the channel.
The evolution of high-speed GaAs ICs, is to utilize the superior electronic properties of GaAs.
The hetero structure formed using the layers of GaAs with InAlAs, gives higher electron
mobility and superior performance in high frequency applications. Further at the microwave
frequency range, where the normal MOSFETs succumb to perform, the GaAs, devices can
work because they are formed by the modulation doping technique, which improves their
carrier transport efficiency. Hence, hetero structure GaAs devices constitute the major part of
High Electron Mobility Transistors (HEMTs).

21

CHAPTER 4
LITERATURE REVIEW

22

Lilienfeld Julius Edgar, in1925 patented the first idea on field effect transistors. In his patent
titled Method and apparatus for controlling electric currents he described a method of and
an apparatus of controlling the flow of current in between two terminals of an electrically
conducting solid by establishing a third potential on a terminal which is in between the said
terminals. Not only this, he also talked of the various applications of this solid device in
amplifier and oscillator circuits which were till then made up of only vacuum diodes and
triodes and were excessively clumsy and bulky. Though the device was primitive and
rudimentary by todays standards of technology yet it needs special mention because it
emancipated an era of an altogether new thought of solid state devices and the related
physics.
His idea did not grab much attention then. But almost 35 years later, at Bell s laboratory, in
1960, Kahng and Dawon in their patent , successfully modeled and fabricated the first
insulated gate field effect transistor, by eliminating the problems of surface states that blocked
the penetration of electric field inside the semiconductor body. This device due to the
materials used in its fabrication came to be known as MOSFET (Metal Oxide Semiconductor
Field Effect Transistor). The gate electrode (terminal) was made up of metal. Beneath it there
was Silicon oxide layer, which insulated the gate from the bulk silicon body. The device was
initially designed for the channel length greater than 1000 nm but at the same time gave
flexibility to scale down the device, well up to 200 nm channel length. The initial device that
was made was a p-channel MOSFET because, at that time, the technology was not developed
enough to make pure silicon oxide free from any trapped oxide charge.
Later, several modifications were done in the above proposed device, like replacing the metal
gate with the poly silicon gate. These modifications were more of industry driven than the
ones proposed by academicians. The reason was obviously to look for simpler fabricating
steps. For instance, the primary motive for the poly silicon gate technology was ease of
working with the ploy silicon material which unlike metals, does not melt at high
temperatures, the device is subjected to, during fabrication.
However the major breakthrough in the world of MOSFET was destined to come with the
Scaling theory as proposed by Dennard and Gaensslen in 1972. In this paper, the famous
Dennard Scaling Theory was presented which was named after Dennard himself. The scaling
law was formulated to scale down MOSFET to micrometer regime. It had two parts: voltage
scaling and current scaling. The idea was that the power density of the MOSFET device
23

remains constant and hence, both the voltage and current levels have to be scaled down in
proportion of the channel to ensure that device remains compatible. That simply meant if the
channel length and width, both are reduced by a factor of k then the voltage and current
levels have also to be reduced by the factor of k so that the expression (voltage * current)/
(length *width) remains the same. Thus the paper presented a method to scale down the
lateral and vertical dimensions, doping levels, operating voltages and current levels in a selfconsistent fashion. The small devices hence obtained are free from the deleterious effects of
short channel. It was this scaling theory that actually gave teeth to the Moores law and
helped it survive the tests of time.
However, Dennard scaling law also broke down around the year 2006-07 because of
limitations in fabrication technology of single gate planar MOSFET devices. This is because
the pressure put by the idea of keeping pace with the Moores law, was way too much for the
fabrication industry to handle. As the channel length grew smaller, the thickness of oxide and
gate electrode has to be reduced. Thus at 50 nm range the gate electrode becomes so thin that
its effect on channel is greatly reduced. Also the static power consumption when the device is
not in use increases because of high leakage current in short channel devices. The problem of
breaking down of Dennard scaling is often known as dark silicon. Thus, a paradigm shift in
the making of devices and ICs happened. While industry responded to this problem by using
multicore technology in processor, the academicians resorted to the research in multi-gate
technology.
The initial papers on multi gate technology preached about using more than one gate around
the channel to establish effective control of the gate voltage on the drain current. Further, the
aim was to eliminate the problem of DIBL and leakage current. But none of them were based
to improve high speed applications of the. Earlier, devices were not able to operate
satisfactorily in microwave and above frequency range.
As we know, carrier transport efficiency depends on the effective control of gate voltage in
the channel region. Thus, underlap channel has to be created to study and analyze the
movement of carriers in the channel under the application of gate voltage.
VLSI performance is improved by planar device scaling according to Moores law for past
decades. However, for 20 nm technology and beyond, it is very difficult to meet ITRS targets,
especially short channel effect (SCE) control and suppression of device performance
variability, by planar device scaling. Therefore, there is a strong interest in new device
24

architectures. Double gate dielectric modulated MOSFET sensor is one of the most promising
device structures for scaled CMOS/memory applications thanks to its good SCE
controllability its small variability and ability to bind on the sensing area. However, the future
of Double gate dielectric modulated MOSFET sensor is not so obvious due to low binding
probability in carved cavity region and low structural stability stemming from the
mechanically suspended nano-gap structure

25

CHAPTER 5
SIMULATION TOOL

26

5.1 Introduction:
As the complexity and challenges in semiconductor technology increases, there is a great
need for some powerful simulation tools to aid in design and solution of the problems.
Design, fabrication and characterization on transistors are getting much more complex with
methods of solving short channel effects and scaling MOSFETs channel has become much
more complicated. However, MOSFET is still the mostly used component in integrated
circuit design for chips which is used in microprocessors and microcontrollers to run
electronic gadgets.
Apart from that, the cost factor also needs to take into consideration in fabrication
process. It is because the repeating trial and error fabrication process is not only timeconsuming, but also uses up costly resources or materials that might be implemented to
improve the devices performance. Although the main material used to fabricate MOSFET is
just silicon, which considered a low cost material, the failure fabrication in the trial and error
process might also create unwanted wastes and cause the pollutions to the environment. As
such, the simulation tool becomes necessary today, as it allows virtual fabrication, simulate
and emulate the characteristics of the fabricated devices. With it, engineers, researcher and
analysts can make better improvement to the MOSFET design.
5.2 TCAD Simulation Software:
ATLAS enables device technology engineers to simulate the electrical, optical, and thermal
behavior of semiconductor devices. ATLAS provides a physics-based, easy to use, modular,
and extensible platform to analyze DC, AC, and time domain responses for all semiconductor
based technologies in 2 and 3 dimensions.
Atlas is used as a simulator whereas outputs from simulation are shown in tonyplot.

27

Figure 5.1 Block Diagram of Silvaco Software

5.3 Key Features:

Accurately characterize physics-based devices in 2D or 3D for electrical, optical, and


thermal performance without costly split-lot experiments

Solve yield and process variation problems for optimal combination of speed, power,
density, breakdown, leakage, luminosity, or reliability

Fully integrated with ATHENA process simulation software, comprehensive visualization


package, extensive database of examples, and simple device entry

Choose from the largest selection of silicon, III-V, II-VI, IV-IV, or polymer/organic
technologies including CMOS, bipolar, high voltage power device, VCSEL, TFT, electronic,
LASER, LED, CCD, sensor, fuse, NVM, Ferro-electric, SOI, Fin-FET, HEMT, and HBT

Connect TCAD to Tape out with direct import of ATLAS results into UTMOST for SPICE
parameter extraction

Parallel processing supported on multi-core and multiple processor SMP machines

28

Figure 5.2 Flow Chart of ATLAS working Module

5.4 Deck Build: Interactive Deck Development and Runtime Environment


Deck-Build is an interactive runtime and input file development environment within atlas
TCAD and several other SIMUCAD products can run. Deck-Build has numerous simulator
specific and general debugger style tools, such as powerful extract statements, GUI based
process file input, line by line runtime execution and intuitive input file syntactical error
messages. Deck-Build contains an extensive library of hundreds of pre-run examples decks
which cover many technologies and materials, and also allow the user to rapidly become
highly productive.
5.5 Tonyplot: 1D/2D Interactive Visualization Tool
Tony plot is a powerful tool designed to visualize TCAD 1D and 2D structures. Tonyplot
provides visualization and graphic features such as pan, zoom, views, labels and multiple plot
support. TonyPlot also provides many TCAD specific visualization functions, 1D cut lines
from 2D structures, animation of markers to show vector flow, integration of log or 1D data
files and fully customizable TCAD specific colors and styles.

29

CHAPTER 6
SIMULATION MODELS

30

The device was simulated on Silvaco Atlas. The conformal mapping technique has been
usedto derive the expressions for surface potential, lateral electric field, energy bands (i.e.
conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current
model to analyze the sensitivity of the biosensor has been developed. The sensing parameter
that is generally used for detection purpose is threshold voltage. For particular dielectric
constant (for e.g. K=5), the threshold voltage decreases as the gate material thickness
increases. This is due to the fact that the gate fringing effect increases in the underlap region
for thicker gate electrode. However, after tg=50 nm the threshold voltage does not change
much. At particular dielectric constant (for e.g. K=3), if the gate material thickness increases
then threshold voltage decreases.
The structure of gate underlap DG-MOSFET is similar to a conventional DG-MOSFET,
except the uncovered region between the edge of gate and drain, formed by etching the gate
material and the insulator layer (Al2O3) from the channel end at drain side. Al2O3is high-k
dielectric material, and prevents alkali ions diffusion from high osmolarity biological buffers
into the gate oxides and due to increased electrostatic coupling enhanced device sensitivity.
Therefore, Al2O3is considered as the gate oxide layer in this work instead of SiO2.
In this work, an SiO2 layer having thickness 1 nm is considered over the underlap region is to
account for the growth of native oxide on the underlap region whenever the silicon substrate
is exposed to air ambient. This uncovered channel region serves as a sensing site at which the
target biomolecules are introduced and immobilized. When the target biomolecules are absent
in the underlap region, dielectric constant of underlap region is unity, therefore, the threshold
voltage would be higher as compared to a gate overlap device, due to the change in the gate
dielectric constant (the dielectric constant of air is unity). When the target biomolecules are
immobilized on the sensing site, the dielectric constant will change from unity to a higher
value in the underlap gate region. Consequently, the device electrical characteristics such as
31

threshold voltage and drain current will also change in accordance with the dielectric constant
or charge of target biomolecules.
During simulation, Arora mobility model, field-dependent mobility (FLDMOB), ShockleyRead-Hall (SRH) recombination model, and Boltzmann transport model are used. Quantum
effects have not been considered in the simulation and model.
Before the biomolecules immobilization, the underlap region is empty and hence filled with
air (dielectric constant K=1).To simulate the presence of biomolecules in the underlap region,
an oxide layer is defined in the underlap cavity region with height=19 nm and the dielectric
constant of the oxide region is varied as K=3, 5, 7, 10. The height/thickness of the layer is
chosen so that biomolecules of various heights can be accommodated. For example, if DNA
has been immobilized then 50 base pair DNA can be easily accommodated. The range of the
charge density considered in this analysis for biomolecules is 10^-15 to 10^-16 per square
meter.
The fringing capacitance in the underlap region first decreases with increase in Lun/Lch ratio
and thereafter it becomes saturated for large Lun/Lch ratio. Fringing capacitance increases
with increase in the gate material thickness.

32

CHAPTER 7
SIMULATION DETAILS

33

7.1 Control Parameters:


Various parameters are needed to design a DM-FET. The parameters that are used to write the
program are listed below:Tox1 = Oxide thickness (Al2O3)
Tox2 = Oxide thickness (SiO2)
Tg=Gate material thickness
Tsi =Silicon thickness
Lg=Gate overlap channel region
Ns/d=Doping concentration of source and drain region.
Na= Channel doping
Lch= Length of channel region
Nf= Interface Charge density
Channel length= distance between source and drain in Field Effect Transistors; shorter the
channel faster switching by the FET can be achieved.
The dielectric constant () of the biomolecules is varied within a range of 1-10 (for e.g.
protein=2.50, biotin=2.63, APTES=3.57, and streptavidin=2.1).

34

7.2 Values of the Parameters:


The numerical values used to design DM-FET biomolecules sensor are:S no.

Parameters

Tox1

Value (nm)
Oxide

10

thickness
(Al2O3)
2

Tox2

Oxide

thickness(SiO2
)
3

Tsi

Silicon

50

thickness
4

Tg

Gate

material

10

thickness
5

Gate underlap Channel length

7.3 Base Program:


go atlas
mesh space.mult=2.0
x.mesh loc=0.000 spac=0.06
x.mesh loc=0.005 spac=0.05
x.mesh loc=0.105 spac=0.04
x.mesh loc=0.455 spac=0.05
x.mesh loc=0.605 spac=0.05
x.mesh loc=0.705 spac=0.06
x.mesh loc=0.710 spac=0.06
#
y.mesh loc=0.000 spac=0.06
y.mesh loc=0.005 spac=0.05
y.mesh loc=0.015 spac=0.04
y.mesh loc=0.024 spac=0.05
y.mesh loc=0.025 spac=0.05
35

100-150

y.mesh loc=0.075 spac=0.06


y.mesh loc=0.076 spac=0.06
y.mesh loc=0.085 spac=0.06
y.mesh loc=0.095 spac=0.06
y.mesh loc=0.100 spac=0.06
region number=1 material=Silicon x.min=0.005 x.max=0.105 y.min=0.025 y.max=0.075
region number=2 material=Silicon x.min=0.105 x.max=0.455 y.min=0.025 y.max=0.075
region number=3 material=Silicon x.min=0.455 x.max=0.585 y.min=0.025 y.max=0.075
region number=4 material=SiO2 x.min=0.585 x.max=0.605 y.min=0.025 y.max=0.075
region number=5 material=Silicon x.min=0.605 x.max=0.705 y.min=0.025 y.max=0.075
region number=6 material=Vacuum x.min=0.000 x.max=0.105 y.min=0.000 y.max=0.025
region number=7 material=Poly x.min=0.105 x.max=0.455 y.min=0.005 y.max=0.015
region number=8 material=Al2O3 x.min=0.105 x.max=0.455 y.min=0.015 y.max=0.025
region number=9 material=Air x.min=0.455 x.max=0.605 y.min=0.000 y.max=0.005
region number=10 material=oxide x.min=0.455 x.max=0.605 y.min=0.005 y.max=0.024
region number=11 material=SiO2 x.min=0.455 x.max=0.605 y.min=0.024 y.max=0.025
region number=12 material=Vacuum x.min=0.605 x.max=0.710 y.min=0.00 y.max=0.025
region number=13 material=Vacuum x.min=0.00 x.max=0.105 y.min=0.075 y.max=0.100
region number=14 material=Al2O3 x.min=0.105 x.max=0.455 y.min=0.075 y.max=0.085
region number=15 material=Poly x.min=0.105 x.max=0.455 y.min=0.085 y.max=0.095
region number=16 material=SiO2 x.min=0.455 x.max=0.605 y.min=0.075 y.max=0.076
region number=17 material=oxide x.min=0.455 x.max=0.605 y.min=0.076 y.max=0.095
region number=18 material=Air x.min=0.455 x.max=0.605 y.min=0.095 y.max=0.100
region number=19 material=Vacuum x.min=0.605 x.max=0.710 y.min=0.075 y.max=0.100
# #1=gate #2=drain #3=source
electrode name=fgate number=1 x.min=0.105 x.max=0.455 y.min=0.000 y.max=0.005
electrode name=fgate number=2 x.min=0.105 x.max=0.455 y.min=0.095 y.max=0.100
electrode name=drain number=2 x.min=0.705 x.max=0.710 y.min=0.025 y.max=0.075
electrode name=source number=3 x.min=0.000 x.max=0.005 y.min=0.025 y.max=0.075
#
contact name=fgate workfunction=4.7
contact name=drain workfunction=neutral
contact name=source workfunction=neutral
#
doping uniform conc=1e26 n.type direction=x regions=1
doping uniform conc=1e23 p.type direction=x regions=2
doping uniform conc=1e23 p.type direction=x regions=3
doping uniform conc=1e26 n.type direction=x regions=5
interface qf=3e10
model cvt srh arora fldmob srh boltzmann conmob analytic consrh print
method newton gummel
solve init
solve vfgate=0.01
solve vdrain=0.0

36

method gummel newton itlimit=10 trap atrap=0.1 maxtrap=4 autonrnrcriterion=0.1 \


tol.time=0.005 dt.min=1e-25
solve init
solve vdrain=0.01 vstep=.01 vfinal=0.05 name=gate
log outf=finfet_shubh.log
solve vgate=0 vstep=.05 vfinal=2.0 name=gate
outputband.paramcon.bandval.bande.mobilityex.velocity \
ey.velocitye.velocity
save outf=dg2_nm.str
tonyplot dg2_nm.log
solve vdrain=1.0
save outf=vdd1
solve vdrain=0.1
save outf=vdd2
load infile=vdd1
log outfile=a_vdd1.log
solve name=fgate Vfgate=0 Vfinal=1.0 Vstep=0.05

load infile=vdd2
log outfile=a_vdd2.log
solve name=fgate Vgate=0 Vfinal=1.0 Vstep=0.05
tonyplot -overlay a_vdd1.log a_vdd2.log
#-set gpfinfet_vdd.set
#
solve init
log outfile=a-ac-1.log master
solve name=fgate vfgate=0 vstep=0.05 vfinal=1.0 vdrain=0.1 ac freq=1.0e6 previous
log off
solve init
log outfile=a-ac-2.log master
solve name=fgate vfate=0 vstep=0.05 vfinal=1.0 vdrain=1 ac freq=1.0e6 previous
tonyplot -overlay a-ac-1.log a-ac-2.log
######################################################
37

extract init inf="a_vdd2.log"


extract name="vt1"(xintercept(maxslope(curve(v."fgate",i."drain"))))
extract init inf="a_vdd1.log"
extract name="vt2"(xintercept(maxslope(curve(v."fgate",i."drain"))))
extract name="subvt"1.0/slope(maxslope(curve(abs(v."fgate"),log10(abs(i."drain")))))
extract name="sub"slope(maxslope(curve(abs(v."fgate"),log10(abs(i."drain")))))
extract name="gm"(slope(maxslope(curve(abs(v."fgate"),abs(i."drain")))))
extract name="Ion/Ioff"((max(abs(i."drain")))/(min(abs(i."drain"))))
extract name="Ion"max(abs(i."drain"))
extract name="Ioff"min(abs(i."drain"))
extract name="dibl" ($"vt2"-$"vt1")/(1.0-0.1)
########## Id Vs Vds ##############################
#
tonyplot dg2_nm.str
quit

7.4 2-D Structure generated by program:

Figure 7.1 2-d structure of Double Gate DM-FET.

38

CHAPTER 8
SIMULATION RESULTS AND DISCUSSIONS

39

8.1. Variation in parameters with respect to Concentration :


S

Parameters

Concentration (atoms /cm3)

Method

1*10

2*1019

8*1018

19

Threshold
voltage (V)

Maximum
slope

0.41

0.42079

0.41209

2755

gmVgs

0.43

0.44

0.45

0.06450

0.06363

82

54

Sub Threshold

0.06

voltage

3710

(V/decade)

Figure 8.1 Id-Vgs graph for different concentrations

8.2. Variations in parameters with respect to Fin length.


S

Parameters

Method

Fin length (nm)


40

n
o

15

20

25

Maximum

0.4076

0.41327

0.41597

slope

gmVgs

0.41

0.42

0.42

Threshold

0.0681

0.06371

0.06162

voltage

446

05

56

Threshold
voltage (V)
Sub

(V/decade)

Figure 8.2 Id-Vgs graph for different Fin lengths

8.3. Variations in parameters with respect to the Height of the fin.


Sn

Paramete

Method

Height of the fin (HFIN in nm)


8
41

10

12

o.

rs
Threshold

Maximu

voltage

m slope

(V)

gmVgs

0.41240

0.41275

0.41295

0.43

0.45

0.45

0.06400

0.06371

0.06200

83

05

83

Sub
Threshold
2

voltage
(V/decade
)

Figure 8.3 Id-Vgs graph for different Fin height

8.4. Variations in parameters with respect to the Fin width.


S

Parameters

Method

Fin width (TFIN in nm)

4
42

o
.
Maximu
1

0.41965

0.41327

0.4082

0.43

0.42

0.41

Threshold

0.05604

0.06371

0.0665

voltage

85

05

Threshold

m slope

voltage (V)

method
gmVgs

Sub
2

(V/decade)

Figure 8.4 Id-Vgs graph for different Fin widths

8.5. Variations in parameters with respect to the Oxide thickness.


S

Parameters

Method

Oxide thickness (TOX in nm)

43

1.5

Maximu

0.4185

0.41327

0.40817

m slope

gmVgs

0.45

0.44

0.45

Threshold

0.0619

0.06371

0.06557

voltage

36

05

99

Threshold
voltage (V)
Sub

(V/decade)

Figure 8.5 Id-Vgs graph for different oxide thickness

8.6. Variation in the parameters with respect to the Buried oxide thickness.
S

Parameters

Method

Buried oxide thickness (TOXB in nm)

5
44

20

50

Maximu

0.41327

0.4129

0.41293

m slope

36

gmVgs

0.45

0.42

0.44

Threshold

0.06371

0.0640

0.06401

voltage

05

19

85

Threshold
voltage (V)
Sub

(V/decade)

8.7 Variation in parameters with respect to underlap channel length


Underlap

Threshold

Sub-Threshold

Gm

Ion/Ioff

Ion

Length

Voltage

Slope

(A/V)

(108)

(A)

Ioff

DIBL

(A)

(mV/V)

(10 )

(10-13)

3.70

8.04

2.18

4.272

4.18

3.31

7.03

2.12

6.134

72.2921

3.59

2.57

1.76

0.68

10.376

0.395030

76.248

3.23

1.90

1.75

0.92

18.693

0.390608

77.5587

2.38

1.54

1.95

1.26

21.865

(nm)

(V)

(mV/decade)

(10-5)

0.410762

61.3157

4.30

0.401881

65.9921

0.401666

2
0

-5

The above table shows the variation of some important parameters required for determining
the short channel effects, like threshold voltage, sub-threshold swing, drain induced barrier
45

lowering, trans-conductance and Ion/Ioff ratio. These parameters values show qualitatively and
the performance of device at very short channel length. For, a double gate hetero structure
MOSFET device, the channel length to height ratio must be within a specific limit. This is
true for channel length to the width of fin ratio also. If there is a large deviation in the specific
ratios, the values like sub-threshold swing will begin to deviate much from the optimum and
may result in a value that is not regarded well from the device operation point of view.
The graphs on the next page, clearly demonstrates the variations in an easy to understand
way. Also, the threshold voltage is now affected by V DS. The vertical axis represents the
variation in subthreshold swing with respect to channel length. Mathematically,

(8.7.1)
where S is the sub threshold swing. At subthreshold voltages the current is mainly contributed
by the diffusion process, which is less significant at shorter length. As, the channel length
reduces the drain current is reduced for the same values of V gs. Hence, the curve for sub
threshold slope decreases at higher values of length.

threshold slope (mV/decade)

80

Length vs Sub-threshold slope

76

Underlap channel length (nm)

72
68
64
Sub
60
0

Fig.8.6 Variation in sub threshold slope with respect to channel length.

46

The graph below shows the variation of drain induced barrier lowering (DIBL) with respect to
the underlap channel length. Mathematically,
(8.7.2)
When we increase the underlap channel length the DIBL values decrease because of a
decrement in the

values. Vt1 is calculated at VDS equal to 1V, while Vt2 is calculated at VDS

equal to 0.1 V. For a larger channel length device, i.e devices having high underlap, the two
threshold voltages do not differ appreciably. That is why there is a decrement in the DIBL
values at higher underlap channel length.

25
20
15
DIBL (V/V)
Length vs DIBL

10

Underlap channel length (nm)

5
0
0

Fig.8.7 DIBL variation with channel length

47

in (A/V)
)
m

5.00E-05
4.50E-05
Length vs Trans-conductance

4.00E-05
3.50E-05

3.00E-05
Underlap channel length (nm)
Transconduct2.50E-05
ance (g)
2.00E-05

1.50E-05
1.00E-05
5.00E-06
0.00E+00
0

Fig. 8.8 Variation of Trans-conductance vs Length.

The above graphs represent the variation of another quantity, trans-conductance with respect
to channel length. While DIBL is a direct consequence of short channel and is pronounced for
channel length less than 20 nm, analysis of trans-conductance requires the understanding of
carrier transport in the device. At shorter channel, the drain voltage has a direct impact on the
threshold voltage of the device, because of the close proximity of drain terminal and the gate
terminal. On the vertical axis, trans-conductance variation is plotted. We know,
gm = Id/Vgs

(8.7.3)

Id increases rapidly at shorter channel length. Hence, the graph increases in value, as we
move along the right, i.e. towards longer channel. The reason being is at higher underlap
length the drain current increases more rapidly with respect to variation in gate voltage.
The graph on the next page demonstrates the variation of the ratio of on current to leakage
current (Ion/Ioff) with channel length variation. As can be predicted easily, the shorter the
48

channel, the more dominating the Ioff is. The sole reason behind the high values of I off is that it
is very difficult to control leakage current in short channel device, when the depletion width
at source and drain begin to interfere with each other. Hence, the ratio has lower values at
shorter channel length, than at longer channel, because the current in off state of the device is
negligible in longer channels. Thus, the noise immunity and static power dissipation is better
for longer channel length devices.

Length vs Ion/Ioff
0

4
6
Underlap channel length (nm)

4.00E+08
3.50E+08
3.00E+08
2.50E+08
2.00E+08
Ion/Iof

1.50E+08
1.00E+08
5.00E+07
0.00E+00

in mho
d

Fig. 8.9 Ion/Ioff variation with channel length


1.00E-02

49

Output conductance (g)

1.00E-03

1.00E-04

1.00E-05

1.00E-06

Fig 8.10 Variation of output trans-conductance with respect to VDS for different underlap length
(VGS=0.6V).

The above graph shows variation of output trans-conductance (g d) with respect to VDS for
different values of underlap channel length. We know,
(8.7.4)
In other words, gd is the reciprocal of output resistance. As we know the output resistance is
less in triode region or the sub threshold region, the value of g d is high when the VDS value is
less than the gate overdrive voltage (VGS-Vt). But as soon as VDS crosses the gate overdrive
voltage, gd starts to fall rapidly and in saturation region it becomes almost constant. Since the
output resistance is very high in the saturation region, g d is almost negligible. The device
performs better for higher underlap length as can be seen from the graph, g d tends to become
constant in the saturation region in those devices yielding a constant drain current in the
channel.

50

Fig 8.11 Variation in TGF with respect to VGS for different underlap length at VDS=1V

TGF (Trans-conductance generation factor) is one of the figures of merits over which a
device performance is judged. It is the ratio of trans-conductance over drain current for
different values of the gate to source voltage (VGS). Mathematically,
TGF = gm/Id

(8.7.5)

We cannot calculate TGF in subthreshold region, because the drain current in negligible in
that region. So once the VGS value crosses the threshold voltage the drain current begins to
flow in appreciable amount and hence the values are obtained. In our device the threshold
voltage is 0.4V, which is why the horizontal axis begins with 0.4V. The trans-conductance
generation factors ideal value is limited around 40V -1 for a subthreshold slope of 60
mv/decade. Thus, as evident from earlier graphs also, at higher underlap length the device
performance improves because of high TGF they offer which is very close to the ideal value
as soon as the inversion layer forms. The inversion layer forms when the gate voltage crosses
the threshold voltage, thus the maximum TGF values are obtained near the threshold voltage.

51

5
4.5
4

lun=0

lun=2

lun=4

lun=6

3.5
Early Voltage (VEA)
3

VGS(V)

2.5
2
1.5
0.4

0.5

0.6

0.7

0.8

0.9

Fig 8.12: Variation of Early Voltage (VEA) with VGS, for different underlap length at VDS=1V.

Early voltage VEA is the ratio of Id over gd at a constant VDS. Mathematically,


VEA= Id/gd

(8.7.6)

It is yet another figure of merit which helps compare device performance. Higher values of
early voltage are desirable. As can be seen from the I D vs VDS graph (Fig: 5.17) for lower
values of underlap length, the drain current is higher than the higher values of underlap
length. So a higher VEA should be expected at lower underlap length. But this does not happen
because an increase in Id value is much more compensated by a sharp decrease in g d values at
greater underlap length, thereby, improving device performance at higher underlap length.

52

3
2.5

Lun=0
Lun=2
Lun=4
Lun=6

2
Intrinsic gain (A
1.5

VGS(V)

0.5
0
0.4

0.5

0.6

0.7

0.8

0.9

Fig 8.13: Variation in Intrinsic gain (Av) with respect to VGS for different underlap length at VDS=1V.

The graph on the previous page shows the variation of Av, with respect to VGS for a constant
drain voltage of 1V. Av is a valuable figure of merit for trans-conductance amplifier.
Generally a MOSFET is modeled as a trans-conductance amplifier because in saturation
region it acts as a constant current source. This is because for whatever V DS values, the drain
current ID remains constant. This current source is voltage dependent as the value of I D solely
depends on the value of VGS. Thus to have an efficient comparison between two amplifiers we
find Av. Mathematically,
Av = gm/gd = gm*RD

(8.7.7)

where RD is the output resistance. For smaller underlap length, the gm values are smaller hence
the intrinsic gain is less. This again goes in the favour of longer underlap device as we want a
high value of intrinsic gain for a better amplification need.

The graph below shows the variation of cutoff frequency (f T) with respect to VGS for different
underlap length. Cutoff frequency is also known as the corner frequency or the break
frequency. It is that limit of the frequency response of the device beyond which energy
passing through it begins to attenuate. The most common and accepted value of the break
frequency for any device or circuit is the point where the gain of the device becomes half of
the gain offered by it at DC or in other words it is that limit when the gain is reduced by 3dB.
53

The fT determines the bandwidth of the device for which it can work as an amplifier with a
constant gain. Mathematically,
fT = gm/ 2

(8.7.8)

As it is evident again greater underlap length has higher bandwidth hence a good
performance at higher frequency.

Fig 8.14 Variation of fT with respect to VGS for different underlap length at VDS=1V

8.8 Variation of surface potential and electric field with respect to underlap channel
length
In single material gate MOSFET devices, when the gate electrode is made up of single metal,
the electric field has a peak value near the drain terminal. This means that the distribution of
electric field throughout the channel is not uniform. Thus, while the electrons near the drain
terminal accelerate more than the electrons near the source terminal. This leads to inefficiency
in the carrier transport, which is not desirable at all. Thus, to remove this inefficiency, it is
essential to use dual material gate wherein two different metals are used in gate electrode with
two different work functions. This leads to a uniform distribution of electric field inside the
channel and hence there is a significant increase in the efficiency of electrons going from
source to drain terminal. Further, the potential curve shows a unique shape when drawn along
the channel length. There is a trough in the graph as usual in almost middle of the channel,
but as expected, at the point of channel where the different gate material is used, the graph
shows constancy.

54

Fig 8.15 Variation of surface potential with channel length

Fig. 8.16 Variation of Electric field with respect to channel

The surface potential inside the channel varies when the channel length is varied, from the
lower limit of 20nm to the upper limit of 30 nm. As we can see, the min. value of surface
potential for the shorter device is more than the min. value of channel potential for the longer
device. Also, these curves have been plotted at zero bias (VDS=0V). Thus, ideally the potential

55

at the middle should have been zero. But, there is some residual voltage still left in the
channel.
8.9 Drain current vs gate voltage variation

Fig. 8.17 ID vs VGS variation for two different values of VDS

The graph shows the variation in drain current vs variation in gate voltage at two different
values of drain voltage. When the VGS value is well below the threshold value, I D is zero
(negligible). When the gate voltage crosses the threshold voltage there is an exponential
increase in the current. The sudden transition from almost zero value on state value of the
drain current is well explained by the logarithmic curve, which shows a steep slope in the
subthreshold region, and then a linear (almost constant slope) in the on state, (when the
current dependence on the gate voltage becomes exponential). As we can see, there is a
change in slope of logarithmic curve at different values of VDS. The variation in the slope of
logarithmic curve in subthreshold region is a very good example of drain induced barrier
lowering in short channel devices.

56

8.10 Drain current vs drain voltage variation

Fig. 8.18 ID vs VDS graph at two different underlap length.

The graph above shows the variation of drain current with respect to the drain voltage. It can
be seen clearly that for the underlap length equal to 0nm there is a visible slope in the graph
even in the saturation region. Thus, the output resistance is not infinite but has some value.
This is not desirable as in saturation region we need infinite output resistance. However for
underlap channel length equal to 8 nm the output resistance in the saturation region becomes
almost infinite. Hence, we can see, the performance of the device improves when the
underlap length increases.

57

58

CHAPTER 9
CONCLUSIONS AND FUTURE SCOPE

59

Fin-FETS promise to alleviate problematic performance versus power tradeoffs. Designers


can run the transistors faster and use the same amount of power, compared to the planar
equivalent, or run them at the same performance using less power. This enables design teams
to balance throughput, performance and power to match the needs of each application.
Leading foundries estimate the additional processing cost of devices to be 2% to 5% higher
than that of the corresponding Planar wafer fabrication of MOSFETS. Fin-FETS are
estimated to be up to 37% faster while using less than half the dynamic power or cut static
leakage current by as much as 90%.
The foundries want to make the transition to FINFETs processes as transparent and smooth as
possible for the design community. In order to do that, industries need to work behind the
scenes to ensure that the tools understand and model the complexities involved. Design teams
want to take advantage of the power, performance and area benefits that triple gate FINFETs
offer while still getting to market quickly and painlessly through a familiar process of
creating the RTL and taking it through a backend implementation process.
In order to continue on the path of Moores Law designers must be able to leverage the
target technology for maximum benefit, and invariably, that means focusing on the details.
By minimizing the size of FINFETs we get these result:
1) Reduce size of chip.
2) Reduce switch time of Fin-FETs.
3) Reduce power consumption.
4) Increased no. of transistors (Moores law).
5) Reducing the Vth in Fin-FETs.
6) Reducing fringing capacitance.
7) Increase Circuit Operation Speed
As we can see, a further reduction in the channel length of MOSFET, is not possible, but the
demand of industry for still shorter devices continues to be there. Thus, the
Fin-FETs will be the new choice of the industry as it provides feasible solutions to the
problems of MOSFETs. Our aim is to find an optimized device which can perform better in
high frequency operations as well as free from the demerits of SCE. This newer device will
find extensive applications in microwave domain where the traditional devices fail to operate
satisfactorily. They can be used in microwave oscillator and amplifier circuits as well.
60

The nano-electronics industry is facing historical challenges to scale down CMOS devices to
meet demands for low voltage, low power, high performance and increased functionality.
Using new materials and devices architectures is necessary. High gate dielectrics and metal
gates have been introduced and have shown their ability to reduce power consumption. Fully
depleted ultra-thin SOI devices are a good alternative to bulk for low power applications.
Multi gate and Amended Channel devices are the current goal in device architecture to
increase Fin-FET drivability, reduce power, and allow new opportunities for future
applications. Thin film based solutions will be necessary in the future because of fundamental
limitations on gate capacitance scaling and system integration requirements. Exploiting 3D
device stacking via wafer bonding could be a good way to introduce new materials (High
Dielectric constant, strained Si, and hybrid orientation) increasing integration density. Si
based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.
This is why thin films based architectures, such as FDSOI, multi gate and multi nanowires
that offer the opportunity to maximize system performance versus leakage current figures of
merit have been developed. These architectures will pave the way to new scaling routes,
which will reduce the demands on gate insulator scaling, which is subject to fundamental
limitations. Development by major nano-electronics laboratories and companies is ongoing
worldwide. In the future, because of the advancements in thin film technologies and wafer
bonding, new materials (IV column or III-V compounds) will be introduced in 3D integration
schemes based on the silicon CMOS platform. This will allow for an increase in performance
as well as a reduction in power consumption.

61

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