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Outline
Low noise amplifier overview
Tuned LNA design methodology
Tuned LNA frequency scaling and porting
Broadband low noise amplifier design methodology
Design goal
Minimize the noise of the amplifier for a given signal
source impedance to approach transistor minimum
noise figure/factor NFMIN/FMIN
Rn
2
F=FMIN YsYsopt
Gs
Design philosophy
Take advantage of what silicon does best: transistors.
Use Si passives only sparingly:
Q is fairly low and undermines overall noise figure
Inductors are (significantly) larger than transistors,
hence expensive.
Make transistor sizing part of the noise matching step.
Use only reactive (loss-less) feedback or minimize the
noise contribution of resistive feedback components.
Avoid active loads if at all possible.
F MIN W f
=0
W f
F 50 N f
=0
N f
Z0
1/NfOPTor 1/lEOPT
1/Nf (1/lE)
F5 0 N f
N f
F5 0 lE
l E
=0
=0
10
R N , FET
Nf N
Gu =G N , FET 2 N f N
B cor =B FET N f N
Gcor =G C , FET N f N
Y sopt = G cor
Zsopt FET
Gu
jBcor =N N f W f
Rn
f Teff
NNfW ffg 'meff
N N f=
GC , FET
GFET
j B FET
R FET
f Teff
Z 0W f fg ' meff
R HBT
N lE
Gu =G HBT 2 N l E
B cor =B HBT N l E
Gcor =G C , HBT N l E
Y sopt = G cor
Zsopt HBT
N lE=
Gu
jB cor =N l E
Rn
f Teff
'
fNlEg meff
f Teff
Z0fg'meff
G C , HBT
'
G HBT
j B HBT
RHBT
gm '
'
r ER b j = Z0 j X sopt
2
g'm '
r ER'b
2
12
Z 0 Rs Rg
T cascode
L S=
Z 0 Rb r E
T cascode
fT
Z IN =T L SRg Rs j L SL G
f gm
fT
Z IN = T L SRb r Ej L SL G
f gm
V
L
V
LG=
2 f gm
L S
=Z
in
DD
IN
o
Z =Z
2
f
1 T RP
G
4 f 2 Z0
SOPT
fT
DD
13
OUT
RS=nZ 0 ;
M1
Z0
2
2
0
LBW
2
PAD
1 L BW CPAD Z C
VIN
ZO
X s =j
2
0 PAD
2 2
0 PAD
[L BW 1 L BW CPAD Z C
Cpad
CS
RS
1 2 L BW CPAD 2 Z C
Without bondwire
Z0
RS=
k
Z0
CPAD Z 20
Z S= j
k
k
k =12 C2PAD Z 20
14
VIN
M2
Csb2 +Cgs2
LM1
M1
Cdb1 +Cgd1
gm1
f T cascode=
2 Cgs1 2 Cgd1
LM1 forms artificial t-line with parasitics of M1 and M2
An optimal LM1 exists that maximized fT.
LM1 ~ W 1-1
Both the gain and the noise figure are improved
15
VDD
CD
C1
VOUT
VBIAS
M
C2
CD
LD
LM
VIN
M
LG
CPAD
LS
16
CPAD
3.58*2
/0.2um
LB = 90 pH
RFIN
LE= 60 pH
RFOUT-DIFF
RC2 =1 k
C C= 23 fF
4.52*2
/0.2um
LPRI/SEC= 160 pH
3.58*2
/0.2um
3.58*2
/0.2um
LE2 = 60 pH
JC1= 4.2 mA
JC2= 6.7 mA
370 m
480 m
17
VT
VDS
Ac-coupled cascode, 1V operation in GP CMOS, insensitive to VT, yet:
2x the DC current
2nd resonant tank reduces bandwidth,
extra lossy inductor and MIM cap => higher loss, larger area
18
21
VD D
LD 1
LD 1
VO U T -
LD 1
VO U T +
VO U T
VD D
Q3,4
V+IN
LG 1
VD D
BIAS
L G 1 V_
IN
VIN
Q1,2
Q3
LG 1
Q1
LS 1
LS 1
LSS2
BIAS
22
23
24
25
26
130nm
90nm
N F' = N F /
W ' = W /
27
L'G = LG /
L S=
LG =
C IN
Z 0 R g R s
2 f T
L S
28
Experimental results
LNA
Nf
Wf
um
IDS
mA
VDD
[V]
14 GHz, 90-nm
90 1
13.5 1.5
128
1100 545 -
145 70
20
28 GHz, 90-nm
45 1
6.75 1.5
128
535
235 -
75
59
20
60 GHz, 90-nm
20 1
55
190
140 190 30
20
1.5
LS
LG
[pH] [pH]
LD
pH
LM
pH
C1
C2
CPAD
[fF] [fF] [fF]
12 GHz, 130-nm 90 1
13.5 1.8
177
1340 492 -
122 135 60
24 GHz, 130-nm 45 1
6.75 1.8
177
718
80
251 -
58
60
29
30
130nm
90nm
Unchanged: ZO P T is
Wf
W 'f=
S
invariant between
N ' f = N f S
technology nodes
W' =W
31
L S=
Z 0 Rg Rs
2 fT
32
Gain and NF
improve with
scaling
33
RP
CD
LD
VOUT
VDD
VIN
Solutions
Current re-use with CMOS inverter (doubles
VDD but still saves power
Don't noise match, just bias at Jopt
LG
C1
LS
fT
fT
C1
1
Cgs2 Cg d
C1
L S L S 1
Cgs2 Cg d
34
VIN
M1
ZO
CPAD
VIN
LG + LS CIN
iin
ZO
ZS
ZIN
Z*SOPT
CPAD
LS
ZS
VIN
ZIN
LG + LS
CIN
iin
ZO
CPAD
ZS
Z*SOPT
RSOPT = Rg+Rs + k2
f Teff
f gmeff
35
VIN
Q1
YIN
nP> nS
Y*SOPT
YS
T1
LP
iin
GO
LS
CPAD+ CIN
YS
YIN
GIN gmeff
LP
M
LP
VIN
iin
GO
CPAD+ CIN
YS
Y*SOPT
GSOPT
36
gmeff f
k2 f Teff
50pH
50pH
80pH
20um
20um
140pH
140pH
20um
..
70pH
30um
20um
105fF
128fF
30um
40um
40pH
60pH
60pH
30um
30um
40um
128fF
63fF
35pH
37
LD
vIN
VDD
VDD
VDD
M1
RD
vOUT
vOUT
RB
vOUT
M1
M1
vIN
-A
-A
LS
ii n
M2
M3
VG
38
39
Back-up slides
40
41
42
use average initial size lE=5 m and 2 emitter, 3base, 2col. HBT
fT
Jopt
44
Jopt
45
46
LE=
ZORbRE
2 f Tcascode
47
L B
1
j C in
1
L E
2
C in
ZSOPT=ZO
ZIN=ZO
48
49
2
f
1 T RP
G 2
4 f Z in
50