GATE-DIFFUSION INPUT (GDI) - A TECHNIQUE FOR LOW POWER DESIGN OF

DIGITAL CIRCUITS: ANALYSIS AND CHARACTERIZATION

Arkadiy Morgenshtein, Alexander Fish2 and Israel A. Wagner

1. Bio-Medical Engineering Department, Technion, Haifa, Israel, E-mail : arkadiy@tx.tcchnion.ac.il
2. Electrical Engineering Department, Ben-Gurion University, Beer-Sheva, Isracl, E-mail : afish@cc.bgu.ac.il
3. IBM Haifa Labs, Haifa, Israel, E-mail : wagner@il.ibm.com

ABSTRACT
GDI (Gate Diffusion Input) - a new technique of low power
digital circuit design is described. This technique allows reducing
power consumption, delay and area of digital circuits, while
maintaining low complexity of logic design. Performance
comparison with traditional CMOS and various PTL design
techniques is presented, with respect to the layout area, number of
devices, delay and power dissipation, showing advantages and
drawbacks of GDI as compared to other methods. A variety of
logic gates have been implemented in 0.35pm technology to
compare the GDI technique with CMOS and PTL. A prototype test
chip of 8-bit CLA Adder has been fabricated, based on GDI and
CMOS cell libraries , showing up to 45% reduction in power-delay
product in GDI. Properties of implemented circuits are discussed,
simulation results are reported and measurements of a test chip are
presented.

I.

INTRODUCTION

With rapid development of portable digital applications, the

demand for increasing speed, compact implementation and low
power dissipation triggers numerous research efforts [ 1,2]. The
wish to improve the performance of logic circuits, once based on
traditional CMOS technology, results in developing of many logic
design techniques during the last two decades. One form of logic
that is popular in low-power digital circuits is pass-transistor logic
(PTL).
Formal methods for deriving pass-transistor logic have been
presented for nMOS. They are based on the model, where a set of
control signals is applied to the gates of n-transistors. Another set
of data signals are applied to the sources of the n-transistors [I].
Many PTL circuit implementations have been proposed in the
literature [ I ,2,3,4,7].
Some of the main advantages of PTL over standard CMOS
design are: (1) High speed - due to the small node capacitances, (2)
Low power dissipation - as a result of the reduced number of
transistors, (3) Lower interconnection effects [5,6] - due to a small
area.
However, most of the PTL implementations have two basic
problems. First, the threshold drop across the single-channel pass
transistors results in reduced current drive and hence slower
operation at reduced supply voltages; this is particularly important
for low power design since it is desirable to operate at the lowest
possible voltage level. Second, since the high input voltage level

0-7803-7448-7/02/$17.00 02002 IEEE

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at the regcncrative inverters is not Vdd, the PMOS dcvicc in the

inverter is not fully tumcd off, and hence dircct-path static power
dissipation could be significant [ 3 ] .
An additional problem of existing PTL is top-down logic dcsign
complexity, which prevents from the pass-transistors capturing a
major role in real logic LSls. One of the main reasons for this is
that no simple and universal cell library is available for PTL based
design.
GDI (Gate Diffusion Input technique) - a new low powcr dcsign
technique, which allows solving most of the problems mcntioncd
above was presented in [9]. GDI approach allows implcmcntation
of a wide range of complex logic functions using only two
transistors. This method is suitable for design of fast, low power
circuits, using reduced number of transistors (as compared to
CMOS and existing PTL techniques), while improving powcr
characteristics and allowing simple Shannons theorem-bascd
design [9] by using small cell library.
The aim of this work is to analyze the GDI technique by
implementation of logic gates and comparing their properties with
their analogues in CMOS and PTL. A variety of logic gates have
been implemented in 0.35pm technology and results of the
comparison are presented. In order to prove the practical
applicability of GDI and display its properties, the prototype test
chip of 8-bit CLA Adder has been fabricated in 1.6pm technology,
based on GDI and CMOS cell libraries.
Section I1 presents a review of basic GDI functions and their
circuit principle. In Section 111 an operation analysis of GDI cell is
presented. Section IV shows the comparisons of various leaf cells
in GDI vs. CMOS and PTL. Section V presents measurements of a
test chip, fabricated in GDI and CMOS. Conclusions and future
work are discussed in Section VI.

11.

BASIC GDI FUNCTIONS

GDI method is based on the use of a simple cell as shown in Fig

1. At a first glance the basic cell reminds the standard CMOS
inverter, but there are some important differences: GDI cell
contains 3 inputs - G (common gate input of nMOS and PMOS), P
(input to the source/drain of PMOS) and N (input to the
source/drain of nMOS). It must be remarked, that not all the
functions are possible in standard p-well CMOS process, but can be
successfully implemented in twin-well CMOS or SO1 technologies.
This issue will be discussed in Section VI.
Table 1 shows how a simple change of the input configuration of
the simple GDI cell corresponds to very different Boolean
functions.

P
Q

VDD

Table 2. Input logic states vs.functionality and output swing oj'F1

function.

Fig I . GDI basic cell

Most of these functions are complex (6-12 transistors) in

CMOS, as well as in standard PTL implementations, but very
simple (only 2 transistors per function) in GDI design method.
The 8-bit CLA Adder presented in Sec. V was based on the F1
function. The reasons for this are as follows: (1) F1 is a complete
logic family (allows realization of any possible 2-input logic
function), (2) FI is the only GDI function that can be realized in a
standard p-well CMOS process, because the bulk of any nMOS is
constantly and equally biased.
As can be seen, GDI cell structure is different from the existing
PTL techniques, and has some important features, which allows
improvements in design complexity level, transistor count, static
power dissipation and logic level swing (all of these will be
discussed in Sections IV - V). Understanding of GDI cell
properties demands a deeper operational analysis of the basic cell
in different cases and configurations.

VDD

CMOSInverter
nMOS Trans Gate
CMOSInverier

out

Function

level of F1 is VTp (instead of expected OV) because of poor highto-low transition characteristics of PMOS pass-transistor [4].It is
obvious that the only case (among all the possible transitia'ns)
where the effect occurs is the transition from the A=O, B=VDD to
A=O, B=O.
The fact that demands a special emphasis is that in about 50%; of
the cases (for B=l) the GDI cell operates as a regular CMOS
inverter, which is widely used as a digital buffer for logic level
restoration. In some of these cases, when VDD='1' without a swing
drop from the previous stages, a GDI cell functions as an inverter
buffer and recovers the voltage swing. Although this feature
allows a self-swing restoration in certain cases, in this paper the
worst-case is assumed and additional circuitry is used for swing
restoration in the implemented circuits.
An additional analysis of transient response, swing-restore
buffering and switching characteristics is presented in [8]. It can be
shown from this analysis, that the delay of CMOS gate compared
to GDI gate with same b c t i o n a l complexity is given by:

where the high bound is for high output capacitive load and $the
low bound is for low output capacitance.

'0'

'1'

NOT

IV.

Table 1. Various logic functions of GDI cell for different input

configurations

111.

OPERATIONAL ANALYSIS OF GDI

CIRCUITS

As mentioned in Section 1, one of the common problems of

PTL design methods is the low swing of output signals because of
the threshold drop across the single-channel pass transistors. In
existing PTL techniques additional buffering circuitry is used to
overcome this problem.
In order to understand the effects of low swing problem in GDI
cell, we suggest the following analysis, based on the example of
F1 function, and can be easily extended to use in other GDI
functions. Table 2 presents a full set of logic states and related
finctionality modes of F 1.
As can be seen from Table 2, the only state where low swing
occurs in the output value is A=O, B=O. In this case the voltage

I - 478

COMPARISONS WITH OTHER LOGIC

STYLES

In this work a variety of logic gates have been implemented in

0.35pm technology to compare the GDI technique with CMOS and
PTL. Five sets of comparisons were carried out on different logic
gates. Circuits were designed at the transistor-level in a 0.35 pm
twin-well CMOS process technology (VTN=0.56V,
VTW0.65V). The circuits were simulated using Cadence Spectre at
3.3V, 40 Mhz and 27'C, with load capacitance of 100 fF.In our
simulations the well capacitance and other parasitic parameters
were taken into account. Each set includes a logic cell
implemented in four different techniques: GDI, CMOS,
Transmission Gate and n-MOS Pass Gate. Cells were designed ifor
a minimal number of transistors. Several examples of logic gates
in each technique are shown in Table 3, while in n-MOS Pass Gate
cells a buffer was added, because of low swing of output voltage.
Most circuits were implemented with W/L ratio of 3, to achieve
the best power-delay performance. Same transitions of logic values
were supplied to the inputs of the test circuits in each technique.
Measured values apply to transitions in inputs connected to gate of
transistors, in order to achieve a consistent comparison.

9
CMOS
TG
N-PG
-

2 transistors
OR

6 transistors

$$
!........i

4 transistors

ouf
OUf

vdd

2 transistors

AND
F1
F2

6 transistors

AB
AB
A+B

6 transistors

25.7
31.2
32.0

0.9
0.8
1.3

8
8
8

34.1
45.2
43.1

6 transistors

1.4
1.5
1.9

12
12
12

30.8
31.8
33.2

0.8
1.1
1.4

4 transistors

16
16
16

30.1
31.8
29.6

2.8
2.5
3.5

16
16
16

Table 4. Logic gates comparisons (GDI, CMOS, Transmission Gate and n-MOS Pass Gate). Two cells and buffers are taken info account in

each number of transistors.

Measurements were performed on test circuits that were placed
between two blocks, which contain circuits similar to the device
under test. This allows more realistic environment conditions for
test circuit, instead of the ideal input transitions of simulators
voltage sources.
In order to perform a fair comparison between the techniques, the
measurements were carried out from cells series with buffers and
not from a single cell. GDI and TG test circuits contain 2 basic cells
with one output buffer. N-PG contains two buffers - one after each
cell. CMOS has no buffers in test circuits.
As can be seen from Table 4, among the presented design
techniques, GDI proves to have the best performance values and
lowest transistor count. Even in the cases, where power or delay
parameters of some GDI gates are inferior, as compared to TG or
N-PG, the power-delay products and transistor count of GDI are
lower. The TG design method can be an alternative for GDI in
some functions, if high frequency operation is of concern. It
should be noticed that the results of CMOS delays compared to
GDI, in most cases are bounded according to expression (l), as
expected.

V. MEASUREMENTS OF A TEST CHIP

A prototype chip of a widely used 8-bit CLA Adder [ l ]
designed in GDI and CMOS (Fig. 2) was fabricated in 1.6pm

I - 479

Fig. 2. Microphotograph of &bit Adder test chip.

CMOS technology (MOSIS). The design was based on GDI and

CMOS cell libraries for p-well CMOS technology [8].
Several sets of measurements and tests where applied on test
chips, using EXCELL 100+ testing system of IMS. Each set
included over 20,000 random transitions, which were used in delay
and power measurements. The GDI Adder contains 366 transistors
and its area is 0.375 m m 2 , while CMOS Adder has 392
transistors and 0.33 m m 2 . Because of the use of limited GDI

Table 5. Measured delays andpower dissipation of GDI and CMOS 8-bit Adders,

cell library in p-well CMOS process, the number of transistors and

area of CMOS and GDI circuits are close.
Delay Measurements: The maximal delay of both circuits was
measured by increasing the frequency of input signal and checking
the results of addition. The frequency, in which the first error
appears, defines the delay of the circuit. Table 5 presents the
results of delay in GDI and CMOS adders for various voltage
supply levels.
It can be noticed that for the given implementation and the
output load, defined by the testing system, both circuits have equal
delays.
Dynamic Power Measurements: Final results of dynamic power
dissipation are also shown in Table 5. Dynamic power
measurements were performed for various frequencies,
respectively to the voltage supply level. For 5V supply, the
measurements were performed at 12.5 MHz, for 4.5V - at 10
MHz, and for the rest of the values - at 4 MHz.
Power-Delay Product: Due to equal delay values in both circuits,
the normalized power-delay product has about the same values as
those of power measurements. For power and power-delay
product, improvements in the range of 11% - 45% were measured
in GDI.

VI.

CONCLUSIONS AND FUTURE RESEARCH

Different implementations of a novel Gate-Diffusion Input

(GDI) technique for low-power design were presented. An 8-bit

CLA Adder was fabricated using GDI and CMOS, and used as a
test vehicle. Measurements, as well as simulation comparisons
with existing PTL and CMOS techniques were camed out, as
described in this paper and elsewhere [SI, showing an up to 45%
reduction of power-delay product in the test chip in GDI over
CMOS, and significant improvements in performance, as well as
decreased number of transistors in GDI circuit over CMOS and
PTL.
The device under test was implemented in regular p-well CMOS
processes, which casts a limitation on a GDI cell library. Still,
even in limited-library based GDI circuits, significant
improvements of performance are observed. Implementations of
GDI circuits in SO1 or twin-well CMOS processes are expected to
supply more power-delay efficient design, due to the use of a
complete cell library with reduced transistor count.
The advantages of GDI technique, namely Shannon-based
design algorithm [9], 2-transistors implementation of complex
logic functions and in-cell swing restoration under certain
operating conditions are unique within existing low-power design
techniques. This, together with positive measurement and
simulation results, provide an evidence that GDI design might
enrich the toolbox of VLSI circuit designers.

I - 480

We hope that the presented results will encourage further

research activities on GDI technique. The issue of sequential logic
design with GDI is currently being explored, as well as technoloiy
compatibility for twin-well CMOS process. More work w,w
recently done in automation of a logic design methodology based
on GDI cells.

ACKNOWLEDGMENTS
The authors would like to thank Professor E.G. Friedman for his
constructive comments and suggestions. We would also like to
thank G. Samuel and the staff of Technion Research Center of
Microelectronic Systems, for their support during the research. We
finally thank M. Feldman, A. Panush and other students for
participating in projects in different stages of the research.

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