Documentos de Académico
Documentos de Profesional
Documentos de Cultura
Proceedings of ICRMET-2016
Mrs. G.Jyothi
Dr. M Z Kurian
Dept. of ECE
Sri Siddhartha Institute of Technology
Tumkur Karnataka, India
grandhejyothi@gmail.com
I. INTRODUCTION
A delay-locked loop (DLL) and a phase-locked loop (PLL) are
similar, but unlike PLL, DLL does not have internal voltage
controlled oscillator. The clock rise-to-data output valid timing
characteristic is enhanced by such DLL. DLL also is used for
clock recovery (CDR). A DLL is a negative delay gate placed
in the clock path of a digital circuit. The main key block is a
delay chain. It provides high-bandwidth data transmission rates
in between devices. DLL transmissions dont have low clock
skew for output clock signals, propagation delay and advanced
clock domain control. This DLL fed by a reference clock. DLL
determines the period of that reference clock by adjusting a
feedback loop via the delay line. The loop is locked as the
delayed clock signal matches the incoming clock signal. Clock
skew can not only further increase system clock frequency but
also avoid system malfunction. Phase-locked loops and delaylocked loops have been widely used to overcome the clockskew problem. These kinds of circuits are called clock-decked
buffers. A DLL has a phase detector (PD) or a phase comparator
(PC), a variable delay line, and a shift register for its operation,
to convert the PDs output signal to a control signal for the
delay line chain. Delay is produced using different driving
circuits that use different power efficient flip flops. Proposed
technic uses Low Power Forced Stack Clocked Pass Transistor
flip-flop (LP-FSCPTFF), that uses less power and lesser delay
time than that of conventional dual edge triggered flip flops.
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IAETSD 2016
ISBN-13: 978-1535448697
Proceedings of ICRMET-2016
CONVENTIONAL NAND DCDL USING DOUBLE
CLOCKED SENSE AMPLIFIER BASED FLIP-FLOP.
The driving circuit that is used in conventional DCDL is the
double clocked flip-flop. It is one among the special flip-flops
which use two different clock signal sources, so that it could
provide two different delays for LH as well as HL transitions.
One among these clock signals is CLH. I.e., Clock signal will
rise when there is low to high transitions. And the other one is
CHL. I.e., Clock signal will fall for high to low transitions. But
this too has disadvantages such as high power consumption and
higher delay time. This special sense amplifier based flip-flop
will have sense amplifier in the first and set-reset (SR) latch in
the next stage respectively. That conventional flip-flop tha is
used is shown in the Figure-4. on the clock rising edges the
sensing stage captures input state and a latch stage provides the
two flip-flop outputs that are detailed in the Figure and can be
analyzed using SR latch that is NAND based or more structures
that are advanced.
Figure-2. Multiple glitches forb the control code increased by two or more.
The values of Si and Ti, and the delay element states that cause
these values are shown in the Table-1.
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IAETSD 2016
ISBN-13: 978-1535448697
Proceedings of ICRMET-2016
Figure 6 : Low Power Forced Stack Clocked Pass Transistor flip-flop (LPFSCPTFF)
Figure 5: Proposed NAND based DCDL using Low Power Forced Stack
Clocked Pass Transistor flip-flop (LP-FSCPTFF)
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ISBN-13: 978-1535448697
Proceedings of ICRMET-2016
Above plot of power consumption vs supply voltage shows the
power consumption of various low power efficient low power
flip flops like Conditional Discharge Flip Flop (CDFF),
Conditional Data Mapping Flip Flop (CDMFF), Clock Pair
Shared Flip Flop (CPSFF), Low Power Clocked Pass Transistor
Flip Flop (LPCPTFF), Low Power Forced Stack Clocked Pass
Transistor Flip Flop (LPFSCPTFF). CDFF consumes less
power at 1.7v supply, where in CDMFF power reduction is seen
which is reduced by about 80% at 500 MHz. CPSFF
overshadows this CDMFF by showing reduced power upto
50%. Compared to all other power efficient D Flip Flops the
proposed LPFSCPTFF consumes the least power which is
reduced upto 90%. Simulation is done in Tanner EDA tool 13.0.
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