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Question bank

Module 1
1

State various short channel effects and explain one of them.

Jun15

With the help of neat cross sections and appropriate masks, give the
process flow of N-well CMOS technology.

Jun15

Explain level 1 and level 2 MOSFET model used in circuit simulator

Dec15

How low power circuit is designed through voltage scaling.

Dec15

Explain hot carrier effect in short channel MOSFET.

Dec15

What are different types of MOSFET scaling. Explain advantages and


disadvantages of each using appropriate equations.

Dec15

Dec13

Module 2
1

Draw layout of 2 input CMOS NOR gate using lambda rules

Jun15

Explain various sources of power dissipation in CMOS inverter

Jun15

Draw static CMOS NAND and NOR gates. Size all transistors in
NAND and NOR gate to provide worst case equal rise and fall delay
for both gates. Assume mobility of electron is two times higher than
that of holes. Magnitude of threshold voltage for all transistors is same.

Jun15

Jun15

Jun15

In 2 input CMOS NAND gate all PMOS transistors have (W/L)p=20


and all NMOS transistors have (W/L)n=10. Draw its equivalent CMOS
inverter and find size of PMOS and NMOS transistor in the equivalent
inverter circuit.

Dec15

Compare resistive load inverter, saturated load inverter and CMOS


inverter on the basis of noise margins, power dissipation, area and
delay.

Dec15

Draw 2 input CMOS NOR gate and using equivalent inverter approach
and derive expression for VIL,VIH,VOL and VOH.

Dec15

Dec13

10

Dec13

11

Dec13

Module 3:
1 Implement master slave D flip flop using C2MOS logic style

Jun15

Jun15

Jun15

4 What are advantages & disadvantages of dynamic logic circuit.

Dec15

5 Design clocked D-FF and implement using standard CMOS logic style.

Dec15

6 Implement y= (A(D+E)+BC) using


I. Static CMOS style
Ii. Pseudo NMOS logic style
III. Dynamic logic style
IV. Transmission gate logic

Dec15

7 Short note: C2MOS logic style


II. 1-bit shift register

Dec15

8 Discuss the concept of charge sharing and how it affects reliability of


integrated circuit.

Dec12

9 Discuss dynamic CMOS logic. Compare it with static CMOS logic.


What is primary drawback of dynamic CMOS logic. Show the
modifications in dynamic CMOS logic to overcome its drawback.

Dec12

Module 5
1 Explain 4*4 bit array multiplier with the help of necessary hardware for
the generation and addition of partial product.

Jun15
Dec15

2 Short note: carry look ahead adder

Jun15

3 Short note: barrel shifter

Dec15
Jun15
Dec12

4 Show the implementation of four bit carry look ahead adder along with
all equations.
5 Draw and explain manchester carry out circuit using carry kill bit. Also
draw k-input dynamic manchester carry chain.

Module 4
1 Implement NOR based 2:4 decoder.

Jun15

Jun15

3 Short note: flash memory

Jun15

4 Why sense amplifier is used in memory circuit. Explain its working.

Dec15

5 Draw layout of 6 transistor CMOS SRAM using lambda rule.

Dec15

6 Short note: 3T-DRAM cell

Dec15

7 Draw schematic for 6T SRAM cell and explain its stability criteria

Module 6
1 With the help of suitable diagrams explain how clock is generated and
stabilized in VLSI chip.

Jun15

2 Explain with help of neat diagrams importance of power distribution


network in VLSI chip.

Jun15

3 Short note: ESD protection circuit

Jun15

4 Short note: Interconnect scaling

Jun15

5 Why ESD protection is required for CMOS chips. Explain various


techniques of ESD protection.

Dec15

6 Short note: clock distribution in VLSI system.

Dec15

7 Draw and explain clock generation and stabilization network. And explain
how this clock is distributed in an integrated circuit.

Dec12