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#10: Do not lay the transistors out as they are placed in the schematics
Quite often you stare a little bit too much on the schematics when you do your layout. A
classical example is a cascade of differential amplifiers. In the schematics you typically
have your differential pair, active load, etc., in each sub-amplifier. You lay out according
to the schematics and you put your input terminals to the left and your output terminals to
the right. Then you start hooking the cascaded stages up and there it starts to get
messed up. You start to cross wires back-and-forth to fit the input to output terminals. It is
much better to rotate the amplifier 90 degrees and then put the input terminals to the left
and outputs to the right. Then you can more or less put the stages adjacent and
automatically hook up.
There are more things like this spend some more time on what you actually have in the
schematics and do not follow it too much in detail (from a placement point of view).
#9: Matching
Matching is very important we all know that. Any small variations in transistor sizes
might give you large variations in terms of voltage or current dependent on gain and
architecture. So, essentially, this bullet is stating the obvious do not forget to match
your circuit. The question though is how should you match? We have those well-known
interdigitized and common-centroid approaches, where one interleaves in one or two
dimensions in order to spread out the statistical variation to more than one transistor.
However, what about these things:
o avoid metal on top of the gate
o orient all transistors (that should be matched) such that the current flows in the
same physical direction
o proximity effects, i.e., the edges should also match
o shallow trench isolation, i.e., do not put the combined active area edges to far
from the gates (that is, do not place the transistors in too large islands)
o and much, much more.
o You need to do a metal mask change i.e., a bug is detected in your design once
chip is back in bench and you need to hook up an additional inverter or so
somewhere. To save money, you just want to change the (upper) metal layers on
your wafer. However, if the spare inverter is not there to begin with you need to
pay quite a few extra k$.
o Five hours before tape-out you realize you want some more driving capability in
one of your amplifiers, just a little bit of extra current. Unfortunately, since you
have done a dense design, adding that extra transistors forces you to do a
substantial redesign of your layout.
o There is a misunderstanding between PNR/RTL and analog macro and you need
to do some digital encoding for some control wires. Running an ECO on the
digital core takes too much time and you have to do a manual, digital place-androute inside the analog macro.
For all of these cases it would be very nice to have extra circuitry already at hand in your
layout. Remember that normally you are not really doing the most dense layouts in the
market. Especially for the first test runs this is not the case, area and cost optimization
follows later on. First, it is about time-to-market, and to be able to do quick changes to
your design is very important. Layout can be quite tedious, even if you have an
experienced layout engineer at hand, there will be communication required that takes
time.
So add extra transistors/resistors/capacitors, extra inverters/nand/nor/gates, why not
even an extra amplifier? You can even make them programmable (remember one of the
other lists) such that you can add/increase through software.
#7: Electromigration
Modern consumer-market temperature specifications actually stretches beyond 125
degrees. It could very well be 150 degrees. The tough requirements on metal wire widths
for these temperatures get even more tougher. In some cases, the design kit is not really
characterized at these frequencies, but instead data relies on linear extrapolation of other
data points.
Notice also that you might want to run some simulations and bench tests outside the spec
points in order to characterize the circuit better. Thereby, why not design your circuit to
meet also those external corners.
So, in short do not forget to make your wires extra-wide.
o avoid routing wires on top of high-gain nodes. This might give you a strong
capacitive coupling that could have significant impact on performance
o remember that the capacitive side-wall coupling between drain and source could
become quite large if you stack many vias on top of eachother in order to reach a
higher level metal.
o Make your design as regular as possible, let your (wild) target be to place-androute your analog design using a digital back-end tool (!)
o Jump back-and-forth between the two different worlds to mutually understand the
complexities at both ends. How can an analog macro be inserted (and properly
verified) in the digital PNR? How can a digital macro be inserted (and properly
verified) in the analog flow?