Design of 2 stage CMOS

Operational Amplifier
FINAL PROJECT

Venkata Kishore Kajuluri

ECE 523 | December 2, 2015

Goal
The goal of this project is to design a CMOS operational amplifier
block to be used in a complex system-on-a-chip (SoC). The design
must meet the requirements and it should be optimized for
robustness, power, and/or speed.

Design Specifications
Gain >= 60 dB, Unity Gain frequency >= 60MHz, Phase Margin >=
45Deg, Offset <= 50uV, Dynamic Rage = +/-6.5V (for 10mV error), Slew
Rate >= 80 V/us. The power supply is +/-7.5V and the transistors are
from TSMC 0.35u HV process.

Introduction:
There are various parameters to be considered while designing any
circuit. The parameters that are to be considered when designing an
Op-Amp are described below.

1. Gain: The most important factor in designing an Op-Amp circuit

is the required gain from the circuit. In this circuit, we expect a
gain of >= 60 dB. In order to achieve such higher gains, we use
multiple stage CMOS Op-Amp. For this project we use 2 stage
op-amp with differential amplifier at the first stage and a
common source amplifier at 2nd stage
2. Unity Gain Frequency: The frequency at which the Gain of the
circuit becomes 1 or 0 dB is termed as Unity Gain Frequency. In this
project, we need Unity Gain Frequency to be greater than or equal to
60 MHz.

3. Phase Margin: For Amplifiers, Phase Margin is the difference

between phase measured in degrees for an output signal and 180

degrees. Phase margin should be >= 45 degrees.

4. Offset: The input offset voltage is the differential voltage that is

required between the input terminals of differential amplifier to
make output voltage equal to zero.
5. Slew Rate: It is maximum rate of change of output with respect to unit
time. In this project, we expect slew rate to be greater than or equal to
80 V/us.

Procedure:
The circuit contains two stages. The first is formed by the differential pair Q1-Q2
with its current mirror load Q3-Q4. Differential pair is biased using the current
source Q5. The transistor Q5 is fed by a reference current mirror IRef. The second
stage is comprised of transistor Q6 with its current source load Q7. The second
stage is used to improve the gain significantly. The two stage Op-Amp is expected
to produce a gain greater than 1000.

In order to design the Op-Amp with the specifications mentioned above, the
first step is to estimate the value of bias current from current source IRef. The
next step is to calculate the (W/L) ratios of the transistors in the circuit

based on the Reference Current. Finally, we estimate the value of the

compensation Capacitor required to provide the negative feedback.

In order to avoid systematic output dc offset voltage, we need to choose

the (W/L) ratios of transistors carefully. To nullify the output dc Offset

PAGE 1

voltage, following condition must be met.

[(W/L)6 / (W/L)4] = 2 [(W/L)7 / (W/L)5]

T-Spice Netlist:
* OPAMP test circuit for ECE523 design project
.lib 'hv15.l' TT_hva
.param IRef=1.5E-6
VDD

VDD

GND

DC

7.5V

VSS

VSS

GND

DC -7.5V

.SUBCKT OPAMP VDD VSS INP INM OUT gnd

* Your OPAMP Circuit will be here
*
*I1 1 VSS IRef
RB 6 gnd 81K
M1 4 INM 2 VDD pch_hva L= 1.5u W= 15u
M2 3 INP 2 VDD pch_hva L= 1.5u W= 15u
M3 4 4 VSS VSS nch_hva L= 1.5u W= 2.5u
M4 3 4 VSS VSS nch_hva L= 1.5u W= 2.5u
M6 OUT 3 VSS VSS nch_hva L= 1.5u W= 30u
M8 1 1 VDD VDD pch_hva L= 1.5u W= 225u
M7 OUT 1 VDD VDD pch_hva L= 1.5u W= 180u
M5 2 1 VDD VDD pch_hva L= 1.5u W= 27.54u
M9 1 1 6 6

nch_hva L= 1.5u W= 49.99u

*
Rc 3 5 10K
CC 5 OUT 0.08pF
.ENDS OPAMP
* AC Characterization

PAGE 2

XOP12

VDD VSS In1 In2 Out12 gnd OPAMP

CL12

Out12 GND

0.5PF

RF12

Out12 In2

10MEG

CF12

In2

GND

10MF

Vin12

In1

GND

DC

.AC

0V

AC

-1V

DEC 100 1KHz 1GHz

.Probe ac VDB(Out12) VP(Out12)

.measure ac ft when vm(Out12)=1
.measure ac maxgain max vm(Out12)
.measure ac Gain_dB max vdb(Out12)
.measure ac f3db when vm(Out12)='maxgain*0.7071'
.measure ac fp1 when vp(Out12)=135
.measure ac fp2 when vp(Out12)=45
.measure ac pm find vp(Out12) when vm(Out12)=1
* Transient Characterizations
XOP34

VDD

VSS In3 In4 Out34

CL34

Out34 GND

0.5PF

RF34

Out34 In4

1M

Vin34

In3

PULSE (-5V

.Tran

1ns

GND

gnd OPAMP

5V

100ns

1ns

1ns

1us

2us)

3us

.Probe tran V(In3) V(Out34)

.measure tran SRr derivative V(Out34) when V(Out34)=0 rise=1
.measure tran SRf derivative V(Out34) when V(Out34)=0 fall=1
* DC Characterizations
XOP56

VDD

RF56

Out56 In6 1M

Vin56

In5

.DC

Vin56

VSS In5 In6 Out56 gnd OPAMP

GND DC
-7.5V

0V
7.5V

0.01

.Probe dc V(In5) V(Out56)

.measure dc

DRL find V(In5) when V(Out56,In5)=10mV cross=1

.measure dc

DRH find V(In5) when V(Out56,In5)=10mV cross=2

PAGE 3

.measure dc

Offset find V(In6) when V(In5)=0

.measure dc

Power

find '15*(I(VSS)-I(VDD))/3' when V(In5)=0

.END

Schematic Diagram:

PAGE 4

Observations:
Slew Rate: In order to adjust the slew rate closer to 80 V/us, we need to change
the value of Resistor Rb. But, changing the Slew Rate effects the Offset
proportionally. Increasing the Slew Rate increases the offset and vice - versa.

Power Dissipation: The major factors for power dissipation is the current
source. In order to minimize power, the transistors are optimized and also Rb
helps to minimize the amount of current drawn from the source.

Offset: to adjust he offset the ratio of the transistors M6,M5,M4,M7 are adjusted .
the main idea is to keep the M6/M4 ratio twice that of the ratio of M7/M5. And
the transistors M1 and M2 must have half the size of transistor M5.

Phase Margin: Phase Margin can be adjusted by adjusting the value of Resistor
Rc.

Gain: Changing above parameters also effects the gain of the OP-AMP circuit.
Characterization Parameters for the Designed Operational Amplifier:
1. Gain = 71.3726 dB
2. Unity Gain Frequency = 69.9584MEG
3. Phase Margin = 50.7854
4. Offset = 1.3334u
5. DRL = -7.3181 v
6. DRH = 6.7152 v
7. Slew Rate Rise = 81.1603 V/us
8. Slew Rate Fall = -124.5736 V/us
9.

Power = 3.3837m
PAGE 5

Results:
T-Spice - Tanner SPICE
Version 16.31
Network license from: ece46sql01.ece.unm.edu
Product Release ID: T-Spice Win64 16.31.20150805.02:42:47
Copyright 1988-2015 Mentor Graphics Corporation
Parsing "C:\Users\venkat602609\OneDrive\My Masters\Analog
Electronics\Project\OPAMP_Test_Template.cir"
Initializing parser from header file "C:\Program Files\Tanner
EDA\Tanner Tools v16.3\tiburonda\models\VAdatabase.sp"
Initializing parser from header file "C:\Users\venkat602609\OneDrive\My
Masters\Analog Electronics\Project\OPAMP_Test_Template\header.sp"
Reading library entry "TT_hva" from "C:\Users\venkat602609\OneDrive\My
Masters\Analog Electronics\Project\hv15.l"
Reading library entry "MOS_hva" from "C:\Users\venkat602609\OneDrive\My
Masters\Analog Electronics\Project\hv15.l"
Start of OPAMP_Test_Template.cir
Loaded BSIM3v33 model library, Berkeley BSIM3 v3.3.0
General options:
search = C:\Users\venkat602609\OneDrive\

threads =

1
Device and node counts:
MOSFETs -

27

MOSFET geometries -

Capacitors -

Resistors -

Voltage sources -

Subckt Definitions -

Subckt Instances -

Unique Instances -

Model Definitions -

12

Computed Models -

Independent nodes -

78

Boundary nodes -

PAGE 6

Total nodes -

84

Opening simulation database "C:\Users\venkat602609\OneDrive\My

Masters\Analog Electronics\Project\OPAMP_Test_Template.tsim"
Measure information will be written to file
"C:\Users\venkat602609\OneDrive\My Masters\Analog
Electronics\Project\OPAMP_Test_Template\OPAMP_Test_Template.measure"
Measurement result summary
DRL

-7.3181

DRH

6.7152

Offset

1.3334u

Power

3.3837m

Measurement result summary

ft

69.9584MEG

maxgain

Gain_dB

71.3726

f3db

24.4576k

fp1

24.4028k

fp2

85.9847MEG

pm

50.7854

3.7036k

Measurement result summary

SRr

81.1603MEG

SRf

= -124.5736MEG

Parsing

0.06 seconds

Setup

0.09 seconds

DC operating point

0.12 seconds

DC Analysis

1.57 seconds

AC Analysis

0.27 seconds

Transient Analysis

0.46 seconds

PAGE 7

Output

0.05 seconds

Overhead

3.03 seconds

----------------------------------------Total

5.64 seconds

Simulation completed

PAGE 8

Characterization Waveforms:
DC Cahracterization:

PAGE 9

AC Characterization:

Transient Analysis:

PAGE 10

Conclusion:
Operational Amplifier with the required specifications is designed. The
transistors are optimized to dissipate minimum amount of power, meeting all the
requirements.
Initial hand calculations may vary with the final design because of design
optimization.

Initial Hand Calculations:

PAGE 11