09/11/1431

Integrated Circuits Design

Lecture 1
Dr. Ahmed H. Madian

Dr. Ahmed H. Madian

Course Objective

Give an introduction to the primary design parameters

in digital integrated circuit.
Focus on the transistor level design and analysis.
Analyze digital circuits by calculating the delay, noise
margin, area, and power dissipation.
Cover different techniques to build digital circuits such
as static versus dynamic logic.
Discuss some industrial design issues such as global
signals and testing.

Dr. Ahmed H. Madian

09/11/1431

Text and Reference Books

Text Book


Sung-Mo Kang and Yusuf Leblebici, "CMOS

Digital Integrated Circuits: Analysis and Design.

WCB McGrew-Hill, 2003, ISBN: 0-07-246053-9.

Recommended reference books:



Jan M. Rabaey, Anantha Chandrakasan, and

Borivoje Nikolic Digital Integrated Circuits:
Second Edition. Prentice-Hall, 2003, ISBN-10: 013-090996-3, ISBN-13:9780130909961.

Dr. Ahmed H. Madian

Administrative rules

Course schedule
Lecture : Wednesday (2nd slot), 10:30 12:00 (H11)
 Office hours : Wednesday, 12:30-2:00 (C3.220)
 Teaching assistant: Eng. Mohamed Zidan


Grading
Assignments:
 Quizzes:
 Mid term exam:
 Final exam:


10%
10%
30%
50%
Dr. Ahmed H. Madian

09/11/1431

Course Outlines

Introduction
MOS inverters
Inverter switching characteristics
Power dissipation in digital circuits
Combinational and sequential MOS logic circuits
Dynamic logic circuits
Memories
Design for testability
Dr. Ahmed H. Madian

What is Integrated Circuits?

Integrated Circuit (IC): Is an electronic circuit which

can perform a completed task
IC usually contains analog and digital circuits.
Analog circuits could be as simple as a diode
(rectifier) or a simple amplifier or as complex as a
PLL (Phase Locked Loop).
Digital circuits could be as simple as an inverter
which inverts the polarity of the input signal or as
complex as a micro-processor.
In this course we are only concerned with digital
ICs.

Dr. Ahmed H. Madian

09/11/1431

Top design level

Our Course focus

on this area

bottom design level

Design
hierarchy
overview

System specifications

Abstract High-level model

VHDL, Verilog, HDL

System design
and verification

Logic synthesis

Logic design
and verification

Circuit design

CMOS design
and Analysis

physical design

Manufacturing

VLSI
Dr.Finished
Ahmed H. Madian

Initial concept

chip

Silicon logic design

and verification
Mass production,
testing and
packaging
Marketing

Moores Law

In 1965, Intel co-founder Gordon Moore predicted the future. His prediction,
now popularly known as Moore's Law, states that the number of transistors on
a chip doubles about every two years. This observation about silicon
integration, made a reality by Intel, the world's largest silicon supplier, has
fueled the worldwide technology revolution.
Many predictions followed his statement such as Area/Power/Frequency.

Dr. Ahmed H. Madian

09/11/1431

Design Parameters of Digital Circuits

Functionality
Area
Frequency
Power
Noise
Logic levels
These parameters are inter-dependent
which means satisfying one of them could
cause a violation to the other.

Dr. Ahmed H. Madian

Logic Levels
Volts

In binary system, theres only

two values logic 1 or logic 0.
For each logic theres a defined
voltage range.
If the signal voltage lies in the
range from VH1 to VH2 its logic 1
If the signal voltage lies in the
range from VL1 to VL2 its logic 0

VH2

Logic 1
VH1
VL2

Logic 0
VL1

10

Dr. Ahmed H. Madian

Undefined
region

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Manufacturing Technology

Different technologies are used to build ICs:



(GaAs, SiGe, Bipolar, ECL, NMOS, CMOS, etc.)

Why CMOS and not any of those?



CMOS has a super-advantage over all other

technologies which is its power dissipation.
CMOS should dissipate no static power which
makes it the most attractive technology until now.

Dissipated Static Power = 0W

So, we need to review the MOSFET

characteristics

11

Dr. Ahmed H. Madian

Revision on MOSFETs characteristics

MOSFET (Metal Oxide Semiconductor Field Effect

Transistor)
It has two types (N-channel and P-channel)

D: Drain
S: Source
G: Gate

NMOS

12

PMOS

Dr. Ahmed H. Madian

09/11/1431

Modes of operation of NMOS

Transistor

(1) Off Mode:

(2) On Mode:

VGS < VT
VGS > VT

(a) Linear region VDS < VGS VT

ID = 0

or

VGD > VT

V 2
I DS = K n (VGS VT )VDS DS

(b) Saturation region VDS > VGS VT

13

VGD < VT

Kn
(VGS VT )2
2

I DS , sat =
where

or

n C ox W
2

Dr. Ahmed H. Madian

Modes of operation of PMOS

Transistor

I SD = K P (V SG VTP

I SD, sat =
where

VDG > |VTP |

) V SD VSD

(b) Saturation region VSD > VSG |VTP |

or

KP
(VSG VTP
2
p

C ox W
.

2
L

14
Dr. Ahmed H. Madian

ID = 0

(1) Off Mode:

VSG < |VTP |
(2) On Mode:
VSG > |VTP|
(a) Linear region VSD < VSG |VTP | or
2

VDG < |VTP |

)2

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Course Outlines

15

Introduction
MOS inverters
Inverter switching characteristics
Power dissipation in digital circuits
Combinational and sequential MOS logic circuits
Dynamic logic circuits
Memories
Design for testability
Dr. Ahmed H. Madian

MOS Inverter Static Characteristics

16

Inverter is one of the basic elements in digital ICs.

A lot of circuit analysis are based on determining the
characteristics of the inverter.
Inverter characteristics could be classified into static and
dynamic characteristics.
Static characteristics define the noise margins of the device.
The function of an inverter is to invert the polarity of the input
signal.

Dr. Ahmed H. Madian

09/11/1431

The Basic Inverter

The ideal inverter has:





Vth = VDD/2
VoL = 0
VoH = VDD

Where VDD is the supply voltage

VTC (voltage transfer characteristics) of the inverter

17

Dr. Ahmed H. Madian

Resistive Load MOS inverter

18

For Vin < VT The NMOS

is in cut-off
IDS = 0
Vout = VDD

Dr. Ahmed H. Madian

A
0
1

B
1
0

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Resistive Load MOS inverter

For VT Vin < Vx



The NMOS is ON and in the saturation region

I DS =

Kn
(VGS VT )2
2

Vout = VDD IDs R

V x = Vout + VT = VDD I DS R + VT = VDD

Kn
(VGS VT )2 .R + VT
2
IDS
Linear

saturation

VGS

VDD
19

Dr. Ahmed H. Madian

Resistive Load MOS inverter

For VX Vin


The NMOS is ON and in the linear region

V2
V2
I DS = K n (VGS VT )VDS DS = K n (Vin VT )Vout out

2
2

Vout = VDD IDs RL

Vout
Cut-off
Sat.

VDD

linear

VT
20

10

VX

Vin
Dr. Ahmed H. Madian

VDS

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Noise Margin in the MOS Inverters

VOH : Maximum output voltage when the output level is logic 1

VOL : Minimum output voltage when the output level is logic 0
VIL : Maximum input voltage which can be interpreted as logic 0
VIH : Minimum input voltage which can be interpreted as logic 1

21

NML= VIL - VOL

NMH= VOH - VIH

Dr. Ahmed H. Madian

Noise Margin in Resistive Inverter

VOH when Vin = 0 => IDS=0 => Vout = VDD
VOL when Vin = VDD

V2
V DD VOL
= k n (V DD Vt )VOL OL

RL
2

2V DD
1
2
VOL 2.(V DD VT +
).VOL +
=0
( k n .R L )
k n RL

VOL = V DD VT +

1
1
V DD VT +
k n RL
k
n RL

VIL when dVout/dVin = -1

(VDD Vout ) = k n .(V

2

RL

22

in

2V
DD

k n RL

and NMOS in Saturation

VT )2

1 dVout
.
= k n .(Vin VT )
RL dVin

VIL = VT +

11

VOH=VDD

1
.( 1) = k n .(V IL VT )
RL

1
k n RL
Dr. Ahmed H. Madian

09/11/1431

Noise Margin in Resistive Inverter

VIH when dVout/dVin = -1

and NMOS in Linear

(VDD Vout ) = k .(V V ).V V 2

n
in
T
out

out

RL

1 dVout
.
RL dVin

dV
dV
= k n .(Vin VT ). out + Vout Vout . out
dVin
dVin

1
.(1) = k n .[(VIH VT )(1) + Vout Vout .(1)]
RL

VIH = VT +

23

12

8 VDD
1
.

3 k n RL k n R L

Dr. Ahmed H. Madian