Analog VLSI Circuits

E3-238
Homework No.2
SUVENDU MONDAL
DEPT:- IAP
SR. NO:-12268

Q1. Design a two-stage amplifier as shown in Fig. 1 meeting the following specifications:
Unity Gain Bandwidth > 750 MHz
Low Frequency Gain > 60 dB
Low Frequency CMRR >60 dB
VDD=1.2 V
Load Capacitance CL=500 fF
(You can make use of the simulator to obtain the necessary small signal parameters for your design.)
Use suitable circuits to form the current sources I1and I2 deriving from a given reference ideal current
source of 10A.
a) Outline your design methodology and provide the dimensions of the transistors used in the circuit and
the input bias.
b) Identify the poles and the nodes at which they occur.
c) Obtain the frequency response of the amplifier and show that it meets the specifications.
d) What is the Gain Margin and Phase Margin of your circuit? Do you think it is acceptable?
e) Plot CMRR vs frequency.
f) Derive the input referred noise for the circuit you have designed. Substitute the small signal parameters
of your circuit and give the final expression.
g) Compensate the amplifier to get the minimum phase margin of 45 degrees. Provide a short theoretical
explanation for the improvement in phase margin. Overlay the new Bode-A graph with the previous
result. What is the new location of poles and zeroes?

Fig 1

Optional Part (not compulsory)

h) Connect the amplifier in a unity gain configuration. Give a pulse having 100 mV amplitude and pulse
width equal to 2 ns at the input. Plot the output. Now change the pulse width to 500 ps and plot the
output. Give a brief theoretical explanation for the two results.

a) Design Methodology: We redraw the circuit in Fig 1 in Fig 2 by replacing ideal current sources by
ideal current mirrors.

Fig 2: Detailed schematic diagram of Fig 1

We need: Unity Gain BW > 750 MHz, Low Frequency Gain > 60 dB, Low Frequency CMRR > 60 dB,
VDD = 1.2 Volt, Load Capacitance CL= 500 fF
The gains of the first and second stages and CMRR of the circuit in Fig 2 can be written as:

= (

Where,

and

and

||

=
=

||

||

||

||

are the transconductance and output resistance of M1 and M2

are the transconductance and output resistance ofM3 andM4, and

is the output resistance of M5.

This equation can be simplified to give

[

Where,

and

and

|+|

are the overdrive and Early voltage of the differential pair, and

are the overdrive and Early voltage of the mirror.

Channel length, L = 3 * (minimum channel length) = 3* 120nm = 360nm (Chosen to reduce short channel
effect). Now we write,

where,
and,

L=360nm

0.06um/V for NMOS

= 0.05 um/V for PMOS

Hence, |VA(NMOS)| = 360 X 10-9 X 1/(0.06 X 10-6) = 6 V

And, |VA(PMOS)| = 360 X 10-9 X 1/(0.05 X 10-6) = 7.2 V
For CMRR > 60 dB
20log10CMRR > 60 => CMRR > 103 => [4/(VOV(dP)*VOV(mir))]*(6*7.2/(6+7.2)) > 103
This simplifies to:

= 120 mV
= 100 mV

Now we set,
=

Now we assume,

=
=

for I1

for I2.

(i)

Using the simulator, we can find a typical value of a eff for given W/L. A typical DC simulation set-up
gave us:

= 530 A/V2

= 100 A/V2

When the output of the first stage and input of the second stage are connected,

| |
/

| |

= | |

| |
/

( ) =

| |

( ) =

After tuning the W/L values in order to meet the design specifications:

=
=

The input DC biases are 300 mV.

b) Location of the poles of the system:

.
.

for I1
for I2
=

.
.

Pole due to differential stage:

=

+ , ) + , ( +

= equivalent capacitance at drain of MOS M3.

Assuming

Where

, 1 , we may write:
||

Pole due to common source amplifier:

=

c) Circuit diagram and frequency response:

Fig 3: Uncompensated amplifier circuit

Frequency response:

||

, )

1) Differential mode:

Fig 4.1: Frequency response of uncompensated amplifier in differential mode.

Fig 4.2: Frequency response of uncompensated amplifier in differential mode.

Fig 4.3: Frequency response of uncompensated amplifier in differential mode.

From the above three figures we see that differential gain = 60.8625 dB.
And Unity Gain Bandwidth = 768.86MHz.
2)Common mode: The common mode frequency response is given below.

Fig 5: Frequency response of uncompensated amplifier in common mode.

We see that the common mode gain = -11.499 dB in low frequency.
So CMRR= 60.8625-(-11.499) dB= 72.3615 dB.

So we see that this design meets all the specification.

d) Gain Margin and Phase Margin:
From, Fig 4.1 and 4.3 we see that,
Gain Margin= 6.573 dB
And Phase Margin= -9.221 deg.
e) CMRR vs Freq:

Fig 6. CMRR vs Frequency Plot

f) Input Referred Noises:
Flicker noise:
Due to M1 M2
Both have equal contribution thus total referred noise due to both is given as
, ,

Due to M3, M4

Both have equal contribution thus total referred noise due to both is given as
, ,

Due to M6

 , ,

Due to M5 M7 M8

, ,

Total flicker noise is summation of all above

Thermal noise:

Due to M1 M2
=

, ,

Due to M3 M4
=

, ,

Due to M6
, ,

Due to M8

gm

gds + gds

, ,

gm

gm

, ,

, ,

Due to M5

Due to M7

gm gds + gds

Total thermal noise is summation of all above thermal noises.

The total input referred noise is equal to flicker noise + thermal noise.

g) Circuit after compensation:

A capacitor is added in the fashion shown in below circuit, the value of the capacitor is 5pF.

Fig 7: Circuit diagram of compensated amplifier

The frequency response of the compensated circuit is given below.

Fig 7.1: Frequency response of compensated amplifier in differential mode.

Fig 7.2: Frequency response of compensated amplifier in differential mode.

From Fig 7.1 and 7.2 we see that,
Gain Margin= -11.15 dB
And Phase Margin= 71.94 deg.
A comparison of GM and PM is given below for both compensated and uncompensated circuit.
Gain Margin (dB)

Phase Margin (deg)

Compensated

-11.15

71.94

Uncompensated

6.573

-9.221

The phase margin after adding compensation has become positive and is equal to 72.13 deg (approx). The
system has become stable but at a cost of reduced bandwidth.

We compare the uncompensated and compensated gain and phase plots below:

Fig 8. Overlaid Pot

Reference: Analysis and Design of Analog Integrated circuits.(Page-425 onwards) by

Paul R. Gray; Paul J. Hurst; Stephen H. Lewis; Robert G. Meyer.