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Power Switches
AmitMohod
The
simulation
is
performed
for
verifying
the
INTRODUCTION
64
TABLE I
SWITCHING SCHEME FOR THE PROPOSED BASIC UNIT
Switches states
state
S2
S3
on
off
off
off
off
on
Va
off
on
off
Va+Vb
(2)
Ns= 3n+4
Nvs = 2n (3)
(1)
All the voltage levels that can be generated by the
proposed cascaded multilevel inverter depending upon the on
and off states of the power switches are shown in Table II. As
aforementioned and also according to the Table II, the
proposed inverter which is shown in Fig. 2 is able to produce
only positive levels at the output of the cascaded series
connection of the proposed basic unit. Hence, for generating
both the positive as well as negative levels, an H-bridge is
added at the output of the proposed topology with four
switches TI to T4. This inverter is named as advanced
cascaded multilevel inverter which is shown in Fig. 3. For
generating the positive voltage levels at the output of the
proposed inverter, switches TI and T2 are turned on
simultaneously and in this case the load voltage Vload will be
VB
/.. .. .. .\...
\ S3)
VOlit
S,
tI
I
I
II
I
I
I
I
I
I
,
I
I
I
I
Unit 1
VOIl/I
V2B
Unit 2
tJ
21 f--J
S22
V2A
it
:1
; I
11
S23: 1
!VOU/2
Vow
:1
; I
..................... .............................. ,i
Vaut
\"('.:
\
2015
y,:.i
.
.
65
!+
i+
Sl1
Unitt
II
Vi~
S13!
I Voutl
!ilI
SI2
!! II
iI
, I
VIA
............................._..................1r_ _-1 t
TI
il
V2B~
r&!i~
l__:_Jl
UnY,I th,
Vout
VnA
r-.. . . . _.. . . . . _. . . _1 t
;
Vn;r
r~2 sJ! II
Vou,"
Nlevel
i
ii
!
1..................-.-..:.:...................1
(4)
VnB = (2n-l)Vdc
=4
X (Li~l
2i-l) + 1
(5)
(6)
SWITCHING SCHEME OF THE SWITlCHES FOR THE DIFFERENT OUTPUT VOLTAGE LEVELS GENERATED AT THE OUTPUT
Vout
Sl1
S12
S13
S21
S22
S23
S31
S32
S33
on
off
off
on
off
on
off
off
on
off
off
on
off
off
off
off
on
off
off
on
off
off
on
off
on
off
off
on
off
off
off
off
on
on
on
off
off
off
on
off
off
off
off
off
off
off
on
off
on
on
off
off
off
on
on
off
off
on
off
off
off
off
off
off
off
on
off
off
off
off
off
off
off
on
off
off
off
on
on
on
on
off
on
off
on
off
off
off
on
off
VIA
VIA+VIB
V2A
VIA +V2A
V3A
VIA +V3A
VIA + VIB +V3A
V2A+V3A
...
...
...
...
...
...
...
...
...
...
Sil
Si2
Si3
on
off
off
on
on
on
on
on
on
off
off
on
off
off
off
off
off
off
off
on
off
off
off
off
off
off
off
off
on
off
(V;AH'iB)
i=1
66
40
30
20
Ndriver
Proposed
10
L0
0
10
Nlevel
20
40
30
SIMULATION RESULTS
,+
Unit
lovT
'2
I! s" r
j
SI3
! I
I
1! vOUlI
!: II
,I
: I
! 1i
I1;
t......
....................
.. ............ .............................
........................... ;
Unit
2!
20vT
S21
!'II
r22
sii
2:
20V
j,II
3 1I1Volt12
: I
,I
: I
,I
VOIII
--:--+
lIoad
t.................... ............................ J-
40
30
20
NIGHT
Umt 3
10
IOV
:t
r;{
lH
r i!
S 31
32
30V
30
2015
40
T;
S33 Vo,,'"
: I
,, 11
. 1
1!
1
67
0.01
0.02
0.03
0.04
0.05
Time!s]
0.06
0.07
0.06
0.09
O. I
(c)
FFTanalysis
0.7
THO=
57'/.
0.6
19 0.5
0.4
'00.3
.:.
0.2
o. 1
100
200
300
700
800
900
1000
900
1000
(d)
FFTanalysil
Fundamental (50Hz) = 3.519, THO= 1.99%
200
300
700
800
(e)
Fig. 9. Simulation results; (a) output voltage wavefonn of the basic unit;
(b) output voltage wavefonn of the 37-level cascaded multilevel inverter;
(c) load current wavefonn with an RL load (R=50n and L=30mH) (d)
Hannonic spectrum of the load voltage; (e) Hannonic spectrum of the load
current.
6
68
2015
CONCLUSION
[1]
[2]
[3]
[4]
6.
[5]
[6]
[7]
[8]
[9]
2015
69