A Parameterized Ethernet Media Access Controller Soft IP

Ming-Chih Chen, and Ing-Jer Huang

Dept. of Computer Science and Engineering
National Sun Yat-Sen University
Kaohsiung, Taiwan
Abstract
This paper presents the implementation of a reusable Ethernet MAC (Media Access Controller)
Soft IP. The IP is used to execute Ethernet CSMA/CD protocol. This protocol performs receiving
and transmitting processes of packets. In order to reuse this IP (Intellectual Property), first, we
specify the interface of MAC that is called MII (Media Ind ependent Interface) and the physical
layer device that is called transceiver. Second, we specify the other interface of MAC connected
with customers packet switch fabric module. So, the IP can be reused in different types of Ethernet
devices, which require different number of MAC modules. An automatic MAC unit generator is
implemented. Users can select the desired number of MAC units through parametric environment
setup. In order to verify the integration of MAC IP with packet switch fabric, we provide a 10/100
Mbps layer-2 switch controller RTL simulator. And an analyzer helps to evaluate the performance
of MAC unit in the switch. In addition, an FPGA prototyping reveals the validity of the IP. Finally,
a TSMC 0.6 m CMOS technology is used to implement a single MAC IP.

Keyword: Ethernet, IP, MAC, CSMA/CD, MII, FPGA

1. Introduction
Todays network services impose tremendous requirement on Internet. And different
connection devices extend the communication
possibilities. The expone ntial uses of e-mail,
distance learning, video, conference, and etc.,
contribute an increasing requirement for connectivity. Conve ntional Ethernet and Fast
Ethernet can sustain some immediate requirements. But QoS (Qua lity of Service), video on
demand, and etc, need huge bandwidth. Gigabit Ethernet will be applied for these requirements.
Different network requirements can be
differentiate according to their layout. LANs
(Local Area Networks) are generally confined
to a building, or a campus and are the leaves of
spanning tree of networking. MANs (Metropolitan Area Networks) are confined to cities,

and WANs (Wide Area Networks) are restricted to connecting cities, countries.
Several topologies are dominant in the
LAN connection, like star, bus, and token ring.
IEEE standardized LANs protocols, like IEEE
802.3 Ethernet, IEEE 802.4 Token-Bus, and
IEEE 802.5 Token-Ring. The Ethernet technology uses IEEE 802.3 CSMA/CD protocol
for determination of physical network access.
And the protocol is defined in the Data Link
Layer of OSI (Open System Interconnection).
The Data Link Layer contains LLC (Logical
Link Control) sub- layer and MAC (Media Access Control) sub- layer. Different IEEE 802.x
protocols distributed in the MAC sub- layer
shares the same 802.2 LLC standard. IEEE
802.3 CSMA/CD is general called an Ethernet
MAC (Media Access Controller).
The Ethernet MAC is the most widely
used interconnection mechanism for todays

LAN systems, such as adapter, hub, bridge,

switch and etc. It performs receiving and
transmitting packets through Ethernet devices.
It connects the physical layer that is called
transceiver downstream and connects the
packet switch fabric upstream. Due to the requirements of different Ethernet equipments,
formulate it to be an Ethernet MAC IP.
There are several important guidelines of
IP, Reuse, Retarget, and Reconfiguration. To
reach the reuse of Ethernet MAC IP, the specification of upstream and downstream interfaces
is needed. The destination of retarget is to design a flexible module, and can be target to
different CMOS processes. The reconfiguration
of the MAC IP is used to apply for different
number of MAC requirements. And automatic
generator of this IP can help designer or
third-parity to reduce the difficulties of integration. Indirectly, speed up the time to market.
The rest of this paper includes the follo wing sections. In Section 2, we present the
background and application of MAC(s). Section 3 introduces th MAC IP architecture and
partition method. The functions and features of
the MAC IP are presented in Section 4. In Section 5, we present the MAC implementation
and verification system. Finally, the conclusion
is given in Section 6.

2. Background
The CSMA/CD (Carrier Sense Multiple
Access with Collision Detection) is the most
widely used interconnection mechanism for
todays LAN systems, such as adapter, switching hub, bridge and so on. With the demand
towards higher speed, the 100 Mbps Ethernet
becomes popular and acceptable on the market.
The MAC units are the common packet access
mechanism of such Ethernet devices. In order
to reduce the design flow and the
time-to- market of communication devices, we
need an integrated 10/100 Mbps Ethernet MAC
Soft IP.
In a typical high performance network interface, there are three major portions in the

design of a communication controller chip described as follows:

l Receiver: The receive MAC follows the
receiving flow of 802.3 CSMA/CD. On
the receiving side, a packet is received
from the network, and then is checked by
the CRC (Cyc lic Redundancy Check). Information such as DA (Destination Address), SA (Source Address) and Length
field of a packet will be extracted simultaneously. And error signals will also be
presented such as Length too small/long,
and CRC errors. If correct, then it will be
scheduled to store in the allocated memory. Otherwise, it will be discarded.
l Transmitter: The transmitter follows the
transmitting flow of 802.3 CSMA/CD. On
the transmitting side, a packet is transmitted from assigned memory such as main
memory in NIC, or SGRAM in Switch,
and then is appended by the CRC. Information such as CRC errors and CRS will
be presented in the transmitting process. If
correct, then it will be scheduled to the
destination port(s). Otherwise, it will be
discarded or retransmitted.
l Controller: The controller is used to
schedule the flow of packet accesses and
provide the information of the requirement of packet accesses.
The block diagram of a switch hub system
is shown in Figure 1. In the architecture, the
MAC unit includes receiver and transmitter.
The 802.3 CSMA/CD protocol has been implemented in the MAC unit. The controller that
was mentioned above has been implemented in
the packet switch fabric. The same design
considerations of NIC are shown in Figure 2.
From the view of architecture, the MAC unit
can be abstracted as an object. The object can
be created as a function or a macro.
In order to meet the reuse of IP, there are
several considerations may be included and
specified. First, to reduce the forwarding delay
in the Ethernet devices, the cut-through and
store-and-forward operation must interact in
the packet accesses. Second, the MAC and
PHY layer interconnection must be defined as
a specification. The MII is an IEEE 802.3

compliant interface that is used to interconnect

the PHY layer devices. This interface is used to
provide media independence for various forms
of shielded/unshielded twisted pair wiring, fiber optic cabling, and other potential media.
The interface signals between PHY layer and
MAC sub- layer can be specified according to
the definition of LLC sub-layer.
Third, the MAC and controller interface
must be specified. Due to the relationship of
controller and MAC is a master and a slave.
The MAC is a slave in the relationship. So, the
specification of MAC can provide an easy
communication interface to the controller. The
several considerations above are implementation in our design.
Application &
Verification
Environment
Cut-through

SGRAM

Store and
Forward

Packet Switch Fabric

Tx FIFO
&
DMA, Snoop
(Transmitter)

Rx FIFO
&
DMA
(Receiver)

Tx MAC

Rx MAC

# of MAC unit

Transmitter

Receiver

802.3 CSMA/CD

MII

MII

MAC
IP

Figure 1. The block of switch

PCI Interface

PCI Bus Master

Interface

Flash EPROM

Tx FIFO

Micro-Machine
&
System Control
Block

Tx/RX FIFO
Controller

Rx FIFO

10/100 Mbps
MAC
Serial
Interface

MII
Interface

Figure 2. The block of NIC

In order to meet the reuse of IP, there are
several considerations may be included and
specified. First, to reduce the forwarding delay
in the Ethernet devices, the cut-through and
store-and-forward operations must interact in
the packet accesses. And if a cut-through
transmission doesnt success, stores the frame
to memory and reschedules it to the destination.
Second, the MAC and PHY layer interconnection must be defined as a specification.
The MII is an IEEE 802.3 compliant interface
that is used to interconnect the PHY layer devices. This interface is used to provide media
independence
for
various
forms
of
shielded/unshielded twisted pair wiring, fiber
optic cabling, and other potential media. Third,
the MAC and controller interface must be
specified. Due to the relationship of controller
and MAC is a master and a slave. The MAC
plays a slave role in the relationship. So, the
specification of MAC can provide an easy
communication interface to the controller. The
several considerations above are impleme ntation in our design.

3. MAC IP Architecture & Partition

The Ethernet MAC IP is a hardware design to implement the CSMA/CD functional
capabilities. The LLC sub- layer provides an
easy way to transform data between the IP and
other devices. The MAC sub- layer is defined
by the IEEE 802.x protocol. The Ethernet
MAC implements IEEE 802.3 CSMA/CD
protocol. From the view of architecture, we can
partition the IP according its functionalities.
And reuse the IP through the parameterized
selector.
3.1. Architecture Description
The main service of MAC is to follow the
CSMA/CD protocol. When receiving a frame
from PHY layer, drops the header, and CRC
fields of the frame. This is called Decapsulation. When transmitting a frame, appends the
header (Such as DA, SA, Length), and CRC
fields of the frame. This is called Encapsulation. The block diagram of the MAC unit is
shown in Figure 3.We have integrated the fo llowing functions into a single chip described as
follow:
(1) CSMA/CD MAC unit: The unit is implemented by IEEE 802.3 CSMA/CD protocol. It is used to deal with transmit and
receive processes. And it includes two major portions, receiver and transmitter.
(2) Snooping mechanism: The unit is used to
support the cut-through mode of packet
transmission and helps to reduce the frame
delay. When the destination link of transmitted packet is not busy, the unit detects
some situations such as link speed, queued
frames. Then transmitting frames to the
destination port directly.
(3) Distributed DMA units: The unit is used
to support the store-and-forward mode of
packet transmission. When the transmitting
packet cant confirm the cond itions of
cut-through mode, the MAC operates with
store-and-forward mode. The DMA helps
to transfer data between the DRAM memory and the MAC port for receiving or
transmitting a packet. A DMA controller
associated with a port is a bus master for

performing the data transmission. The centralized or distributed bus arbiter can arbitrate the use of the memory bus.
(4) Transmit and receive FIFO: The unit
performs the packet queuing. The requirement of FIFO is to temporal store the
frame transmitted to or from PHY layer. In
the design of Ethernet devices, the small
memory is to acquire the time of packet
scheduling and to avoid the packet loss due
to underflows or overflows of packets.
(5) MII: The interface is used to provide media independence for various forms of unshielded/shielded twisted pair wiring, fiber
optic cabling, and other potential media so
that identical media access controller may
be used with any of these media. This interface provides independent 4-bit width
transmit and receive data paths. And synchronous data transmissions trigger with
RCLK and TCLK, which are provided
from PHYSICAL layer.
The architecture can be divided into
two portions. One is the receiver circuit (Rx
MAC), and the other is the transmitter circuit
(Tx MAC). They are shown in Figure 3.
Rx DATA
Rx
CONTROL
Rx
CONTROL

Rx DMA

Rx CONTROL
&
STATUS
Rx FIFO
&
FIFO
CONTRO
L
Rx DATA

RECEIVE
Rx
CONTROL

Rx
STATUS

Rx DATA

Tx
CONTROL

SNOOP

Tx
CONTROL

Tx DMA

FLOW
CONTROL
Tx
CONTROL
Tx CONTROL
&
STATUS
Tx FIFO
&
FIFO
Tx
CONTROL CONTRO Tx DATA
L

TRANSMIT

Tx DATA

Rx
DATA

Rx DATA

MII
PORT
Tx DATA

Tx
CONTROL

Tx
STATUS

Tx DATA

Figure 3. The block of MAC IP

3.2. Packet Access Process
In the MAC design, we divide it into two
parts. One is the Rx MAC, and the other is
the Tx MAC. They all follow CSMA/CD
protocol. Their operations are described as
follows:
(1) Transmit operation:
To follow the
CSMA/CD transmitting processes, the al-

Tx
DATA

gorithm was specified. The algorithm of

transmitting a packet is shown in Figure 4,
implements with the transmitter. The
transmitter reads data from the transmit
FIFO through a 64-bit data bus and transfers the data through the MII interface to
MII port. When the Tx FIFO is filled to the
threshold level, or when there is a full
frame buffered into the Tx FIFO, the
transmit MAC begins to encapsulate the
frame after a minimum inter frame gap
(IFG) time. Actual transmission of the data
on the network occurs only if the network
has been idle for a 96-bit duration, or the
IFG, and the back-off time requirement
have been satisfied. The MAC detects a
collision when the COL signal asserts in
the MII. When the MAC senses a collision while transmitting, it halts the transmission of the data. Then, it transmits a jam
pattern
consisting
of
hexadecimal
AAAAAAAA. At the end of the jam
transmission, it begins the back-off waiting
period determined by the truncated binary
exponential process. When sixteen times of
attempts has been made at transmission and
all have been terminated by a collision. The
MAC sets a dirty bit indicates that the
buffer associated with this frame can be released. The above operation is referred to
the half-duplex mode. The full-duplex
mode for transmitting frames unconditio nally.

TransmitFrame

Transmit Eanble?

yes
assemble frame
yes

deferring on?

no
start transmission
no

collision Detect
no
send jam

no
transmission
done?

increment
attempts

too many
attempts?

no
yes

yes

compute backoff

wait backoff time

Done:
transmitDIsabled

Done:
transmitOK

Done:
excessiveCollisionError

Figure 4. The transmit flow of 802.3

CSMA/CD
(2) Receive operation: The MAC continually
monitors the network for a new frame reception. The specified algorithm is shown
in Figure 5. When a new frame is recognized, it starts to process the incoming data.
With MII interface, the MAC detects the
activity when both RxDv and CRS signals
are asserted. The RxDv is asserted by the
PHY layer for receive valid data while
CRS is the carrier sense. After detecting the
activity, the MAC starts to process the
preamble bytes. The first bit of the destination address signifies whether it is a frame
for broadcast or unicast. The input data
(starting from the DA field) are buffered in
the receiving FIFO. As the FIFO has
reached a threshold value, the DMA moves
the data out of the Rx FIFO and sends them

to the output queue of the destination port.

The frame is rejected if a CRC error occurs.

ReceiveFrame

Receive Eanble?

yes
start receiving
no

no

done receiving?

yes
yes

frame too small?

(collision)

yes

no

frame too long?

no

no

recognize
address?
valid frame
check
sequence?

no

yes
extra bits?
yes
valid length field?
yes
no

yes
no
dissemable
frame

Done:
receiveDisabled

Done:
frametooLong

Done:
lengthError

Done:
receiveOK

Done:
alignment Error

Done:
frameCheckError

Figure 5. The receive flow of 802.3

CSMA/CD
The two operations follows IEEE Ethernet
protocol, but need several units to support such
as DMA, and FIFO. And to support
cut-through/store-and-forward
transmission,
the interaction of DMA and snooping mechanism is needed. How to divide or integrate
these modules is more important.
3.3. MAC Partition
The partition of MAC IP can be divided
into several blocks according to the different
requirements of designers. So, the vertical and
horizontal segmentation are described as fo llows:
(1) Vertical segmentation: The segmentation
is considered according to the compliance
of
CSMA/CD
protocol
and
cut-through/store-and-forward
transmissions. If designer only need the modules of
performing the CSMA/CD protocol.
Through parameterized selector, designer

can only select the modules of CSMA/CD

IP. In order to support both the cut-through
and store-and- forward transmission modes,
the parameter of both modes can be enable
or disable. If we only select the
store-and-forward mode, the Tx/Rx DMA
modules will be included with CSMA/CD
IP. If selecting both modes, the Tx/Rx
DMA modules and snooping mechanism
will be included with CSMA/CD IP. In
general, the design of supporting both
transmission modes is provided. So, providing both modes is the default setting.
The vertical segmentation of MAC IP is
according to its functionality. And the advantage of the segmentation will be revealed in the synthesis of IP. The implementation of the CSMA/CD protocol includes these portions that can be optimized.
For an example, the Tx and Rx FIFO controller, they are the similar circuit. If the
optimization is successful, the reducing of
nets can be expected. Certainly, there are
several additional functions can be selected
or used such as flow control and
auto-negotiation.
(2) Horizontal segmentation: The segmentation is determined according to receive and
transmit processes. The reason of the segmentation is that the designer wants the lucid circuits. If the designer wants to add
some new functions or modules into the IP,
the clear partitions of Rx/Tx modules are
needed. The segmentation often provided
by the synthesis tool. For example, the
scripts of synthesized flow provided by the
IP generator. In the scripts, designers can
set optimize or dont touch instructions
to reach the transparency of Rx/Tx processes.

4. MAC IP Function & Feature

The function of MAC is to communicate
with PHY layer downstream and interconnect
with packet switch fabric upstream. Reuse and
retarget of this IP are the main features. We

have presented some functions and features

hidden in the former sections. Here, we will
explain them respectively.
4.1. Functional Description
In the MAC design, we divide it into two
parts. One is the receiver circuit (Rx MAC),
and the other is transmitter circuit (Tx MAC).
They all follow CSMA/CD protocol. Here,
there are two important functions described as
follows:
(1) Collision retransmission: When a collision happens in the transmitting process,
the transmitter sends jamming signals and
calculates the random delay time. The
random delay time generates from the binary expone ntial back-off algorithm.
While the delay time expires, retransmits
the packet. If collisions of a frame occur
frequently, the transmitter discards the
frame. The function helps to reduce the
collision times of networking environment.
And increasing the bandwidth of network
indirectly.
(2) Flow control: A special instruction is
available for generation of PAUSE frames
used for flow control in the full duplex
mode (IEEE 802.3x). The host, on determination of its buffer level, decides not to
receive more frames until its buffer has
reached a safe limit. The host then decides to send PAUSE frame to the sending
station asking it to inhibit the transmission.
The receiver receives a PAUSE signal and
the PAUSE Timer on it starts counting
down. And stopping to receive frames
until the count reaches zero. During the
pause period, the transmitter can still
transmit control frames if requested to do
so by the host. The function can help to resolve the traffic congestion of network.
And also reducing the situation of packet
loss due to the smaller memory design.
4.2. Key Features and Claims
The purpose of MAC IP design is to ha ndle receiving/transmitting processes, and also
to support store- and- forward/cut-through
transmission mode. It can operate in 10/100

Mbps half and full duplex mode. The reception/transmission of frames need to be scheduled by the switch mechanism. Hence, we
need the FIFO design to buffer the
transmission requests of frames. The MAC
provides these features described as follows:
l Supports for reconfiguration: We can
configure the desired number of MAC IP
through the parameterized generator.
l Supports for reuse: Reusing this IP to
different network devices with MAC. If
the specification of MAC is clear enough,
the reuse of this IP is easy.
l Supports for Automatic Test Pattern Generator: Using the generator to simulate
those situations of packet transmission.
l Supports for Switch RTL simulation environment: Using the integrated Switch
Controller & MAC IP to simulate the validity of MAC functions. Through the
simulator, the observed results will be
stored into a report.
l Supports for Report Analysis: Using
Report Analyzer to indicate these situations of packet transmission writing in the
simulation report.
l Physical proof & demo environment:
Using TSMC 0.6 m CMOS technology
to implement. And Uses Xilinx Virtex
FPGA chip & demo board for revealing
demo environment.
4.3. Configuration Information and Parameters
Due to the different requirements of designers, we design the parametric program to
auto-generate MAC RTL codes. Due to the design automation, user can utilize the parametric
configuration to get the MAC IP. The ge nerator of MAC units is shown in Figure 6.
For example, we illustrate one and six
port MAC IP respectively. The generator of
MAC units is shown in Figure 6. We can select
the port numbers of MAC in this C program.

Figure 6. One portion of Automatic IP

generator
We define the specification of one-port
MAC IP. In the MAC IP, only one unit of Rx
MAC and Tx MAC are included. For example,
the verilog modules of one-port and six-port
MAC are shown in Figure 7 and Figure 8.
The difference between one-port and six-port is
the top module of hierarchical architecture. The
instance of one-port MAC is only one Rx/Tx
MAC unit. But six-port has six units of them.
And the other difference of output nets.
Six-port MAC has six copies of portions of
nets. But the bit-widths of data or address bus
are the same. From the difference of top modules, we can create a generator to generate arbitrary ports of MAC IP.

Figure 7. A portion of one-port MAC IP

Figure 8. A portion of six-port MAC IP

5. MAC IP Verification & Implementation

The design of MAC IP is used to support
different Ethernet devices that use IEEE 802.3
CSMA/CD Std. The verification of MAC
closely links with the IP design. Here, we
provide test patterns to verify the functionality
of this IP, and also provide a switch simulator
to reveal the practicability of this IP. In order to
faster prototype and modify the IP, we utilize
the FPGA design flow. And we integrate the
Xilinx Virtex Development System and the I/O
Board designed by ourselves to form the Demo
System. The bus model design methodology
provides packet streams in the demo system.
5.1. Verification Strategy
Figure 9 shows the verification flow of
the MAC. There are two verification strategies of this IP. First, using Automatic Test Pattern Generator of ours for verifying the MAC
RTL design and its gate level circuit. In order
to support different designs, we provide two
verification models described as follows:
(1) An individual Rx/Tx MAC test bench:
The environment is used to simulate the serial/parallel data inputs of Rx MAC/Tx
MAC. And it provides the input signals to
emulate the real variation of external signals. Through the output signals dumping,
we can check the correction of this IP. This

method is the general step in design methodology.

(2) A switch system model: The model is a
switch simulator. The simulator is implemented by Verilog RTL codes. The MAC
IP is one of components in the layer-2
switch. The linking port numbers of the
switch simulator can be configured by setting parameters. So, we can verify one, two,
or many port numbers of the MAC IP. Increasing the port numbers is the same as
increasing the number of MAC units. In
our IP design, despite the different numbers
of MAC units, they can be integrated to
form the MAC IP. The example is shown in
Figure 7 and Figure 8. When we have integrated the MAC IP into the switch system,
the Automatic Test Pattern Generator will
provide the requirement of packet streams.
In the simulator, we provide the probes of
internal signals for dumping the run time
results. And the Report Analyzer can analyze the dumping results and provide the
report of this switch performance including
the MAC IP. The report of the Analyzer is
shown in Figure 10. The example is illustrated in the report. The simulator configuration is an eight ports switch and every
port links 100 Mbps Ethernet devices.
From the report, the successful rate of
cut-through is 36/160=0.225, the delay
time of cut-through in Rx FIFO is 3680
nanosecond, and so on. These messages
help designer to realize the influences of
different packet streams that may cause the
switch and MAC IP.
Second, integrating I/O Board and Xilinx
Virtex FPGA Development System for providing the physical proof. The fast prototyping
Demo System helps to reveal the practicability
of the MAC IP.
Here, we provide a bus model that implements the test bench in the Xilinx Virtex
ROM module. Through integrating FPGA
evaluated board and external I/O Board, we
can display the handshaking between data and
signals.

MAC Verification

RTL & Gate Level

Simulation

Switch System
Model
&
Emulating
Network
Environment

Individual Rx/
Tx MAC
Testing

FPGA
&
Bus Modeling
Simulation

Individual Rx/Tx
Verifcation
Environment

Figure 9. The verification flow of MAC IP

Figure 10. The report of the Report Analyzer

5.2. Implementation Method (IC and
FPGA)
The MAC implementation includes two
portions. First, we propose the ASIC design.
Our design uses TSMC 0.6 m CMOS technology for implementing a single MAC unit.
The synthesis report is shown as Table 1. The
gate counts of our design are about twenty

thousand. And the critical path delay is 11.04

ns. In order to meet the requirements of different numbers of MAC ports, we provide an
MAC IP generator. Through the generator, we
can select the desired numbers of MAC ports
to synthesis automatically. And the automatic
synthesis scripts help designers to get the gate
level circuit of the MAC IP.
Second, we also provide the FPGA demo
system.
We
use
Xilinx
Virtex
XCV300-6BG432 FPGA chip for implementing our single MAC unit. The packet streams
are implemented as a bus model. The bus
model is embedded into the memory of FPGA
Development System.
The demo system is shown in Figure 11. It
integrates FPGA Development System and I/O
Board. The I/O Board is an external circuit that
can display the important data and signals of
MAC IP such as DATAIN (4-bit MII data),
DATAOUT (64-bit Data Bus), COL (Collision
Detection), and so on.
When the demo system starts, the received packet stream will be read from the
ROM modules of FPGA Development System.
When the received packet comes to the Rx
MAC modules in MII form (4-bit parallel data),
the 7-segment displayer signals the received
value, and Carrier Sense signal is triggered.
When the received packet is transmitted to
64-bit Data Bus, another 7-segment displayer
will be triggered. On the transmit side, when
the packet stream is read from the ROM modules, the opposite LED displayers will be triggered.
The download report of FPGA based implementation is shown in Table 2. The report
shows the utilized rate of FPGA chip. And Table 3 shows the major portion of timing analysis. The maximum frequency is 18.855 MHz.
Table 1. One MAC synthesis report
Report Output
Data Arrival Time
11.04 ns
(Critical Path)
Total
Dynamic 763.6920 mw
Power
Total Area
19497.203125 gates

Xilinx Virtex Chip

(Development
Board)

J-TAG
download cable

Data/Signals
Displayer
(I/O Board)
Figure 11. The prototype of the MAC demo
system
Table 2. The download report of Virtex Chip
Device utilization summary:
Number of External 1 out of 4
25%
GCLKIOBs
Number of External 44 out of 316 13%
IOBs
Number of SLICEs
1090 out of 35%
3072
Number of GCLKs
4 out of 4
100%
Number of TBUFs
726 out of 22%
3200
Table 3. The timing analysis of FPGA
Timing summary:
Timing errors: 0 Score: 0
Constraints cover 154291 paths, 2084 nets,
and 7362 connections (100.0% coverage)
Design statistics:
Minimum period: 53.036 ns (Maximum
frequency: 18.855MHz)
Maximum net delay: 13.729 ns

6. Conclusion
We have presented the design of a MAC
IP for the 10/100 Mbps Ethernet network. The
MAC IP can be utilized in different Ethernet
devices. In the goals of reducing design flow
and accelerating time-to- market, we have designed a MAC unit generator. Through automatic port(s) configuration, designers can integrate the MAC unit(s) with other circuits into a
system chip. The FPGA design flow helps us
to develop a prototype speedily. We also provide a switch system simulator to serve as the
verification environment. And a report analyzer helps us to analyze the timing and status
of packet transmission between Rx/Tx MAC
and switch fabric. Currently, we are engaged in
the modification of FPGA demo system to
support dynamic packet streams downloading
through the J-TAG download cable. Gigabit
Network is rising and flourishing now, the integrated 10/100/1000 Mbps Ethernet MAC IP
will be utilized to support the development of
Gigabit Ethernet devices.

References
1. H. E. Meleis, and N.S. Dimitrios, Designing Communication Subsystems for
High-Speed Networks, IEEE Network,
Vol. 64, pp. 40-46, July 1992.
2. IEEE 802.3u, IEEE 802.3z, IEEE 802.3x,
and IEEE Std. 802.3, fourth edition, 1993.
3. S. Sathaye, K.K. Ramakrishnan, and
H.Yang, FIFO design for a high-speed
network interface, Local Computer Networks, 1994. Proceedings, 19th Conference
on, pp. 2-11, 1994.
4. Switched Ethernet Controller, GT-48001
Rev. 1.1, Galileo Technology, Dec. 19,
1996.
5. J. L. Hennessy and D. A. Patterson,
Computer Architecture A Quantitative
Approach, 2nd Edition, Morgan Kaufmann
publishers, Inc. 1996.

6. A. Elaadnay, M. Singhal, and M.T. Liu,

Performance study of buffering within
switches in LANs, Computer Communications, Vol. 19, pp. 659-667, 1996.
7. Mark Ross, Andy Bechtolshe im, My T. Le,
and Jim O'Sullivan - Cisco System, Inc.
FX1000: A High Performance Single
Chip Gigabit Ethernet NIC, Compcon'97.
Proceedings, pp. 218-223, 1997.
8. C.H. Chen, M.H. Sheu, M.D. Shieh, T.S.
Lee, and M.C. Chen, Design and
Implementation of a 10/100 Mbps Ethernet
Switching Hub Controller, Proceeding of
the IEEE Asia Pacific Conference on
Communications, 1998.
9. Bill Hubbs, A Survey of Highly Integrated
Ethernet DataComm Devices, IEEE
Aerospace Conference, Vol. 4, pp. 489-498,
1998.
10. M. Birnbaum, and H. Sachs, How VISA
Answers the SOC Dilemma, Computer,
Vol.226, pp.42-50, June 1999.