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Seminar Report
EECS 5930
Instructor: Dr. Mansoor Alam
Muhtadi Choudhury
R01346931
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VLSI circuits
The University of Toledo
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Fig: The Effect of Reducing Number of Transmitted Coefficients on Image Visual Degradation
In this talk the first emphasis was exploring new techniques for the purposes of the robust
transmission of image data over packet-switched networks. He explained the important role
played by data compression and robust image transmission over packet-switched networks in
multimedia communication. Dr. Salari spoke about the method which is based on an
evolutionary algorithm that provides an optimized data packetization scheme for the
transmission of SPIHT coded bit streams. He showed the methods to obtain an enhanced
resolution (or high resolution) image from a sequence of low-resolution image frames. This
problem is known as super-resolution and considered to be very important in many image
processing applications including surveillance, satellite imaging, detection of small anomalies in
medical images and scientific imaging. Later he spoke about integrated recurrent neural network
(IRNN) which provides the advantages of both the Hopfield network and the multilayer feedforward network. To exploit the frequency content of the signal, an iterative scheme was
discussed in which the frequency content of the image is adaptively increased during the
reconstruction process of the high resolution images.
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FPGA Testing
I would like to work on the FPGA Testing. I would like to work on this under the
guidance of Dr. Niamat, Professor in the Department of Electrical Engineering & Computer
Science, University of Toledo.
Introduction:
In recent years FPGAs have made a major competitive presence in the market. The
computing systems designed using reconfigurable hardware is now used in many sensitive
applications. In such applications the security of the device is a major factor to be considered.
Unfortunately the FPGA hardware and software design flows lack a strong security. There are
many potential ways to attack a hardware device which can lead to stealing of confidential
information, modify the system to perform devious, unintended activities, perform denial of
service, or even destroy the system.
Field-programmable gate arrays (FPGAs) combine the programmability of processors
with the performance of custom hardware. As they become more common in critical embedded
systems, new techniques are necessary to manage security in FPGA designs. Because FPGAs can
provide a useful balance between performance, rapid time to market, and flexibility, they have
become the primary source of computation in many critical embedded systems. However,
techniques beyond bitstream encryption are necessary to ensure FPGA design security.
Fig: Demonstation to design a trustworthy FPGA which can be applicable for various
applications
Mant researchers worked on this using few techniques which include bit stream
techniques, cryptographic techniques and few other traditional techniques were also included.
They also worked using Physically Unclonable Functions for the authentication of the Ics.
The University of Toledo
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I would like to come forward and work further on these PUFs for the enhancements
technology. The main work relays on how PUFs can be more effectively used for this security
and authentication purposes. Thus the ultimate goal of our research is to enable a new class of
systems that are both reconfigurable and secure.
Advantages of PUFs:
1) Unique
2) Reliable
3) Low- Cost
4) Robust
Current Applications:
A number of applications depend on the protection of security-sensitive hardware:
1) Preventing unauthorized users from gaining access to the functionality of the integrated
circuits (ICs).
2) Smartcard systems, designers face the difficulty of preventing adversaries from hacking
and cloning the ICs embedded in these systems. Sometimes the ICs can be so vulnerable
to different types of attacks that the security of the ICs can be compromised with
relatively little effort.
Future Work:
Future work includes the design and fabrication of custom ICs to evaluate the
authentication approach across a large number of physical ICs and to experiment with the testtime and run-time detectability of various design alterations.
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