Documentos de Académico
Documentos de Profesional
Documentos de Cultura
KNCET, TRICHY
UNIT I
Analysis of Clocked Synchronous Sequential Networks (CSSN) - Modeling of CSSN- State Assignment and Reduction- Design of CSSN- Design of
iterative circuits-ASM chart- ASM Realization, Design of arithmetic Circuits for Fast adder-Array Multiplier.
Session
No.
Topics to be covered
Ref
1.
2.
Design of a Sequential parity checker, Analysis of Moore and Mealy sequential circuit by signal
tracing and timing charts.
3.
Method of constructing state table and state graphs for Moore and Mealy machines.
4.
5.
Guidelines for state assignments and reduction of state table using state assignment.
6.
Different types of State Assignment- Shared row, Multiple row and One hot state assignment.
7.
8.
9.
Algorithmic State Machine (ASM) Charts- Derivation and realization of ASM Chart.
10.
Design of Arithmetic circuits for Fast adder- Carry look ahead adder.
11.
Page No
Material Page
No
KNCET, TRICHY
UNIT II
Analysis of Asynchronous Sequential Circuit (ASC) - Flow Table Reduction-Races in ASC- State Assignment Problem and the Transition Table- Design of
ASC-Static and Dynamic Hazards- Essential Hazards- Design of Hazard free circuits- Data Synchronizers- Designing Vending Machine Controller- Mixed
Operating Mode Asynchronous Circuits. Practical issues such as clock skew, synchronous and asynchronous inputs and switch bouncing.
Session
No.
Topics to be covered
Ref
12.
13.
Design of Pulse mode sequential circuit- Primitive state table, state table reduction and state
assignment.
14.
Problems in Asynchronous Sequential Circuits Cycles, Critical race and Non- Critical race.
2,5
15.
2,5
16.
Design of Hazard free switching circuits- Static Hazard and Essential Hazard elimination.
2,5
17.
18.
Design of Vending machine controller- Description/ Specification, FSM design steps, State
diagram and state table.
19.
20.
Practical issues: Clock skew, synchronous and asynchronous inputs and switch bouncing.
Page No
Material Page
No
KNCET, TRICHY
UNIT III
Fault diagnosis: Fault Table Method- Path Sensitization Method- Boolean Difference Method- Kohavi Algorithm -Tolerance Techniques- The Compact
Algorithm. Design for testability: Test Generation- Masking Cycle - DFT schemes. Circuit testing fault model, specific and random faults, testing of
sequential circuits, Built in self test, Built in Logic Block observer (BILBO), Signature analysis.
Session
No.
Topics to be covered
Ref
21.
Fault Models- Stuck-at fault, Bridging fault, stuck-open fault and Temporary faults.
22.
Fault Diagnosis of Digital systems- Test generation for combinational logic circuits- Fault
Table Method and Path Sensitization method.
23.
24.
25.
26.
27.
28.
Design for Testability (DFT), DFT schemes, Circuit testing fault model: Specific and random
faults.
29.
30.
Page No
Material Page
No
KNCET, TRICHY
UNIT IV
PERFORMANCE ESTIMATION
Estimating digital system reliability, transmission lines, reflections and terminations, system integrity, network issues for digital systems, formal verifications
of digital system: model- checking, binary decision diagram, theorem proving, circuit equivalence.
Session
No.
Topics to be covered
Ref
31.
Estimating Digital System Reliability- Failure rates, Reliability and MTBF, System
Reliability.
32.
Transmission lines with infinite and finite length terminated with characteristic impedance,
Logic signal terminations.
33.
Network issues for digital systems: Noise, Time margin, Parasitic inductance and
capacitances.
34.
Digital System Integrity to minimize Noise Margin, Transmission Line effects, Signal Path
Return currents and power distribution.
35.
Design and Verification of Digital Systems: Design flow and RTL Verification.
36.
37.
38.
Page No
Material Page
No
KNCET, TRICHY
UNIT V
TIMING ANALYSIS
ROM timings, Static RAM timing, Synchronous Static RAM and its timing. Dynamic RAM timing, Complex Programmable Logic devices, Logic Analyzer
Basic Architecture, Internal Structure, Data display, Setup and Control, Clocking and Sampling.
Session
No.
Topics to be covered
Ref
39.
40.
Static RAM Internal Structure and Timing parameters for Read and Write operation of
static RAM.
41.
Synchronous SRAM- Internal Structure and its read and Write operation.
42.
43,44
45.
46.
47.
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Material
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KNCET, TRICHY