Documentos de Académico
Documentos de Profesional
Documentos de Cultura
23
24
ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007
Fig.1:
circuit
Fig.2: Important waveforms of the VFPFC by simulation (Assuming C2=C3=C/2 & C1=C4=C). Upper: Input voltage, Vin and current, Iin and output
voltage, Vo ; Lower: VFPFC diodes current, ID11D15
Value
Output capacitance = 54F
C1/C4 = 232F; C2/C3 = 116F
(1)
pP
T HD =
2
n=2 In,harmonics(rms)
I1,f undamental(rms)
(2)
25
Fig.3: Frequency spectra of input currents of conventional rectifier and VFPFC at 200W output power
The decrease in the harmonic distortion power and
the fundamental reactive power for the fixed average power (Pavg ) gives higher power factor, and since
there is rapid reduction in harmonic currents, THD
is lowered as a result.
Thirdly, the two small capacitors CIN1 and CIN2
serve to increase the conduction time of the input current by providing a path alternately for input current
to flow into the VFPFC before the input line voltage
rises above the VFPFC voltage and hence giving a
decrease in current distortion.
Fourthly, R2 and R3 are also used to suppress current distortion by limiting and smoothing the peak
diode charging current. Though efficiency would drop
a bit as power is being dissipated by those resistors,
the average power loss by R2 and R3 is only a tiny
fraction of input power. Experimental results in later
session proved the prediction is correct. Fig. 4 displays the THD and power factor at different power
levels for both rectifiers. The capacitors used in both
cases are according to 10% output voltage drop during discharge period.
3. 2 THD and PF of different combinations of
capacitors
There are ten possible categories of VFPFC capacitors combinations as shown in Table 1. For different
capacitors values the power factor and the THD%
are also different. The set of combination with highest power factor and lowest THD is obtained when
(C1=C4) (C2=C3). According to Fig. 5, the optimized capacitance values for highest power factor are
obtained when C2=C3=1 /2 C1=1 /2 C4.
4. CIRCUIT DESIGN OF VFPFC
4. 1 Effective VFPFC capacitance
The effective VFPFC capacitance Cef f is the combined capacitance of the VFPFC during the discharge period, which is equal to 3C/4. It is because
Cef f = (C1//C3) + (C2//C4), for C1=C4=C and
C2=C3=C/2. As discussed in Section 3.2, this set of
capacitors obtains the highest PF and lowest THD.
2 P0 (tholdup + tnormal )
(Vs2 Vf2 )
(3)
where Vs and Vf are the designated initial and final Cef f voltage, respectively, in the entire discharge
period. The discharge period is the time from t4 to
t6 of Fig. 2 (tnormal seconds) plus after the time t6
of Fig. 2 for tholdup seconds).
4. 2 Design curves of proposed VFPFC
Fig. 6 gives some design curves for choosing different combinations of optimized valley-fill effective
capacitance (Ceff) and resistance values (R2/R3) for
highest power factor under different output power
and power factor. These curves give only rough values
although they are obtained from a number of simulation results. Accuracy of these curves will be justified
by experimental results in Section 4.3.
To design the VFPFC, the output power and the
allowable output voltage drop during the discharge
period should be determined first. The holdup start
time should be chosen at a minimum value of VCef f
during normal operation, i.e. after tnormal . After
calculated Cef f from (3), then the input capacitors
CIN0, CIN1 and CIN2 values are chosen from Fig
6(a). After that, the current limiting resistors R2 and
R3 are selected from Fig. 6(b) according to desired
power factor. The efficiency of the VFPFC due to
these selected resistors are shown in Fig. 6(c).
26
ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007
Table 1:
power
Different combinations of VFPFC capacitances versus power factor and THD at 200W output
Vs =
2
2 110 = 103.71 V (take100V )
3
Vf = (1 0.15)Vs = 85V
Cef f =
2 50 (0.004 + 0.005)
= 352F
0.92(1002 852 )
4
Cef f = 469F (take470F )
3
Simulation and experimental results are given in
Table 2. The input voltage, the input current and the
output voltage of the experimental circuit are shown
in Figs. 7(a) and 7(b). The measured power factor of
the 50W VFPFC circuit is 0.95 and efficiency is 93%.
From some simulation and experimental results
shown above, there is very little difference between
them. Although the design curves cannot definitely
guarantee that what you see what you get, they are
good enough as a rough design guide.
C=
5. DISCUSSION
Since the proposed PFC circuit has no inductor,
which is the bulkiest and largest component for conventional PFC circuit like boost PFC converter, the
size of the proposed circuit can be comparable to the
existing ones. Beside, there is no switching loss associated with the circuit operation, the diode size can
be further reduced comparing to the same rating of
output power of active PFC circuits. Besides, normal standard diodes can be used as no switching is
involved, hence the cost may also reduce. In addition, due to the advancement of semiconductor packaging, we may use dual-diode in a single package such
as TO-220 for higher power application to minimize
space.
Since the main function of the PFC circuit is to im-
27
with the VFPFC, the THD% is reduced dramatically, and the power factor is raised to an acceptable
value. When compared with the LC filters for power
factor correction, the VFPFC yields acceptable PF
and THD% but with smaller size and weight. Design curves have been drawn to serve as a design tool
for choosing appropriate capacitance and resistance
values.
References
[1]
(a)
[2]
[3]
(b)
[4]
[5]
(c)
Fig.6: (a) Optimal values of VFPFC capacitances
of CIN0, CIN1 and CIN2 for highest PF and lowest THD for output power range between 50W and
300W; (b) Current limiting resistance of R2/R3 for
different power factor at different hold-up time requirement; (c) VFPFC efficiency according to resistances of R2/R3 selected from Fig. 6(b)
[6]
[7]
[8]
[9]
28
ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007