A Digital Mediaprocessor

Texas Instruments

DM310 Processor
A programmable architecture
for multimedia devices
Course:
Course: Architectures for multimedia systems

Politecnico di
Milano

Prof.: Silvano Cristina

Student:
Student: Zambon Diana (matr. 682069)

Texas Instruments DM310

Diana Zambon

Outline
9

Device characteristics

System Architecture:

Block-diagram

Example Data-flow

The subsystems
DSP
Coprocessor
ARM
Imaging/Video

SDRAM Central Memory

Interfacing

Modes of Operation

Performance and power consumption

References

Texas Instruments DM310

Diana Zambon

Characteristics

DUAL-CORE Architecture

TMS320c54x : TI programmable DSP (Digital Signal Processor)

ARM925 : RISC ARM9 Architecture

High integration

4 subsystems enabling advanced on-chip functionalities

High flexibility given to programmability

Programmable DSP and imaging co-processors

SDRAM central memory

Rich interfacing set (USB, MMC, SD, MS, UART,)

Low-power low-cost (given to high integration)

Targets any multimedia applications (digital cameras, DVR, .)

Texas Instruments DM310

Diana Zambon

System Architecture

Block Diagram
Imaging/video Subsystem
CCD/
CMOS
imager

CCD
controller

Preview
engine

Video
encoder

USBF USBH
GIO UART
MMC/SD
MemStick
WDT
External
Memory I/F
for CFC/SM
Flash/SRAM

OSD

DACs

SDRAM
Analog/
digital
video
output

Analog/digital,
digital/analog
serial
interface for
audio

DSP (C54x)
core

SDRAM/
memory
traffic
controller

128-Kbyte RAM

Image buffers
(31 K-entries x 16 bits)

ARM 925
16-Kbyte
instruction
cache
8 KByte data
cache

Imaging
accelerator
(iMX)

Variablelength
coder and
decoder

Quantization
and inverse
quantization

8-KByte RAM

ARM Subsystem

Texas Instruments DM310

DSP Subsystem

Coprocessor Subsystem

Diana Zambon

Example data flow: Video Encode

CCD/
CMOS
imager

2 from
Raw data

CCD
controller

Data
from 3SDRAM
is
CCD/CMOS
sensor

Preview
engine

coprocessor
subsystem
encoder
for
live
Preview
engine
in the SDRAM

Analog/
digital
video
output

DACs

processed
DSP
by OSD
&by
video
CCD
Controller
&&
Compressed
bitstream

Video
encoder

OSD

Data
from
SDRAM
read
and 4processed
is processed
by is

DSP (C54x)
core

SDRAM/
memory
traffic
controller

128-Kbyte RAM

Image buffers
(31 K-entries x 16 bits)

for MPEG4read
compressione
viewing
onto
and
iswritten
and
compressed
data
LCD
screen
SDRAM
bythe
the
on-chip
DMAs
isinwritten
back
to SDRAM
the ARM
subsystem

USBF USBH
GIO UART
MMC/SD
MemStick
WDT
External
Memory I/F
for CFC/SM
Flash/SRAM

and written
to a media card

Media
Card

ARM 925
16-Kbyte
instruction
cache

Imaging
accelerator
(iMX)

8 KByte data
cache

Variablelength
coder and
decoder

Quantization
and inverse
quantization

8-KByte RAM

Texas Instruments DM310

Diana Zambon

System Architecture - subsystems

Imaging/Video subsystem
Responible for communicating with external input devices (es. sensors CCMOS/CCD) and
external visualization devices (monitor NTSC/PAL, LCD).

CCD controller :

can
caninterface
interfacewith
withall
allCCD
CCDand
andCMOS
CMOSsensors;
sensors;
performs
pixel
processing.
performs pixel processing.

Preview Engine:

supports
supportsrealreal-time
time(30
(30f/f/s)s)NTSC/
NTSC/PAL
PALvideo
videodata
data
along
with
live
digital
zoom
along with live digital zoom

OSD (On- Screen Display) :

Video Encoder:

Texas Instruments DM310

can
cansimultaneously
simultaneouslydisplay
displaytwo
twovideo,
video,
two
twoOSD,
OSD,and
andone
onecursor
cursorwindows
windows

supports
supportsNTSC/
NTSC/PAL/
PAL/RGB
RGBvideo
videooutput
output(supports
(supports33
onchip
DACS)
and
also
digital
interface
for
on- chip DACS) and also digital interface forLCDs
LCDs
Diana Zambon

System Architecture - subsystems

DSP & Coprocessor

Performs all the SIGNAL PROCESSING COMPUTATIONS (audio / image / video)
TMS320C54x DSP with 128 KB on- chip RAM : the core of signal computations

8-way
8-waySIMD/vector
SIMD/vectorprocessor
processorwith
withdedicated
dedicatedmemories
memories
for
forprogrammable
programmableimage
imageand
andvideo
videoprocessing
processing

iMX - Image Accelerator

QIQ - Quantization and Inverse Quantization

programmable processor

Accelerates
Acceleratesseveral
severalimage/video
image/video
compression
compressionalgorithms
algorithms

Accelerates
AcceleratesHuffman
Huffmancoding
codingand
andcompression
compressionfor
for
the
theJPEG,MPEG,
JPEG,MPEG,H.
H.263
263standards
standards

VLCD - Variable-Length CoDec

DSP clock up to 72 MHz and coprocessor clock up to 144 MHz

Dedicated 31K x 16 bit buffer
Up to three threads of concurrency in the DSP&coprocessor subsystem

Texas Instruments DM310

Diana Zambon

System Architecture - subsystems

TMS32054x family
Modified Harvard 16-bit Multi-bus architecture
(3 data bus, 1 program instructions bus)

Simultaneous
Simultaneousacces
accestotoprogram
programinstructions
instructionsand
anddata
data

CPU with different independent functional units allows high parallelism

40-bit ALU including:
22reads
reads++11write
writeoperation
operationcan
canbe
beperformed
performed
a 40-bit adder + two 40-bit accumulators
ininaasingle
singlecycle
cycle
A 17 x 17 multiplier allows 16-bit signed or unsigned multiplication,
with rounding and saturation control - all in one instruction cycle

Filtering,
A second
40-bit transformate
adder
at output computations
ofcomputations
the multiplier and
Filtering,
transformate
andmatrices
matrices
=> MAC
operation, dualrequire
addition and
multiplication
multiplication
MAC
operationin :parallel.

multiplication require MAC operation :

A CSSU (Compare Select & Store Unit: fastens particular operations)
(op1
(op1op2)
op2)

crucial
crucialparallel
parallelinstructions
instructions
exec
execinin11instruction
instructioncycle
cycle

Dual-Acces 128 Kbyte on-chip RAM *;

On-chip ROM;

26 Memory-Mapped Registers (from HEX 0000 to 005F); (sprs039c.pdf page 39)

Other on-chip peripherals;
Higly specialised instruction-set (arithmetic,logic,L/S, I/O, control,move instructions)
72 MHz clock frequency
Single Cycle Fixed-Point Instruction Execution Time from 25 to 10 ns; MIPS from 40 to 120(a).
*single access on 548/549

Texas Instruments DM310

Diana Zambon

System Architecture - subsystems

ARM
Realizes the bulk of the system level tasks
(including hosting any operating system)
ARM controls all the on-chip blocks except the DSP subsystem
(can communicate with DSP if needed)
32-bit RISC-processor core (32-bit instructions)
ARM925 with

4/64
4/64set-associative
set-associativecache
cache
Random
Random/ /round-robin
round-robinreplacement
replacement
algorithm
algorithm

16 KB I- cache,
8 KB D- cache, and a
dedicated 8 KB of SRAM

Write-back
Write-backand/or
and/orwrite-through
write-through
32-bit ALU + 32x32 MAC unit + barrel shifter
16 registers used as source and destination operands and as address registers
Data-dependent multiply operations: between 2 and 7 cycles to complete an operation
Clock frequency up to 120 MHz
Texas Instruments DM310

Diana Zambon

System Architecture - subsystems

ARM architecture
37 32-bit integer registers (16 available)
Pipelined (ARM9: 5 stages)
Caches are separate for instructions and data - Harvard (ARM9)
8 / 16 / 32 -bit data types
32-bit long instruction word
36 Instruction Formats

Fig. ARM9TDMI Pipeline (comparison-ARM7-ARM9-v1.pdf)

Texas Instruments DM310

Diana Zambon

System Architecture - subsystems

Peripherals

(ARM subsystem)

Several peripheral blocks are integrated into the ARM subsystem

Supports storage interfaces to several media cards such as
Compact Flash (CF)

Smart Media (SM)

Secure Digital (SD)

Multi-Media Card (MMC)

Memory Stick (MS)

Can support 2 cards at the same time.

Integrated USB host & function, serial I/ F, UART, and timers
Glue less interface to 8-, 16-, and 32- bit external hosts
Support for Flash (Nand/ Nor) and external SRAM
Multiple on- chip DMAs for data movement between peripherals
without ARM intervention

Texas Instruments DM310

Diana Zambon

System Architecture

SDRAM & Memory Traffic Controller

Several sources and sinks to SDRAM exist in the DM310 processor
All requests are routed through the SDRAM/ Memory traffic controller
Optimized to realize optimum throughput and latency via buffering
Programmable priority scheme to each requestor in the system
Several latency intolerant blocks (for functional correctness) exist in the chip

Texas Instruments DM310

Diana Zambon

Modes of Operation
Still image capture
Live preview mode
Still image playback
Video encode
Video decode/ playback
Audio encode
Audio decode
Photo printing

Texas Instruments DM310

Diana Zambon

Performance and power consumption

Supports multiple applications and file formats (MPEG- 1, 2, 4, WMV, H. 263,
H. 264, JPEG, JPEG2K, M- JPEG, MP- 3, AAC, WMA, )
Real- time (30 f/ s) MPEG- 1, 4 video encode at CIF resolution (352 x 288)
Real- time (30 f/ s) MPEG- 4 video decode at VGA resolution (640 x 480)
One- second shot- to- shot delay for processing a raw 6-megapixel image
including JPEG compression
Three PLL let several clock frequencies run on different portions of the chip
Consumes 250 mW in the video preview mode (whole chip)
Consumes 400 mW while performing video encoding or video decoding
Consumes 400 mW while performing still capture of an image (processes 6
Mega pixels/ second including JPEG compression)
Texas Instruments DM310

Diana Zambon

References

DM310

TI TMS320c54x DSP

Anatomy of a portable digital

mediaprocessor

TMS320C54x, TMS320LC54x,
TMS320VC54x FIXED-POINT
DIGITAL SIGNAL PROCESSORS

www.elet.polimi.it/upload/silvano/
mioweb5/FilePDF/ARCMULTIMEDIA/DM310_IEEEMicro2004.pdf

TMS320DM310 DSP - Product

Bulletin

focus.ti.com/pdfs/vf/vidimg/dm310pb.pdf

focus.ti.com/lit/ds/sprs039c/sprs039c.pdf

Programmable DSP Platform for

Digital Still Cameras

Performance of the
ARM9TDMI and ARM9E-S
cores compared to the
ARM7TDMIcore
www.arm.com/pdfs/comparison-arm7arm9-v1.pdf

General purpose processors ARM ARM9

http://www.bdti.com/procsum/arm9.htm

focus.ti.com/lit/an/spra651/spra651.pdf

Texas Instruments TMS320C5x

Other links:

www.hotchips.org/archives/hc15/2_Mon/7
.ti.pdf

DSP-introduzione

TI Portable Media Device block

diagram

Texas Instruments Launches

Innovative DSP-based Solution
Offering Industry's Highest
Performance for Portable
Multimedia Appliances

ARM

TMS320DM310 - A Portable
Digital Media Processor

www.harvard.co.uk/home/article_details.a
sp?id=4720

www.bdti.com/procsum/ti320c5x.htm

garga.iet.unipi.it/II/DSP_INTRO.pdf

www.arm.com

ARM920T-System-on-Chip Open
OS Processor
www.arm.com/pdfs/DVI0024B_920t_po.pdf

Texas Instruments DM310

focus.ti.com/docs/solution/folders/print/267
.html

Linux OS for DM310

www.montereylinux.com/datasheets/
montereylinuxDM310-ds-20040106.pdf

Data flow example

www.hotchips.org/archives/hc15/2_Mon/7.t
i.pdf

Diana Zambon