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Computer-System Structure
Each device controller is in charge of a particular device type (disk drive, video
displays etc).
I/O devices and the CPU can execute concurrently.
Each device controller has a local buffer.
CPU moves data from/to main memory to/from local buffers
I/O is from the device to local buffer of controller.
Device controller informs CPU that it has finished its operation by causing an
interrupt.
2.1
2.2
External Interrupts
Interrupt Handler
2.3
Separate segments of code determine what action should be taken for each
type of interrupt
2.4
Traps
To start an I/O operation, the CPU loads the appropriate registers within the
device controller.
The device controller examines the contents of these registers and determines
what action to take and then performs the action.
Device controller informs CPU that it has finished its operation by causing an
external interrupt.
A disk block read example:
For disk reads, the controller reads the block (one or more sectors)
from the derive serially, bit by bit, until the entire block is in the
controller internal buffer.
It then performs a checksum to verify that no read errors have
occurred.
The controller sends an interrupt. When the OS starts running, it can
read the disk block from the controllers buffer a byte or a word at a
time by executing a loop, with each iteration reading one byte or word
from the controller device register and storing it in the main memory.
2.5
I/O Structure/Methods
2.6
Recall that with interrupt driven I/O, the CPU can request data from an I/O
controller one byte/word at a time which wastes the CPU time.
DMA is a scheme which allows block of data transfer from the device to the
memory without the intervention of the CPU.
After setting up buffers, pointers, and counters for the I/O device by the CPU,
the device controller transfers blocks of data from buffer storage directly to
main memory without CPU intervention.
2.7
Only one interrupt is generated per block, rather than the one interrupt per
byte.
The OS can only use DMA if the hardware has a DMA controller.
The basic operation of the CPU is as follows:
A user program (or OS) requests data transfer
The OS finds a buffer from a pool of buffers (a buffer is 128 to 4096
bytes long depending on the device type).
A device driver sets the DMA controller registers to use the appropriate
source and destination addresses and transfer length.
A command to I/O controller is also issued telling it to read data from
the disk to its internal buffer and verify the checksum.
When the Valid data is in the controllers buffer, DMA can begin.
The DMA controller initiates the transfer by issuing a read request over
the bus to the disk controller.
The disk controller writes the data to the memory and sends an
acknowledgement to the DMA.
The DMA increases the memory address to use and decrements the
byte count. If the byte count is still greater than 0, the process is
repeated.
When the whole block is transferred, the DMA controller interrupts the
CPU to let it know that the transfer is complete.
If both the DMA controller and the CPU want to access the memory at
the same time, the CPU is made to wait this is called cycle stealing.
Note that the processor is only involved at the beginning and end of the
transfer
2.8
Storage Structure
Main memory only large storage media that the CPU can access directly.
Secondary storage extension of main memory that provides large
nonvolatile storage capacity.
Magnetic disks rigid metal or glass platters covered with magnetic recording
material
Disk surface is logically divided into tracks, which are subdivided into
sectors.
The disk controller determines the logical interaction between the device
and the computer.
Storage Hierarchy
Storage-Device Hierarchy
2.9
Caching
Dual-Mode
Operation
Interrupt/fault
use
r
monit
or
set user mode
Trap instruction is
used to switch to
monitor mode
2.10
I/O Protection
Memory Protection
Must provide memory protection at least for the interrupt vector and the
interrupt service routines.
2.11
2.12
CPU Protection
A user program must be prevented from getting stuck in an infinite loop and
never returning control to the OS. To accomplish this, a timer is used.
A Timer interrupts computer after specified period to ensure operating system
maintains control.
Timer is decremented every clock tick.
When timer reaches the value 0, an interrupt occurs.
Timer commonly used to implement time sharing.
Time also used to compute the current time.
Load-timer is a privileged instruction.
2.13