WE6C-6

Efficiency-Enhancing Technique: LDMOS Power Amplifier Using

Dual-Mode Operation Design Approach
Younkyu Chung, Yuanxun Wang, Dal Ahn, and Tatsuo Itoh
Department of Electrical Engineering, University of California, Los Angeles
405 Hilgard Ave., Los Angeles, CA 90095

Absiracf - This paper presents an input power-dependent

high-efficieney LDMOS power amplifier by employing a
dual-mode operation design approach. The proposed
amplifier scheme provides two dimerent operating modes
depending on the power level: low or high input power
modes. By controlling the number of operating amplifiers in
each mode, the efficiency of the amplifier at low power level
is substantially improved. Four single stage LDMOS power
ampliliers with Motorola MRF 21030 were incorporated
with a dual-mode input power divider and output power
combiner. In the proposed operation, either one or fonr
amplifiers were activated. The measurement results show a
M dBm saturated output power and 40 % PAE in high input
power mode, when four amplifiers are active. By switching
the operation to the low input mode, when the input power
was relatively low, a 5 % increase in PAE was obtained.
Indk Terms
LDMOS, power-added eniciency (PAE),
coupled-line coupler, switch, characteristicimpedance.

1. Introduction

In RF and microwave systems, several power

amplifiers have often been incorporated with an input
power divider and an output power combiner to provide
sufficient output power. The total amount of output power
is directly proportional to the number of operating
amplifiers. Occasionally, however, the required power
level is much lower than the total output power h m all
the activated amplifiers. Since the desirable power level is
fairly low, the other amplifiers consume unnecessary DC
power. This results in lowering the overall efficiency of
the entire power amplifier structure. In such a system with
multiple power amplifiers, generally, the efficiency is
poor when the input power is low.
To solve these problems several design approaches
have been demonstrated, such as Doherty, dual-path, and
others [1-4]. Doherty amplifiers employ an auxiliary and a
peak amplifier [I-21. In [3], dual-path power amplifier
scheme was investigated. Two different size GaAs high
electron mobility transistors (HEMTs) were integrated
with path-control switches. Depending on the input power
level, a HEMT of desired size was selected by the control
switches. Recently, a new power combining scheme was

reported by authors' research goup [4]. Under the

condition that the output power was dynamically changing,
the number of operating amplifier was controlled. The
combining method provided proper matching conditions
at different operating conditions with different number of
amplifiers in operation. This approach was accomplished
by utilizing the different output impedance characteristics
of field-effect transistors (FETs) when they are biased to
the class-AB or pinch-off [S-61.
Silicon laterally diffised metal-oxide semiconductor
(LDMOS) bas often been used for base-station RF power
amplifiers. This is because of the simplicity, maturity, and
excellent RF performance such as high gain, good
linearity, and high output power of the LDMOS transistor
[7-91.
In this paper, a new efficiency-enhancing amplifier
design technique is presented by utilizing a dual-mode
operating approach. This method was applied to the
design of a high-power and high-efficiency LDMOS
power amplifier for a 2.1 GHz F
G base-station application.
For this desired operation, a new dual-mode input power
divider using coupled-lie couplers is proposed and
successfully demonstrated. A dual-mode output power
combiner was realized by means of using a LDMOS
device nature at the pinch-off bias condition. The
implemented input power divider and output power
combiner at 2.12 GHz were incorporated with Motorola
MRF 21030 LDMOS power amplifiers.
11. Dual-mode power amplifier

In the proposed power amplifier configuration, the

number of operating amplifiers is controlled depending on
the input power level to avoid unnecessary DC power
consumption. As depicted in Fig. 1, the dual-mode power
amplifier consists of a dual-mode input power divider,
four LDMOS power amplifiers, and a dual-mode output
power combiner. In this work, either one or four
amplifiers are activated at each mode.

859
0-7803-8331-1/04/$20.00 0 2M)4 IEEE

2004 IEEE MTI-S Digest

POUT

respectively. The electrical length of the coupler is 90.at

the designed 2.12 GHz.
For all couplers, either the coupling or the isolation
tenninal relative to the input terminal where RF signa1
comes is connected to the GND through mode-control
switches, SI through S.,, The other side of each coupltx
remains open. Based on the operating principle of the
coupler at this condition [lo-111, each coupler behaves
like a conventional transmission line when the switch is
OFF. The equivalent characteristic impedance of this
coupler is given by

Fig. 1 The proposed dual-mode power amplifier

wIliigluation
L

When input power is relatively low, one amplifier (PA,)

is on, while the others do not operate. In this low poweroperating mode, the proposed divider delivers all input
power to the PA, and the output power from the PA, is
directed to the fmal output load with minimum loading
effect due to the other branches. However, as the input
power increases towards the saturated power level of PAI,
the divider and combmer switch to the high input power
mode. This mode enables all input power to be equally
distributed to amplifiers, PA, through P&.
In Fig. 2, the detailed schematic of the dual-mode input
power divider is shown, It is composed of two quarteransmission sections with characteristic impedance
and four 3 dB couplers.

From the designed Z

, and &, it is clear th
equivalent characteristic impedance is equal to
These equivalent and conventional lines satisfy the input
matching conditions.
However, when the switches from S2 to S, turn ON, thi:
reference points A and B in the Fig. 2 become high
impedance points [10-11]. Notice that the switch SI
always remains OFF. Therefore, the input RF signal
propagates through only the top branch in the Fig.2. The
matching conditions of this divider at this mode are
accomplished by the 2 quarter-wave length transmission
lies. In Fig.3, the measured S-parameters are shown in
low input power mode. The measnrement was done when
the switches, SI through &, are turned ON, causing all
input power to he directed into port 2 only.

3:;

Frequency [QM]

Fig. 3 Measured S-parameters of the dual-mode

power divider (low input power mode)
O

I-

Fig. 2 Schematic of dual-mode input power divider

The even and odd mode characteristic impedances (Z,

and J,Z
,
of the couplers are set to 120.2 and 20.6 R,

but

Note that the implemented mode-control switches show

ahout 4-6 Q and Ik R ON and OFF resistances,
respectively. At the designed 2.12 GHz, 1.5 dB insertion
loss was measured. The loss occurs because of the finite
ON and OFF resistances that cause loading effects f

860

non-operating brancbes. The Agilents ADS simulation

results show that the loss can be enhanced significantly by
reducing the ON resistance by 1-2 Q. When the divider
operates in a different mode, the high input power mode,
about -6 dB insertion loss between the input and output
ports was achieved with good matchig performance.
In [4], the device characteristic of a FET, which is
biased to the pinchaff operating region, was utilized.
When a FET is biased in the pinch-off, the input and
output impedances are nearly reactive with only a small
resistive value [5-61. This power combining technique is
extended to the LDMOS power amplifier for the dualmode power combiner in this work [9]. When only PAI is
operating at the low input power mode, the output
impedances of PA24 were tmnsfomed to high impedance
values. Therefore, all output power from the PA, is
delivered to the output load with minimum loading effect
due to the other brancbes.

implemented on the substrate with the same parameters as

the dividedcombiner. The fabricated divider, four
LDMOS power amplifiers, and combiner were connected
together. The entire dual-mode LDMOS power amplifier
is shown in Fig. 4.
For the large-signal measurement, a driver amplifier in
conjunction with a synthesizer was used for sufficient
input power. The drain bias voltage, V, was set to 28 V,
while the gate voltage, VOswas set to 3.75 V for normal
operation and 0 V for pincb-off operation. In Fig. 5, the
measured output power (Pou) and gain of the dual-mode
LDMOS power amplifier is shown.

111. Experimental Results and Discussions

The dual-mode input power divider and output power

combiner was designed at 2.12 GHz. The circuit was
implemented on the 0.787 mm-thick RTDuroid substrate
with dielectric constant of 2.33. The Hittite HMC174MS8
and the RN2 RCP-2Gl5M were utilized for the mode
control switch and the coupler in the power divider,
respectively. The Motorola MRF 21030 and its thermal
model in Agilents ADS were used for the four single
stage power amplifiers.
The measured Pd and gain performance for the dualmode operation was compared with the one and four
amplifier operating cases. In the dual-mode operation, the
critical input power level at which the operating mode was
changed was set to the input 1 dB compression point of
the single LDMOS power amplifier. At the low input
power level, the power amplifier operates in the low
power mode so that it starts to follow one amplifier
operating case. Once the power level reaches the critical
point, the operating mode is switched to the high power
mode. The input power is divided into four brancbes
equally in the desired way described in Section 11. The
equal amount of output power fiom PA14 is combined
together thmugb the proposed combiner. Note that in this
mode, four LDMOSs are biased to class-AB with gate
voltage of 3.75 V. The measured gain in the low and high
power modes are 10 dB and 12 dF3, respectively. Due to
the 1.5 dB insertion loss of the input power divider in low
power mode, the gain in this mode is smaller than that in
the high power mode causing a step at the transition
between operating modes. This inconsistency in gain can

Fig.4 Photograph of dual-mode LDMOS power amplifier

The bias points were set to VDs=28 V and VGs=3.75 V for

normal class-AB operation. The amplifier was
86 1

be improved by means of reducing the ON and OFF

resistances of the mode control switches.
The measured power-added efficiency of the dual-mode
LDMSO power amplifier is shown in Fig. 6.

the operating mode, 5 % improvement in PAE was

achieved.
Acknowledgement
This work was supported by UC MICRO under contract
No.02-029. The authors would like to thank B. Vassilakis,
Dr. A. Khanifar, and F. Cortes from PowerWave
technologies, CA for the support of high power
measurement setup.

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Fig. 6 Measured PAE perfolmance for the dual-mode

LDMOS power amplifier.
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N.Conclusion
The dual-operating mode approach has been proposed
to design a high efficiency power amplifier. This design
method minimizes the DC power consumption. For the
desired operation, a dual-mode input power divider was
implemented by using the coupled-line coupler. The
matching condition was accomplished through the
designed Z, and Zoo. The combined output power
combiner provides the proper matching conditions for the
two different modes. From the dual-mode LDMOS power
amplifier, 10 dB and 12 dB gains were obtained in low
and high input power modes, respectively. By switching

1998,
[IO] Y. Chung D. Ahn,Y. Wang, and T. Itoh, A new input

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Filters, Impedance-Mafching Networks, and Coupling
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