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# INTERNATIONAL ISLAMIC UNIVERSITY MALAYSIA

## END OF SEMESTER EXAMINATION

SEMESTER 1, 2013/2014 SESSION
KULLIYYAH OF ENGINEERING
Programme

: ENGINEERING

Level of Study

: UG 1

Time

Date

: 31/12/13

Duration

: 3 Hours
Section(s)

: 1-8

## Course Code : ECE 1312/ECE 1231

Course Title

: Electronics

This Question Paper Consists of Eight (8) Printed Pages (Including Cover Page) With
Five (5) Questions.
INSTRUCTION(S) TO CANDIDATES

## DO NOT OPEN UNTIL YOU ARE ASKED TO DO SO

Total mark of this examination is 100.
This examination is worth 45% of the total assessment.

## Any form of cheating or attempt to cheat is a

serious offence which may lead to dismissal.
1

Electronics

## Q.1 [20 marks]

(a)

A full wave rectifier circuit is shown in Fig. 1(a) with the primary voltage, v1 = 220
V(rms) and turns ratio, N1:N2 = 20:1. Assume each diode cut-in voltage, V = 0.65 V.
(5+2 marks)
(i) What is the peak value of the output current if R = 1 k ?
(ii) What is the Peak Inverse Voltage (PIV) rating of each diode?

N1:N2

Fig. 1(a)

(b) Fig. 1(b) shows a multiple diode circuit. If each diode cut-in voltage,
V = 0.65 V, determine the diode current, ID1 and the output voltage , V o .
(7 marks)

Fig. 1(b)

Electronics
(c)

## ECE 1312 / ECE 1231

The clamper circuit is shown in Fig. 1(c) has an input sinusoidal voltage,
v I =6 sin ( t ) V(rms). Sketch the output voltage, v O against time, t. Assume that
diode cut-in voltage, V = 0.65 V.
(6 marks)

Fig. 1(c)

3

Electronics

(a)
(i)
(ii)

## ECE 1312 / ECE 1231

The voltage transfer characteristic and its BJT circuit are shown in Fig. 3(a). Assume
that VBE (on) = 0.7 V, VCE(sat) = 0.2 V and = 120.
Find the value of the resistor, RB by assuming VI = 1.9 V.
Sketch the output load line for the circuit.

(5 marks)
(5 marks)

RB

Fig. 3(a)
(b)

Consider the circuit as shown in Fig. 2(b). Determine IBQ, ICQ and VCEQ for =100.
Sketch the output load line and Q-point by assuming, I C =I E .
(6+4
marks)

Fig. 2(b)

Electronics

## Q.3 [20 marks]

(a)

A common-emitter amplifier has output voltage -2.4 V when its input voltage is 250 mV.
The collector resistance of the amplifier 1.5k is changed to 2.5k, what is the new gain
of the amplifier? Consider that ro = .
(4 marks)

(b)

Draw the small-signal equivalent circuit and calculate the voltage gain of the circuit is
shown in Fig. 3. (b). Assume that the transistor and circuit parameters:
= 100, VCC = 12 V, VBE(on) = 0.7 V, RC = 6 k, RB = 50 k, VBB = 12 V and
VT = 0.026 V.
(8 marks)

Fig. 3(b)
(c)

Draw the small-signal equivalent circuit for the common collector amplifier as shown in
Av
Fig. 3(c). Derive the equation for voltage gain
of the circuit.
(8 marks)

Fig. 3(c)

Electronics

(a)

(b)

## Fig. 4(b) shows a NMOS circuit with parameters

Kn = 0.2 mA/V2. Determine the values of VGS, VS and VD.

(4 marks)
VTN = 0.6 V and
(6 marks)

Fig. 4(b)

(c)

Design an n-channel MOSFET circuit is as shown in Fig. 4(c) has the following
specifications: VDD = 5 V, VSS = -5 V, Kn= 0.48 mA/V2 and VTN = 1.5 V. Assume that, IDQ =
0.6 mA, VDSQ= 3.5 V and the MOSFET is operating in the saturation region.
(10 marks)

Fig. 4(c)

Electronics

## Q.5 [20 marks]

(a) Determine the small-signal voltage gain, input and output resistances of a
common-source amplifier as shown in Fig. 5(a). The circuit parameters are,
VDD = 4.5V, RD = 4.7 k, R1 = 120 k, R2 = 47 k and RSi = 4 k. Transistor
parameters are Kn = 0.6 mA/V2 and = 0.025 V-1
(6 marks)

Fig. 5(a)
(b) Fig. 5 (b) shows an n-channel MOSFET logic gate.
(i) Draw the corresponding truth table of the logic gate.
(ii) Identify the function of the circuit (AND/OR/NOR/NAND gate).

Fig. 5(b)

(3 marks)
(1 marks)

Electronics

## (c) An op-amp inverting amplifier circuit is shown in Fig. 5(c).

(5 +5 marks)

(i) Derive the close-loop voltage gain of the inverting amplifier, Av = - R2/R1.
(ii) Determine the values of R1 and R2, if the gain Av = -10, and the current in the
feedback resistor is 10 A when the output voltage is 5.0 V.

Fig. 5(c)

Electronics

## Useful equations for nMOSFET:

2
2
I D K n [2VGS VTN VDS VDS ] I D K n VGS VTN

VA

1 r VA
o
I CQ

Where,

g m 2 K n I DQ

gm
ro

I CQ
VT

V
VA
r T
I CQ
I CQ

I D I s (e

vD
VT

1)