Altera FPGA Tools Tutorial

1. Introduction:
The main purpose of this laboratory is to let you become familiar with the Altera FPGA design
tools. In this tutorial, we will from the very beginning to download the free version design tool, to
use the functional simulator, Altera modelsim, to observe the waveform, and then we use
Quartus II CAD tool to synthesize our design. We can optimize our design, based on compilation
result.

2. Learning Objectives:
Learn how to download the free version Altera FPGA design tools
Learn how to use Altera modelsim to observe the waveform
Learn how to use Altera Quartus II CAD tool to synthesis the design
Learn to observe the compilation results, and do the optimization

3. Download Altera FPGA Tools:

First, enter www.altera.com. Click and enter the Download Center at the top of the website:
https://www.altera.com/download/dnl-index.jsp. Here you can see the softwares we are to
download. Now you have two options: download the Altera installer, or download individual files.
Here I choose to download the Altera installer.

Figure 3-1
See the screenshot above, I circled the download link for the Altera installer. Click the
corresponding block to download it. You might be asked to register and sign in before
downloading, just register your own user ID and password.
As the download is finished, you can run it. Click Next button without exception. When you see

the screenshot below(Figure 3-2), you can specify the installation directory: If you have
downloaded the individual files, you should select the item Specify the Installation Files
Directory, otherwise select Download Installation Files from the Internet. Since we havent
downloaded any individual files, we select to download from the Internet, then click Next.

Figure 3-2

Figure 3-3

Figure 3-4

Figure 3-5
Then you can see Figure 3-3. You can choose your own working directory now, and then click
Next.

Now you can choose the individual files that you want. See Figure 3-4. Choose Quartus II Web
Edition and ModelSim-Altera Starter Edition for free. Click Next till the end. When you see the
figure shown in Figure 3-5, you can wait for the download of the individual files. It takes some
time.
When the download finishes, it will be installed automatically. Finally you can just hit the finish
to exit the download and installation.

4. Tutorials on Altera ModelSimWaveform simulation:

First of all, find modelsim.exe under ./altera/modelsim_ase/win32aloem, double click to open.

Figure 4-1
Figure 4-2
Follow the path File->New->Project to create a new project. As is shown in Figure 4-1, we can
specify the Project Name, Project Location. Leave the default library name and settings directory
as it is. Then click OK. Then we can see Figure 4-2. We can create new files, or add existing files,
or create simulations here. Now we could skip this step, if we havent created our Verilog files.

Then we can see the figure, as is shown in Figure 4-3. We can do the equivalent thing as shown in
Figure 4-2 by following the path Project->Add to Project->., shown in Figure 4-4. Now we select
to add a new file, and see the command window shown in Figure 4-5. We define the file name as
counter.v, and choose the file type as Verilog, and leave the folder as it is. Click OK, and we can
see the file counter.v in the file list. Double click to edit it. You can find the file content here:
http://www.ece.ncsu.edu/asic/share/2011/Tut1_Sim/counter.v. Try to understand the code, and
then copy to your own disk.
Now the Verilog code for the counter has been created. However, we still need to write a
testbench to test its function. So we create another new file named test.v. We can do it in the
same step as we created the counter.v, but now you will be shown how to load the existing file
from your own disk. Select Project->Add to Project->Existing Files., click browse and then find
the corresponding test.v in your hard disk, choose the file type as Verilog, and copy to the project
directory, all shown in Figure 4-7.

Figure 4-3

Figure 4-4

Figure 4-5

Figure 4-6

Figure 4-7

Figure 4-8

Figure 4-9
Now all the Verilog files are prepared, we need to compile them. Find an arbitrary room and right
click your mouse cursor, you will see the screenshot as Figure 4-8. Select Compile->Compile All.
You will see the compile result in the command line, i.e., 2 compiles, 0 failed with no errors..
See Figure 4-9.

Figure 4-10

Now Start simulation window, under the work directory, double click test_fixture, the simulation
window starts. See Figure 4-10.

Figure 4-11
Here is the general view of the simulation window, shown in Figure 4-11. Make sure the
connections between your modules are correct, or you will have problems to get this window. In
the left window, all your modules are shown. When you choose a module, all the signals in this
module would show in the right window.

Figure 4-12
Then Setup the waveform window. In the left window, right click the u1 and choose Add->To
Wave->All items in region to add signals to the waveform window. You can also choose the
particular signals you want to add to the waveform window.
Here is the Waveform window, seen Figure 4-13. In the command line, you can specify the
simulation time, and run the simulation. In this demo, we set the simulation time as 100ps. Type
in run 100ps. If you dont want to specify the simulation time and let it simulate according to

the test_fixture, you can also type in run all. After the simulation, you will see the waveforms
for all the signals, shown as Figure 4-15. Hit F in the waveform window to fit the figure to the
proper size. In fact, you can also specify the radix for the inputs/outputs, also shown in Figure
4-15. Right click the parameter, follow Radix->Binary/Octal/Hexadecimal/. to change the form.
You can also try some other functions or characters as you want, such as Zoom In, Zoom Out, and
so on.

Figure 4-13

Figure 4-14

Figure 4-15
Thats the general tutorial for Altera ModelSim.

5. Tutorials on Altera QuartusFPGA synthesis:

After you ensured the correctness of the waveform function for your RTL design, you still need to
see how your hardware descreption code could be converted into the gate level circuit, how fast
the clock frequency could be, and how much resource it will take from the FPGA board. If the
performance is not satisfied, you still need some further optimization. Altera Quartus II FPGA tool
is such a CAD tool that helps you synthesize your design, showing your compilation result after
the synthesis. Now lets focus on how to use Altera Quartus II.
5.1 Establish a New Project:
First of all, find quartus.exe under ./altera/quartus/bin, double click to open. Then you should
see the display in Figure 5-1.
Then we start a new project, by clicking on File->New Project Wizard. Then you can see the
pop-up of the introduction window. Click Next, you will see the window shown in Figure 5-2. The
working directory will currently be set to whatever directory you had started Quartus II
from. You may change this if you wish. The project must have a name, which is usually the same
as the top-level design entity that will be included in the project. Choose counter as the name for
both the project and the top-level entity, as shown in Figure 5-2. Click Next. This will take you to
the window in Figure 5-3.

Figure 5-1

Figure 5-2

Figure 5-3

If you had design files already coded, you would be adding them here (Browse using and the
click Add). Make sure that all your design files are in the working directory. Note: You can
always add design files later too and not necessarily at this step. So now we skip to the next step,
which leads you to Figure 5-4, i.e., Family and Device Settings.
In this page, we have to specify the type of device in which the design will be implemented. We
could let the Quartus II software to select a specific device in the family, but for now we will
specify the device explicitly. Set the Family to Cyclone II as shown below, choose the
EP2C35F672C6 device, and click Next. The window that opens up now is the EDA tools window
where the user can specify any third-party tools that should be used. We do not need any other
tools, so leave all the boxes unchecked, as is shown in Figure 5-5 and click Next. This should take
you to the Summary of the Project Settings window in Figure 5-6. Press Finish, which returns
to the main Quartus II window, but with counter specified as the new project, in the display title
bar.

Figure 5-4

Figure 5-5

Figure 5-6
5.2 Design entry using Verilog Code:
At this point we have 2 options:
a) Simply add the design counter.v by going to Project->Add/Remove Files in Project
b) Learn to use the Quartus II Text Editor to code a design. (Section 5.2.1)
5.2.1 Using the Quartus II Text Editor
You can skip this section if you prefer to use some other text editor to create the Verilog source
code file or if you are simply using the supplied design.
Select File->New, choose Verilog HDL File, and click OK. This opens the Text Editor window. The
first step is to specify a name for the file that will be created. Select File->Save As to open the
pop-up box. In the box labeled Save as type choose Verilog HDL File. In the box labeled File name
type counter.v. Put a checkmark in the box Add file to current project. Click Save, which puts
the file into your working directory and leads to the Text Editor window. We still use the file
counter.v that has been used in Altera ModelSim. Enter the Verilog code in the Text Editor
window, and then save the file.
At this point your design file should be added to the project. To see the files that are in your
project, go to the Project Navigator window on the left top corner of the Quartus II interface
and click on the Files tab and expand the Device Design Files folder. You can also see what files
are on your project by going to Assignments->Settings and clicking on the item Files.

6. Compiling the design:

The Quartus II tool analyzes the code, synthesizes the circuit and generates an implementation of
it for the target device. All this is done by the application program called the Compiler.
Run the Compiler by selecting Processing > Start Compilation, or by clicking on the toolbar icon
that looks like a purple triangle. As the compilation moves through various stages, its progress is
reported in a window on the left side of the Quartus II display. Successful (or unsuccessful)

compilation is indicated in a pop-up box that says Full Compilation was successful.
Acknowledge it by clicking OK, which leads to the Quartus II display in Figure 6. In the message
window, at the bottom of the figure, various messages are displayed. In case of errors, there will
be appropriate messages given.
The errors and warnings would be given, if there exist. Here is the compilation result of mine,
shown in Figure 6-1:

Figure 6-1
As is mentioned, this is a free version of Quartus, and thus some of the characters are disabled,
just like the Parallel compilation. So we can ignore the warnings regarding this, i.e.,
Warning(20028). The warning, regarding the subscription license, could also be ignored, due to
the constraints of the free version. As for the Warning(169174), since we are only simulating
using this tool, without the FPGA board, its acceptable. Same reason for Warning (306006), since
we havent the FPGA board. So we cant physically load the output pins, so its okay for this
warning.

7. Timing Analysis and Optimization:

As we finish the compilation, we could see the report generated.
Figure 7-1 shows how we could see the timing report. Lets come to the column Compilation
Report, and click on the small arrow before TimeQuest Timing Analyzer. We can see lots of
options, shown in Figure 7-2. If we extend the slow model, we could see the setup summary for
the worst case setup timing, and its slack; similarly, if we extend the fast model, we could see the
hold summary for the best case hold check, and its slack. Under both column of slow model and

fast model, we could check the sub-title named worst-case timing path, to see the timing report,
sorted in ascending order of the slack, for all paths between each two flip-flops. Then we could
optimize the one with smallest slack.

Figure 7-1

Figure 7-2

Figure 7-3

If there are some slack, you can quicken your clock period by clicking on Assignment->TimeQuest
Timing Analyzer Wizard, shown in Figure 7-3. You can create a clock at the very beginning, or
adjust the clock period after viewing the timing report. Then click Next, we could also specify the
parameters such as tsu/thold, tco, tpd according to the specific system. So based on the timing
report, we can do the iteration by quicken the clock, and recompile, and check the slack in timing
report, and then decide if we should continue the iteration above.
You may also be curious about the column Analyze and Synthesis. In fact, if you extend the
column, it gives you the basic information of the analyze and synthesis result for your design,
including the summary, resource usage, optimization results and so on so forth, offering you
some statistics for your design after synthesis.