Intel 8085

6EC: MICROPROCESSOR AND APPLICATIONS
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Comparison of large, mini and microcomputers.

Architecture of a microcomputer based on the Von Neumann model of a stored
program computer.
History of microprocessors.
Architecture of Intel 8085, the 8-bit microprocessor.
Programming model of Intel 8085.
Introduction to the instruction set of Intel 8085.
Instruction format and addressing modes for Intel 8085.
Instruction timings of Intel 8085: Definition of terms: the instruction cycle and the
machine cycle. The five machine cycles of Intel 8085 and their timings: the
Opcode fetch cycle timings, the memory/IO read cycle timings and the
memory/IO write cycle timings.
Basic timing diagram of Intel 8085.
Timing diagram for each instruction in the instruction set of Intel 8085.
Interrupt and hold timings of Intel 8085.
Introduction to the 8-bit microprocessors from the other manufacturers such as
Zilog and Motorola:
(i)
Architecture of Z80.
(ii)
Introduction to the instruction set of Z80.
(iii)
Architecture of MC6800.
(iv)
Introduction to instruction set of MC6800.
Introduction to Intel 8086, the 16-bit P: Architecture of Intel 8086.
Micro-operations that are carried out in the T-cycles of an instruction.
Interfacing devices: tri-state devices: unidirectional and bi-directional buffers,
latches and decoders.
Memory types: ROM and its types; RAM and its types.
Basic memory cell structure: ROM cell structures; RAM cell structures.
Basic memory modules: ROM module; RAM module.
Memory addressing schemes:
(i)
linearly decoding scheme;
(ii)
fully decoding scheme.
Memory interfacing techniques: interfacing a ROM module.
Timing analysis of ROM interfacing.
Memory interfacing techniques: interfacing a RAM module.
Timing analysis of RAM interfacing.
I/O structures:
(i)
programmed I/O
(ii)
DMA structure
(iii)
I/O mapped I/O
(iv)
memory mapped I/O
(v)
interrupt driven I/O
Intel 8085 I/O structure.
Need for the interrupt structure.
Differences between an interrupt and a subroutine.
Differences between an interrupt and DMA.
Hardware interrupts and software interrupts.
30. The interrupt structure of Intel 8085.

31. The programmable interrupt controller (PIC) 8259.
32. Introduction to assemblers: Types: (i) one-pass assembler, (ii) two-pass
assembler, (iii) macro assembler, (iv) cross assembler, (v) resident assembler and
(vi) meta assembler & some assembler directives: ORIGIN (ORG), EQOATE
(EQU), DEFINE BYTE (DB), DIFINE WORD (DW), TITLE, PAGE, SPACE,
END and LIST.
33. Programs using Intel 8085.
34. Debugging programs.
35. Microprocessor-based systems: temperature control, speed control & traffic
control.
6E1 MICROPROCESSOR LAB - I

CYCLE I
1. 8-bit addition using ADD reg and ADD mem
instructions
2. 8-bit subtraction using SUB reg and SUB mem
instructions
3. 8-bit multiplication using ADD and DAD instructions
4. 8-bit division using SUB instruction
5. 16-bit addition using ADD and DAD instructions
6. 16-bit subtraction using DAD instruction
7. 8-bit direct binary multiplication
8. Sorting and searching programs
(i) Largest/Smallest member in a given array of
numbers
(ii) Arranging a given array of numbers in
ascending/descending order
CYCLE II
9. Word display left/right entry.
10. Reading a key press polling/interrupt method.
11. Reading and displaying a key press polling and
interrupt.
12. Code conversion Hex to decimal and decimal to Hex
conversions.
13. Time delay routine waveform generation.
14. Speed control program running a stepper motor at
different speeds.
15. Traffic control program.
Architecture of the 8-bit microprocessor, 8085:
RST 6.5
RST 7.5
TRAP
RST 5.5
INTR
INTA
SOD
Interrupt Control
SID
Serial I/O Control
Multiplexer
IR (8)
ACC (8)
TR (8)
Instruction
Decoder
A
L
U
Register Select
FR (8)
W (8)
Z (8)
B (8)
C (8)
D (8)
E (8)
H (8)
L (8)
Stack Pointer (16)

Program Counter (16)
Increment/Decrement
Address Latch
Timing and Control
CLKOUT
RD
READY
WR
S0 S1 IO / M HOLD
RESETIN
HLDA
Address
Buffer (8)
Data/Address
Buffer (8)
A8 A15
AD0 AD7
RESETOUT
Architecture of 8085: 8085 is an 8-bit microprocessor. The architecture of 8085 has the
following blocks:
(I) Arithmetic/Logic Unit (ALU): The Arithmetic/Logic Unit (ALU) performs the socalled the arithmetic operations such as addition and subtraction and logical operations such
as AND and OR.
(II) Register unit: The register unit of 8085 has various general-purpose and specialpurpose registers.
The register unit of 8085 has seven, 8-bit general-purpose registers, namely A, B, C,
D, E, H and L, which are visible to the user i.e., that are accessible through software
instructions. The register A is often referred to as the accumulator. Most arithmetic/logical
operations and all input/output operations involve the accumulator as one of the operands. All
these 8-bit registers, except the accumulator, can be paired to use as 16-bit registers. The
possible pairs are BC, DE and HL. Some general-purpose registers such as W and Z are
invisible to the user i.e., are not accessible through software instructions.
The register unit of 8085 has two, 16-bit special-purpose registers, namely the
program counter (PC) and the stack pointer (SP). The program counter holds the address of
the next instruction byte to be fetched. It is incremented by one each time an instruction byte
is fetched unless modified by a (1-byte or 3-byte) call or an interrupt. The stack pointer holds
the address of the current location in a block of memory called the stack.
The register unit of 8085 has one more 8-bit register called the flag register. The flag
register reflects the change in the status of the accumulator due to an arithmetic operation or a
logical operation. It consists of five flags, namely the sign (S) flag, the zero (Z) flag, the
auxiliary carry (AC) flag, the parity (P) flag and the carry (C) flag.
The sign flag is set whenever the most significant bit (i.e., the 8th bit) of the result of
any arithmetic or logical operation (except rotation) is 1.
The zero flag is set whenever the result of any arithmetic or logical operation (except
rotation) is zero.
The auxiliary carry flag is set whenever the low-order nibble of the result of an
arithmetic operation overflows i.e., whenever there is a carry from the 4th bit to 5th bit due to
an arithmetic operation. All the logical operations except rotation either sets or resets the
auxiliary carry.
The parity flag is set whenever the result of any arithmetic or logical operation
(except rotation) has even number of 1s.
The carry flag is set whenever the result of an arithmetic operation overflows. All the
logical operations except rotation reset (clear) the carry. The rotation either sets or resets the
carry.
(III) Control and timing unit: The control and timing unit generates various control
and timing signals for the proper operation of the microprocessor and data transfer between
the microprocessor and memory and input/output devices. The various control and timing
signals generated by the control and timing unit of 8085 are as follows:
(1) ALE: Address Latch Enable: This is an active high and outgoing signal. This
signal begins (goes high) at the beginning of the first clock cycle of a machine cycle,
indicating that the data bus is to carry the low-order byte of an address. The falling edge of
this signal is used to latch the low-order address byte. The ALE pin is never tri-stated.
(2) RD: ReaD: This is an active low and outgoing signal. When this pin goes low, it
indicates that the microprocessor is to read from the memory location or the peripheral
device, which it has just selected. This pin is tri-sated during HALT, HOLD and RESET
modes.
(3) WR: WRite: This is an active low and outgoing signal. When this pin goes low, it
indicates that the microprocessor is to write into the memory location or the peripheral
device, which it has just selected. This pin is tri-sated during HALT, HOLD and RESET
modes.
(4) IO/ M: InputOutput/Memory: This is an outgoing signal. When this pin goes high,
it indicates that the microprocessor is to carry out an input/output related operation. When
this pin goes low, it indicates that the microprocessor is to carry out a memory related
operation. This pin remains high or low until the respective operation is completed. This pin
is tri-stated during HALT, HOLD and RESET modes.
(5) S0 and S1: Status signals: These two signals along with the IO/M signal indicates
various machine cycle status as shown below:
IO/M
S0
S1
Opcode fetch
M emory read
Memory write
IO read
IO write
Interrupt acknowledge
HI
Halt
HI
Hold
HI
Reset
Status
HI= Hig h Im ped anc e sta te; X= unsp ecified.
The IO/M, S0 and S1 signals begin at the beginning of the first clock cycle of a machine
cycle and remain stable throughout the machine cycle.
(6) READY: Ready: This is an active high and incoming signal. If this pin goes high
during a (IO or memory) read or write cycle, then the microprocessor will wait for an integral
number of clock cycles before completing the current read or write cycle.
(7) HOLD: Hold: This is an active high and incoming signal. When this pin goes
high, it indicates that another master is requesting the use of the address and data buses. Upon
receiving this signal, the microprocessor will relinquish the control over the bus after
completing the current bus transfer. (It may still continue any internal process.) The
microprocessor can resume the control over the bus as soon as this pin goes low. Therefore,
this pin must remain high as long as the requesting party uses the bus.
(8) HLDA: HoLD Acknowledge: This is an active high and outgoing signal. Upon
receiving the HOLD signal, the microprocessor generates this HLDA signal and indicates the
requesting party that the bus will be free from the next clock cycle. The microprocessor
removes this HLDA signal as soon as the HOLD pin goes low. The microprocessor resumes
the control over the bus one half cycle after the HLDA goes low.
(9) RESET IN: Reset in: This is an active low and incoming signal. When this pin
goes low, the program counter is cleared to zero and the Interrupt Enable and HLDA flipflops are reset (disabled). The data, address and control bus lines are tri-stated. The
microprocessor remains in this state as long as this pin is low. As this signal is asynchronous,
the processor's internal registers and flags are altered with unpredictable data.
(10) RESET OUT: Reset out: This is active high and outgoing signal. Upon being
reset, the microprocessor generates this signal. This lasts an integral number of clock cycles.
This is synchronized with the processor's clock.
(IV) Interrupt system of 8085: The interrupt system of 8085 has two types of
interrupts: (1) the hardware interrupts and (2) the software interrupts.
(1) Hardware interrupts: The interrupt system of 8085 has the following hardware
interrupts:
(i) TRAP: TRAP is a non-maskable hardware interrupt i.e., it cannot be disabled
through a software instruction. Hence TRAP has the highest priority. This interrupt transfers
the execution control to the memory location 0024H. In order for the microprocessor to
service this interrupt, TRAP must remain high until the microprocessor responds to it.
(ii) RST7.5, 6.5 & 5.5: ReSTart7.5, 6.5 & 5.5: These are maskable hardware
interrupts i.e., they can be disabled through software instructions. They have the priority in
the order they are shown. These interrupts transfer the execution control to the memory
locations 003CH, 0034H and 002CH, respectively.
These four interrupts are called the vectored interrupts, as they transfer the execution
control to predetermined memory locations.
(iii) INTR: INTerrupt Request: This is also a maskable hardware interrupt. This has
the lowest priority. When INTR is high, the P completes the execution of the current
instruction and generates an INTA signal. Then the P expects either a 1-byte CALL (RST0
through RST7) or a 3-byte CALL on the data bus. The INTA signal can be used to enable an
external hardware, which has been designed to provide the Opcode for the required CALL
instruction on the data bus. If a 3-byte CALL instruction is used, then the P generates two
additional INTA cycles in order to fetch all the three bytes of the CALL instruction. This is a
non-vectored interrupt, as it does not transfer the execution control to any predetermined
memory location.
(2) Software interrupts: The interrupt system of 8085 has eight software interrupts,
namely RST0, RST1, RST2, RST3, RST4, RST5, RST6 & RST7. These are vectored
interrupts as they transfer the execution control to the predetermined memory locations,
0000H, 0008H, 0010H, 0018H, 0020H, 0028H, 0030H & 0038H respectively. When any of
these instructions is executed, the microprocessor calculates the required vector address
internally as 8 times the respective vector number (i.e., the numbers 0 through 7).
(V) Serial data transfer: The pins SID and SOD are used for the serial data transfer in
and out of the microprocessor.
Programming model of 8085: The following figure shows the programming model of 8085.
< --- 8 b its --->< --- 8 b its --->
Flags
C
ACC
B
D
E
L
< --- 16 b its --->
Program Counter
Stac k Pointe r
The programming model of 8085 has seven, 8-bit general-purpose registers, namely
A, B, C, D, E, H and L and two, 16-bit special-purpose registers, namely the program counter
(PC) and the stack pointer (SP).
The register A is often referred to as the accumulator. Most arithmetic/logical
operations and all input/output operations involve the accumulator as one of the operands. All
these 8-bit registers, except the accumulator, can be paired to use as 16-bit registers. The
possible pairs are BC, DE and HL.
The program counter holds the address of the next instruction byte to be fetched. It is
incremented by one each time an instruction byte is fetched unless modified by a (1-byte or
3-byte) call or an interrupt. The stack pointer holds the address of the current location in a
block of memory called the stack.
The register unit of 8085 has one more 8-bit register called the flag register. The flag
register reflects the change in the status of the accumulator due to an arithmetic operation or a
logical operation. It consists of five flags, namely the sign (S) flag, the zero (Z) flag, the
auxiliary carry (AC) flag, the parity (P) flag and the carry (C) flag.
The sign flag is set whenever the most significant bit (i.e., the 7th bit) of the
accumulator is set due to an arithmetic operation or a logical operation.
The zero flag is set whenever the accumulator is cleared to zero due to an arithmetic
operation or a logical operation.
The auxiliary carry flag is set whenever the low-order nibble of the accumulator
overflows due to an arithmetic operation or a logical operation.
The parity flag is set whenever the content of the accumulator has even number of 1s
due to an arithmetic operation or a logical operation.
The carry flag is set whenever the accumulator overflows due to an arithmetic
operation or a logical operation.
Instruction format for 8085:

Any instruction in the instruction set of 8085 has two parts: (i) the mnemonic and (ii) the
operand.
The mnemonic in an instruction would be an English-like work implying the operation to
be carried out by the instruction.
Any instruction carries out an operation on a source data, translating it into a destination
date. Thus, any instruction has a source of data and a destination of data specified in it. Some
instructions themselves imply either the source or the destination and require that the other by
specified by the user. Some other instructions themselves imply both the source and the
destination. The source or destination specification in an instruction is often referred to as the
operand.
For the execution of any instruction, the user must provide a machine-representable code
(or simply a machine code) that is meaningful only to the P, telling it the operation to be
carried out and the operand.
The machine code for an instruction in the instruction set of 8085 may have one or two or
three bytes. Thus, there are one-byte, two-byte and three-byte instructions in the instruction set
of 8085.
Any one-byte instruction requires only one byte for its machine code, including both the
opcode and the operand.
Ex: MOV A, B.
Any two-byte instruction requires two bytes for its machine code, the first byte being the
opcode and the second, the operand. The operand is either an 8-bit data or an 8-bit port address.
Ex: MVI A, 05H.
Any three-byte instruction requires three bytes for its machine code, the first byte being the
opcode, the second the low-byte of the operand and the third the high-byte of the operand. The
operand is either a 16-bit data or a 16-bit memory address.
Ex: LDA 5105H.
Addressing modes of 8085:
The way of specifying the source or destination of data in an instruction is often referred to
as the addressing mode.
The 8085 P has five addressing modes, namely, (i) the direct addressing mode, (i) the
register direct addressing mode, (iii) the register indirect addressing mode, (iv) the immediate
addressing mode and (v) the implied addressing mode.
In the direct addressing mode, the operand is an 8-bit or a 16-bit address that contains the
(source or destination) data.
Ex: LDA 5105H; INOFH.
In the register direct addressing mode, the operand is a register or a register pair that
contains (source or destination) the data.
Ex: ADD B; DAD B.
In the register indirect addressing mode, the operand is a register pair that contains the
address of (source or destination) data.
Ex: LDAX B; INR mem.
In the immediate addressing mode, the operand is an 8-bit or a 16-bit (source) data. Ex:
MVI B, 05H; LXI H, 5105H.
In the implied addressing mode, there is no operand. Both the source and the destination of
data are implied by the instruction itself.
Ex: CMA; STC.
I. Data transfer instructions:

SlNo.
Instruction
1.
MOV r1, r2
2.
MOV r, mem
3.
MOV mem, r
4.
MVI r, data8
5.
MVI mem, data8
6.
LXI rp, data16
7.
LDA addr16
8.
STA addr16
9.
LHLD addr16
10.
SHLD addr16
11.
LDAX rp
Function
( r2 ) ( r1 )
Move data from r2 to r1. The content of the register r2 is copied
to the register r1.
( mem ) ( r ) or (( HL )) ( r )
Move data from mem to r. The content of the memory location,
whose address is stored in the HL pair, is copied to the register r.
The address of the memory location mem should be stored in the
HL pair before using this instruction.
( r ) ( mem ) or ( r ) (( HL ))
Move data from r to mem. The content of the register r is copied
to the memory location, whose address is stored in the HL pair.
The address of the memory location mem should be stored in the
HL pair before using this instruction.
data8 ( r )
Move data immediate to r. The 8-bit data specified in the
instruction is transferred to the register r.
data8 ( mem ) or 8-bit data (( HL ))
Move data immediate to mem. The 8-bit data specified in the
instruction is transferred to the memory location, whose address
is stored in the HL pair.
data16 ( rp)
Load register pair rp immediate with data16. The 16-bit data
specified in the instruction is transferred to the register pair rp.
( addr16 ) ( A )
Load accumulator from addr16. The content of the memory
location, whose address (addr16) is specified in the instruction,
is copied to the accumulator A.
( A) ( addr16 )
Store accumulator in addr16. The content of the accumulator A
is copied to the memory location, whose address (addr16) is
specified in the instruction.
( addr16 ) ( L ) & ( addr16+1 ) ( H )
Load HL pair direct from addr16. The content of the memory
location, whose address (addr16) is specified in the instruction,
is copied to the register L and the content of the next memory
location is copied to the register H.
( L ) ( addr16 ) & ( H ) ( addr16+1 )
Store HL pair direct in addr16. The content of the register L is
transferred to the memory location, whose address (addr16) is
specified in the instruction and the content of the register H is
copied to the next memory location.
(( rp )) ( A )
Load accumulator indirect from (rp). The content of the memory
location, whose address is stored in the register pair rp, is copied
to the accumulator A.
( A ) (( rp ))
Store accumulator indirect in (rp). The content of the
12.
STAX rp
accumulator A is copied to the memory location, whose address
is stored in the register pair rp.
( HL ) ( DE )
13.
XCHG
Exchange HL pair with DE pair. The content of the HL pair is
exchanged with the content of the DE pair.
II. Arithmetic operation instructions:
SlNo.
Instruction
Function
(r)+(A)(A)
1.
ADD r
Add r. The content of the register r is added to the content of the
accumulator A and the result is stored in the accumulator A.
( mem ) + ( A ) ( A ) or (( HL )) + ( A ) ( A )
Add mem. The content of the memory location, whose address is
2.
ADD mem
stored in the HL pair, is added to the content of the accumulator
A and the result is stored in the accumulator A.
data8 + ( A ) ( A )
Add data8 immediate. The 8-bit data specified in the instruction
3.
ADI data8
is added to the content of the accumulator A and the result is
stored in the accumulator A.
( r ) + ( A ) + ( CF ) ( A )
Add r with carry. The content of the register r is added to the
4.
ADC r
content of the accumulator A along with the carry bit and the
result is stored in the accumulator A.
( mem ) + ( A ) + ( CF ) ( A ) or
(( HL )) + ( A ) + ( CF ) ( A )
Add mem with carry. The content of the memory location,
5.
ADC mem
whose address is stored in the HL pair, is added to the content of
the accumulator A along with the carry bit and the result is
data8 + ( A ) + ( CF ) ( A )
Add data8 immediate with carry. The 8-bit data specified in the
6.
ACI data8
instruction is added to the content of the accumulator A along
with the carry bit and the result is stored in the accumulator A.
(A)(r)(A)
Subtract r. The content of the register r is subtracted from the
7.
SUB r
content of the accumulator A and the result is stored in the
accumulator A.
( A ) ( mem ) ( A ) or ( A ) (( HL )) ( A )
Subtract mem. The content of the memory location, whose
8.
SUB mem
address is stored in the HL pair, is subtracted from the content of
the accumulator A and the result is stored in the accumulator A.
( A ) data8 ( A )
Subtract data8 immediate. The 8-bit data specified in the
9.
SUI data8
instruction is subtracted from the content of the accumulator A
and the result is stored in the accumulator A.
( A ) ( r ) ( CF ) ( A )
Subtract r with carry. The content of the register r along with
10.
SBB r
the carry bit is subtracted from the content of the accumulator A
( A ) ( mem ) ( CF ) ( A ) or
( A ) (( HL )) ( CF ) ( A )
Subtract mem with carry. The content of the memory location,
11.
SBB mem
whose address is stored in the HL pair, along with the carry bit
is subtracted from the content of the accumulator A and the
result is stored in the accumulator A.
( A ) data8 ( CF ) ( A )
Subtract data8 immediate with carry. The 8-bit data specified in
12.
SBI data8
the instruction along with the carry bit is subtracted from the
accumulator A.
(r)+1(r)
13.
INR r
Increment r. The content of the register r is increased by one.
( mem ) + 1 ( mem ) or (( HL )) + 1 (( HL ))
14.
INR mem
Increment mem. The content of the memory location, whose
address is stored in the HL pair, is increased by one.
(r)1(r)
15.
DCR r
Decrement r. The content of the register r is decreased by one.
( mem ) 1 ( mem ) or (( HL )) 1 (( HL ))
16.
DCR mem
Decrement mem. The content of the memory location, whose
address is stored in the HL pair, is decreased by one.
( rp ) + 1 ( rp )
17.
INX rp
Increment register pair rp. The content of the register pair rp is
increased by one.
( rp ) 1 ( rp )
18.
DCX rp
Decrement register pair rp. The content of the register pair rp is
decreased by one.
( rp ) + ( HL ) ( HL )
Double add register pair rp. The content of the register pair rp
19.
DAD rp
is added to the content of the HL pair and the result is stored in
the HL pair.
Decimal adjust accumulator. (1) If the low-order byte of the
accumulator is greater than 9 or if ACF is set (logic 1), 06 is
added to accumulator. (2) If the high-order byte of the
20.
DAA
accumulator is greater than 9 or if CF is set (logic 1), 60 is added
to accumulator. (3) If both ACF and CF are set (logic 1), 66 is
added to accumulator.
III. Logical operation instructions:
SlNo.
Instruction
Function
( r ) AND ( A ) ( A )
AND r. The content of the register r is ANDed with the content
1.
ANA r
of the accumulator A and the result is stored in the accumulator
A.
2.
ANA mem
3.
ANI data8
4.
XRA r
5.
XRA mem
6.
XRI data8
7.
ORA r
8.
ORA mem
9.
ORI data8
10.
CMP r
11.
CMP mem
12.
CPI data8
13.
RLC
( mem ) AND ( A ) ( A ) or (( HL )) AND ( A ) ( A )

AND mem. The content of the memory location, whose address
is stored in the HL pair, is ANDed with the content of the
data8 AND ( A ) ( A )
AND data8 immediate. The 8-bit data specified in the instruction
is ANDed with the content of the accumulator A and the result is
( r ) EXOR ( A ) ( A )
EXOR r. The content of the register r is EXORed with the
accumulator A.
( mem ) EXOR ( A ) (A ) or (( HL )) EXOR ( A ) ( A )
EXOR mem. The content of the memory location, whose address
is stored in the HL pair, is EXORed with the content of the
data8 EXOR ( A ) ( A )
EXOR data8 immediate. The 8-bit data specified in the
instruction is EXORed with the content of the accumulator A
( r ) OR ( A ) ( A )
OR r. The content of the register r is ORed with the content of
the accumulator A and the result is stored in the accumulator A.
( mem ) OR ( A ) ( A ) or (( HL )) OR ( A ) ( A )
OR mem. The content of the memory location, whose address is
stored in the HL pair, is ORed with the content of the
data8 OR ( A ) ( A )
OR data8 immediate. The 8-bit data specified in the instruction
is ORed with the content of the accumulator A and the result is
(A)(r)
Compare r. The content of the register r is subtracted from the
content of the accumulator A and (i) if (A) < (r) CF is set (1), (ii)
if (A) > (r) CF is reset (0) or (iii) if (A) = (r) ZF is set (1).
( A ) (mem ) or ( A ) (( HL ))
Compare mem. The content of the memory location, whose
address is stored in the HL pair, is subtracted from the content of
the accumulator A and (i) if (A) < (mem) CF is set,
(ii) if (A) > (mem) CF is reset or (iii) if (A) = (mem) ZF is set.
( A ) data8
Compare data8 immediate. The 8-bit data specified in the
instruction is subtracted from the content of the accumulator A
and (i) if (A) < (data8) CF is set, (ii) (A) > (data8) CF is reset or
(iii) (A) = (data8) ZF is set.
( An ) ( An+1 ); ( A7 ) ( A0 ); ( A7 ) ( CF )
Rotate accumulator left. The accumulator A is rotated left bit
wise. The CF is set if A7=1 and vice versa.
CF
D7
D6
D5
D4
D3
D2
D1
D0
( An+1 ) ( An ); ( A0 ) ( A7 ); ( A0 ) ( CF )
Rotate accumulator right. The accumulator A is rotated right bit
wise. The CF is set if A0=1 and vice versa.
14.
RRC
D7
D6
D5
D4
D3
D2
D1
D0
CF
( An ) ( An+1 ); ( A7 ) ( CF ); ( CF ) ( A0 )
Rotate accumulator left through carry. The accumulator A is
rotated left through the carry bit wise.
15.
RAL
CF
RAR
D7
D6
D5
D4
D3
D2
D1
D0
( An+1 ) ( An ); ( A0 ) ( CF ); ( CF ) ( A7 )
Rotate accumulator right through carry. The accumulator A is
rotated right through the carry bit wise.
16.
D7
D6
D5
D4
D3
D2
D1
D0
CF
17.
Compliment accumulator. Compliment the accumulator bit wise.
CMA
18.
Compliment carry. Compliment the carry flag.
CMC
19.
Set carry. Set the carry flag.
STC
IV. Branch operation instructions:
Instruction
Function
SlNo.
Jump unconditionally. The program sequence is transferred to
1.
the memory location, whose address (addr16) is specified in the
JMP addr16
instruction.
Conditional JUMP instructions
2.
JC addr16
3.
JNC addr16
4.
JZ addr16
5.
JNZ addr16
Jump on carry. The program sequence is transferred to the

memory location, whose address (addr16) is specified in the
instruction if CF=1.
Jump on no carry. The program sequence is transferred to the
instruction if CF=0.
Jump on zero. The program sequence is transferred to the
instruction if ZF=1.
Jump on no zero. The program sequence is transferred to the
instruction if ZF=0.
Jump on plus. The program sequence is transferred to the

6.
JP addr16
instruction if SF=0.
Jump on minus. The program sequence is transferred to the
7.
JM addr16
instruction if SF=1.
Jump on parity even. The program sequence is transferred to the
8.
JPE addr16
instruction if PF=1.
Jump on parity odd. The program sequence is transferred to the
9.
JPO addr16
instruction if PF=0.
Call. The program sequence is transferred to the memory
10.
CALL addr16
location, whose address (addr16) is specified in the instruction.
CALL instruction: When the CALL instruction is executed, the content of the stack pointer is
decreased by one and the high-order byte of the address of the next instruction is stored in the
memory location pointed by the stack pointer. Then, the content of the stack pointer is again
decreased by one and the low-order byte of the address of the next instruction is stored in the
memory location pointed by the stack pointer. This looks as if PUSH PC was executed. That is
( PC )H (( SP-1 )); ( PC )L (( SP-2 )) & ( SP ) - 2 ( SP )
Conditional CALL instructions
11.
12.
13.
14.
15.
16.
17.
18.
CC addr16
CNC addr16
CZ addr16
CNZ addr16
CP addr16
CM addr16
CPE addr16
CPO addr16
Call on carry.
Call on no carry.
Call on zero.
Call on no zero.
Call on plus.
Call on minus.
Call on parity even.
Call on parity odd.
Return. The program sequence is transferred (returned) to the
19.
RET
main program. This is the last instruction in a subroutine.
RET instruction: When the RET instruction is executed, the content of the memory location
pointed by the stack pointer is transferred to the program counter as the low-order byte of the
address of the next instruction to be executed. Then, the content of the stack pointer is
increased by one and the content of the memory location pointed by the stack pointer is
transferred to the program counter as the high-order byte of the address of the next instruction.
Finally, the content of the stack pointer is again increased by one. This looks as if POP PC was
executed. That is
(( SP )) ( PC )L ; (( SP+1 )) ( PC )H & ( SP ) + 2 ( SP )
Conditional RET instructions
20.
21.
22.
23.
24.
25.
RC
RNC
RZ
RNZ
RP
RM
Return on carry.
Return on no carry.
Return on zero.
Return on no zero.
Return on plus.
Return on minus.
26.
27.
RPE
RPO
Return on parity even.

Return on parity odd.
( HL ) ( PC )
Load PC with HL. The content of the HL pair is copied to the
program counter PC.
V. Stack, I/O & machine control instructions:
SlNo.
Instruction
Function
( rp )H (( SP-1 )); ( rp )L (( SP-2 )) & ( SP ) - 2 ( SP )
Push register pair rp. The high-order byte of the register pair rp
is transferred to the memory location, whose address is the
1.
PUSH rp
content of the stack pointer minus one (SP-1) and the low-order
byte of the register pair rp is transferred to the memory location,
whose address is the content of the stack pointer minus two
(SP-2).
( A ) (( SP-1 )); ( flag register ) (( SP-2 ))
( SP ) - 2 ( SP )
Push processor status word. The content of the accumulator A is
2.
PUSH psw
transferred to the memory location, whose address is the content
of the stack pointer minus one (SP-1) and the content of the flag
register is transferred to the memory location, whose address is
the content of the stack pointer minus two (SP-2).
(( SP )) ( rp )L; (( SP+1 )) ( rp )H & ( SP ) + 2 ( SP )
Pop register pair rp. The content of the memory location, whose
address is the content of the stack pointer SP, is transferred to
the low-order register of the register pair rp, the content of the
3.
POP rp
memory location, whose address is the content of the stack
pointer SP plus one, is transferred to the high-order register of
the register pair rp and the content of the stack pointer SP is
increased by two.
(( SP )) (A ); (( SP+1 )) ( flag register ) &
( SP ) + 2 ( SP )
Pop processor status word. The content of the memory location,
whose address is the content of the stack pointer SP, is
4.
POP psw
transferred to the accumulator A, the content of the memory
location, whose address is the content of the stack pointer SP
plus one, is transferred to the flag register and the content of the
stack pointer SP is increased by two.
( HL ) ( SP )
5.
SPHL
Load SP with HL. The content of the HL pair is copied to the
stack pointer SP.
( L ) (( SP )) & ( H ) (( SP+1 ))
Exchange HL with (SP). The content of the register L is
exchanged with that of the memory location, whose address is
6.
XTHL
the content of the stack pointer SP and that of the register H is
exchanged with that of the memory location, whose address is
the content of the stack pointer plus one (SP+1).
( addr8 ) ( A )
7.
IN addr8
Input from addr8. The content of the port, whose address
28.
PCHL
8.
OUT addr8
9.
EI
10.
DI
11.
HLT
12.
NOP
(addr8) is specified in the instruction, is transferred to the

accumulator A.
( A ) ( addr8)
Output to addr8. The content of the accumulator A is copied to
the port, whose address (addr8) is specified in the instruction.
Enable interrupt. The maskable interrupt system is enabled
following the execution of the EI instruction. Interrupts are
not recognized during the execution of the EI instruction.
Disable interrupt. The maskable interrupt system is disabled
following the execution of the DI instruction. Interrupts are
not recognized during the execution of the DI instruction.
Halt. The processor finishes the execution of the current
instruction and stops any further execution. The address and data
buses are placed in the high impedance state. An interrupt or
reset is required for the microprocessor to exit from the Halt
state.
No operation. No operation is performed.
Read interrupt mask. The instruction reads the status of
interrupts 7.5, 6.5, 5.5 and serial input data bit and the
accumulator is loaded with an 8-bit data with the following
interpretations:
D7 D6 D5 D4 D3 D2 D1 D0
13.
RIM
D7=serial input data (status of SID pin).
D6, D5, D4=interrupt pending flags for RST7.5, 6.5 & 5.5;
pending if bit=1.
D3=interrupt mask enable status; masking enabled if bit=1.
D2, D1, D0=interrupt mask status of RST7.5, 6.5 & 5.5; masked
(reset) if bit=1.
Set interrupt mask. The instruction sets the interrupts 7.5, 6.5,
5.5 and serial data output interpreting the content of the
accumulator as follows:
D7 D6 D5 D4 D3 D2 D1 D0
14.
SIM
The 8085 interrupt system:

SlNo.
Interrupt
1.
TRAP
D7=serial output data. This bit is sent out on SOD pin if SOE=1.
D6=serial output enable; enabled if bit=1.
D5=irrelevant.
D4=reset (mask) RST7.5; reset (masked) if bit=1; this is an
additional control for RST7.5.
D3=mask set enable; enables the functions of bits D2, D1 & D0 if
bit=1.
D2, D1, D0=interrupt mask for RST7.5, 6.5 & 5.5; masked (reset)
if bit=1.
Vector location
0024 H
Comments
Non-maskable, hardware interrupt. This
has the highest priority. In order for the

8085 P to service this interrupt, it must
be kept HIGH until the P responds to it.
Maskable, hardware interrupt. This has
2.
003C H
RST7.5
the priority next to TRAP.
3.
0034 H
RST6.5
the priority next to RST7.5.
4.
002C H
RST5.5
the priority next to RST6.5.
INTR: Maskable, hardware interrupt. This has the lowest priority. When INTR is high, the P
completes the execution of the current instruction and generates an INTA signal. Then the P
expects either a 1-byte CALL (RST0 through RST7) or a 3-byte CALL on the data bus. The
INTA signal can be used to enable an external hardware, which has been designed to provide
the opcode for the required CALL instruction on the data bus. If a 3-byte CALL instruction is
used, then the P generates two additional INTA cycles in order to fetch all the three bytes of
the CALL instruction.
Maskable, software interrupts. For these
5.
0000 H
RST0
interrupts to be serviced, the respective
6.
0008 H
RST1
opcodes must be placed on the data bus
7.
0010 H
RST2
through an external hardware, on
8.
0018 H
RST3
receiving the INTA signal. When two or
9.
0020 H
RST4
more of these interrupts are used, the
priorities among these interrupts must be
10.
0028 H
RST5
resolved by an external hardware. Such
11.
0030 H
RST6
hardware is often called the priority
12.
0038 H
RST7
resolver or controller.
6
6
6
6
6
The 8085-interrupt system has five interrupts, namely TRAP, RST7.5, RST6.5, RST5.5
and INTR. Among them the TRAP has the highest priority, the RST7.5 has the second
highest priority and so on. The INTR has the lowest priority.
All the interrupts except TRAP are maskable i.e., they can be enabled or disabled through
instructions.
For the P to recognize (service) any maskable interrupt, it must be first unmasked (set)
through the instruction SIM and then the 8085 maskable interrupt system must be enabled
through the instruction EI.
Recognition of any maskable interrupt (RST7.5, RST6.5, RST5.5 and INTR) disables all
maskable interrupts. For the P to recognize any maskable interrupt any further, the 8085
maskable interrupt system must be enabled through the instruction EI again.
On being interrupted, the P completes the execution of the current instruction, saves the
program counter in the stack and branches to the respective vector location.
8085 instructions that affect status flags:

S.No. Instructions
1.
ACI d8
2.
ADC r
3.
ADC mem
4.
ADD r
5.
ADD mem
6.
ADI d8
7.
ANA r
8.
ANA mem
9.
ANI d8
10.
CMC
11.
CMP r
12.
CMP mem
13.
CPI d8
14.
DAA
15.
DAD rp
16.
DCR r
17.
DCR mem
18.
INR r
19.
INR mem
20.
ORA r
21.
ORA mem
22.
ORI d8
23.
RAL
24.
RAR
25.
RLC
26.
RRC
27.
SBB r
28.
SBB mem
29.
SBI d8
30.
STC
31.
SUB r
32.
SUB mem
33.
SUI d8
34.
XRA r
35.
XRA mem
36.
XRI d8
d88-bit data; r8-bit register; mem8-bit
Cy
+
+
+
+
+
+
0
0
0
+
+
+
+
+
+
Ac
+
+
+
+
+
+
1
1
1
Z
+
+
+
+
+
+
+
+
+
S
+
+
+
+
+
+
+
+
+
P
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
0
0
0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
0
0
0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
0
0
+
+
+
0
0
+
+
+
0
0
+
+
+
memory; rpregister pair
+ indicates that the particular flag is affected;

0 or 1 indicates that these flags are always 0 or 1 after the execution of the corresponding
instruction
Instruction timings of 8085

T1
T2
T3
T4
CK
IO/M
A15 - A8
AD0 - AD7
undefined
PCH
PCL
OP
ALE
RD
S0
S1
PC out
PC+1-->PC
op-->IR
Decoding
IR=Instruction Register
Opcode fetch cycle timings of 8085
T1
T2
T3
CK
IO/M
addrH
A15 - A8
AD0 - AD7
addrL
d8 from mem
ALE
RD
S0
S1
RP or WZ out
(or)
PC out
d8-------------------------------->reg
PC+1-->PC
d8----->reg
Memory read cycle timings of 8085

RP=BC, DE, HL or SP
T1
T2
T3
CK
IO/M
addrH
A15 - A8
AD0 - AD7
addrL
d8 from cpu
ALE
WR
S0
S1
RP or WZ out
d8-------------------------------->mem
Memory write cycle timings of 8085

RP=BC, DE, HL or SP
Instruction timing of 8085: The important terms that must be known prior to the study of the
instruction timings of 8085 are:
(1) the instruction cycle, which is referred to as the time required to complete the
execution of an instruction and
(2) the machine cycle, which is referred to as the time required to complete a memory
related operation or an IO related operation. Thus, there are five machine cycles possible: (i) the
Opcode fetch, (ii) the memory read, (iii) the memory write, (iv) the IO read and (v) the IO write.
The execution of an 8085 instruction requires one to five machine cycles. The first
machine cycle of any instruction is the Opcode fetch cycle.
The Opcode fetch cycle requires four to six clock cycles (T-states). A memory/IO read or
write cycle requires three clock cycles.
The things explained above have been shown schematically in the following figure:
M1
M2
M3
M4
M5
T1 T2 T3 T4 T5 T6 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
Opcode fetch cycle of 8085: The Opcode fetch cycle timings of 8085 can be explained as
follows:
(i) The microprocessor puts a LOW on the IO/M pin, indicating a memory related
operation.
(ii) The microprocessor puts a HIGH on the S0 and S1 pins, indicating an Opcode fetch.
(iii) The microprocessor places the high byte of the program counter on the address lines
and the low byte of the program counter on the data lines and puts a HIGH on the ALE pin.
All the above actions take place approximately at the beginning of T1.
The ALE remains HIGH approximately for the first half cycle of T1. The low-order
address byte will be available on the data lines only during T1 and then these lines will be used
to fetch the Opcode. Therefore, when the ALE goes LOW, the trailing edge of the ALE must be
used to latch the low-order address byte externally.
(iv) At the beginning of T2, the microprocessor puts a LOW on the RD pin, indicating a
read operation. The RD pin goes HIGH approximately at the beginning of the second half cycle
of T3. When this pin is LOW, the microprocessor reads the data lines, which are now carrying
the Opcode, into the instruction register.
(v) During T4, the microprocessor decodes the instruction.
Memory read cycle of 8085: The memory read cycle timings of 8085 can be explained
as follows:
operation.
(ii) The microprocessor puts a LOW on the S0 pin and a HIGH on the S1 pin, indicating
a read operation.
(iii) The microprocessor places the high-order address byte on the address lines and the
low-order address byte on the data lines and puts a HIGH on the ALE pin.
to fetch the data from the selected memory location. Therefore, when the ALE goes LOW, the
trailing edge of the ALE must be used to latch the low-order address byte externally.
(iv) At the beginning of T2, the microprocessor puts a LOW on the RD pin, indicating a
read operation. The RD pin goes HIGH approximately at the beginning of the second half cycle
of T3. When this pin is LOW, the microprocessor reads the data lines into a register such as the
accumulator.
Memory write cycle of 8085: The memory write cycle timings of 8085 can be explained
as follows:
operation.
(ii) The microprocessor puts a HIGH on the S0 pin and a LOW on the S1 pin, indicating
a write operation.
(iii) The microprocessor places the high-order address byte on the address lines and the
low-order address byte on the data lines and puts a HIGH on the ALE pin.
to carry the data to the selected memory location. Therefore, when the ALE goes LOW, the
trailing edge of the ALE must be used to latch the low-order address byte externally.
(iv) At the beginning of T2, the microprocessor puts a LOW on the WR pin, indicating a
write operation. The WR pin goes HIGH approximately at the beginning of the second half
cycle of T3. When this pin is LOW, the data lines are read into the selected memory location (by
an external logic).
Microoperations in each machine cycle:
Opcode fetch cycle:
(1) During T1, the content of PC is placed on the address bus.
(2) During T2, PC is incremented by one.
(3) During T3, the opcode is read in the instruction register.
(4) During T4, the opcode is decoded.
The execution of the instruction is often carried out in the opcode fetch cycle of the next
instruction.
Memory read cycle:
(1) During T1, the required memory address, which may be the content of either a RP or
WZ or PC, is placed on the address bus.
If PC is used in T1, then
(2) During T2, PC will be incremented by one and during T3, the 8-bit data from the
selected memory location will be read into a register or else
(3) the 8-bit data from the selected memory location will be read into a register during
T2 and T3.
Memory write cycle:
(1) During T1, the required memory address, which may be the content of either a RP or
WZ, is placed on the address bus.
(2) During T2 and T3, the 8-bit data is written into the selected memory location.
Hinds to determine the number of clock cycles (T-states) required by an instruction:

(1) Determine the number of machine cycles required to complete the instruction fetch,
remembering that (i) a 1-byte instruction requires one machine cycle (i.e., the Opcode
fetch cycle to fetch the Opcode) to complete the instruction fetch, (ii) a 2-byte
instruction requires two machine cycles (i.e., the Opcode fetch cycle to fetch the
Opcode, followed by one memory read cycle to read the next instruction byte) to
complete the instruction fetch and (iii) a 3-byte instruction requires three machine
cycles (i.e., the Opcode fetch cycle to fetch the Opcode, followed by two memory read
cycles to read the next two instruction bytes) to complete the instruction fetch. Simply
speaking, the number of machine cycles required to complete the instruction fetch is
equal to the number of bytes required by the instruction.
(2) Determine the other machine cycles required to complete the execution of the
instruction.
(3) Determine the number of clock cycles required by each machine cycle, remembering
that (i) the Opcode fetch cycle requires four to six clock cycles: it normally requires
four clock cycles for most instructions except for those that involve 16-bit operations
or those that involve extra operations other than those suggested by themselves or an
interrupt and (ii) any machine (MR or MW) cycle that follows the Opcode fetch cycle
requires three clock cycles.
Total Machine
cycles for
Instruction
completion of
instruction fetch
MOV r1, r2 OPF
MOV r,
OPF
mem
MOV mem,
OPF
r
MVI r, d8
OPF/MR
MVI mem,
OPF/MR
d8
LXI rp, d16 OPF/MR/MR
LDA a16
OPF/MR/MR
STA a16
OPF/MR/MR
LHLD a16 OPF/MR/MR
SHLD a16
OPF/MR/MR
LDAX rp
OPF
STAX rp
OPF
XCHG
OPF
ADD r
OPF
ADD mem OPF
ADI d8
OPF/MR
ADC r
OPF
ADC mem OPF
ACI d8
OPF/MR
SUB r
OPF
Additional Machine
cycles for completion of
instruction execution
Total
Machine
cycles
Clock cycles
Or
T-states
MR
4+3=7
MW
4+3=7
4+3=7
MW
4+3+3=10
MR
MW
MR/MR
MW/MW
MR
MW
MR
MR
-
3
4
4
5
5
2
2
1
1
2
2
1
2
2
1
4+3+3=10
4+3+3+3=13
4+3+3+3=13
4+3+3+3+3=16
4+3+3+3+3=16
4+3=7
4+3=7
4
4
4+3=7
4+3=7
4
4+3=7
4+3=7
4
SUB mem
SUI d8
SBB r
SBB mem
SBI d8
INR r
INR mem
DCR r
DCR mem
INX rp
DCX rp
DAD rp
DAA
ANA r
ANA mem
ANI d8
XRA r
XRA mem
XRI d8
ORA r
ORA mem
ORI d8
CMP r
CMP mem
CPI d8
RLC
RRC
RAL
RAR
CMA
CMC
STC
JMP a16
RET
OPF
OPF/MR
OPF
OPF
OPF/MR
OPF
OPF
OPF
OPF
OPF
OPF
OPF
OPF
OPF
OPF
OPF/MR
OPF
OPF
OPF/MR
OPF
OPF
OPF/MR
OPF
OPF
OPF/MR
OPF
OPF
OPF
OPF
OPF
OPF
OPF
OPF/MR/MR
OPF/MR/MR
or
OPF/MR
OPF/MR/MR
OPF/MR/MR
or
OPF/MR
OPF
Rcond
OPF
RSTn
PCHL
PUSH rp
OPF
OPF
OPF
Jcond a16
CALL a16
Ccond a16
MR
MR
MR/MW
MR/MW
BI/BI
MR
MR
MR
MR
MW/MW
MW/MW
MR/MR
MR/MR
or
MW/MW
MW/MW
2
2
1
2
2
1
3
1
3
1
1
3
1
1
2
2
1
2
2
1
2
2
1
2
2
1
1
1
1
1
1
1
3
3
or
2
5
5
or
2
3
3
or
1
3
1
3
4+3=7
4+3=7
4
4+3=7
4+3=7
4
4+3+3=10
4
4+3+3=10
6
6
4+3+3=10
4
4
4+3=7
4+3=7
4
4+3=7
4+3=7
4
4+3=7
4+3=7
4
4+3=7
4+3=7
4
4
4
4
4
4
4
4+3+3=10
4+3+3=10
or
4+3=7
6+3+3+3+3=18
6+3+3+3+3=18
or
6+3=9
4+3+3=10
6+3+3=12
or
6
6+3+3=12
6
6+3+3=12
PUSH psw
POP rp
POP psw
XTHL
SPHL
IN a8
OUT a8
EI
DI
OPF
OPF
OPF
OPF
OPF
OPF/MR
OPF/MR
OPF
OPF
MW/MW
MR/MR
MR/MR
MR/MR/MW/MW
IOR
IOW
-
HLT
OPF
NOP
RIM
SIM
OPF
OPF
OPF
3
3
3
5
1
3
3
1
1
1
or
MORE
1
1
1
6+3+3=12
4+3+3=10
4+3+3=10
4+3+3+3+3=16
6
4+3+3=10
4+3+3=10
4
4
5
or
MORE
4
4
4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
MNE
ACI d8
ADC B
ADC C
ADC D
ADC E
ADC H
ADC L
ADC mem
ADC A
ADD B
ADD C
ADD D
ADD E
ADD H
ADD L
ADD mem
ADD A
ADI d8
ANA B
ANA C
ANA D
ANA E
ANA H
ANA L
ANA mem
ANA A
ANI d8
CALL a16
CC a16
CNC a16
CP a16
CM a16
CPE a16
CPO a16
CZ a16
CNZ a16
CMA
CMC
CMP B
CMP C
CMP D
CMP E
CMP H
CMP L
CMP mem
CMP A
CPI d8
DAA
DAD B
OP
CE
88
89
8A
8B
8C
8D
8E
8F
80
81
82
83
84
85
86
87
C6
A0
A1
A2
A3
A4
A5
A6
A7
E6
CD
DC
D4
F4
FC
EC
E4
CC
C4
2F
3F
B8
B9
BA
BB
BC
BD
BE
BF
FE
27
09
Opcodes for 8085 Instruction Set

MNE
OP
MNE
OP
MNE
DAD D
DAD H
DAD SP
DCR B
DCR C
DCR D
DCR E
DCR H
DCR L
DCR mem
DCR A
DCX B
DCX D
DCX H
DCX SP
DI
EI
HLT
IN a8
INR B
INR C
INR D
INR E
INR H
INR L
INR mem
INR A
INX B
INX D
INX H
INX SP
JMP a16
JC a16
JNC a16
JP a16
JM a16
JPE a16
JPO a16
JZ a16
JNZ a16
LDA a16
LDAX B
LDAX D
LHLD a16
LXI B, d16
LXI D, d16
LXI H, d16
LXI SP, d16
MOV B, B
19
29
39
05
0D
15
1D
25
2D
35
3D
0B
1B
2B
3B
F3
FB
76
DB
04
0C
14
1C
24
2C
34
3C
03
13
23
33
C3
DA
D2
F2
FA
EA
E2
CA
C2
3A
OA
1A
2A
01
11
21
31
40
MOV B, C
MOV B, D
MOV B, E
MOV B, H
MOV B, L
MOV B, mem
MOV B, A
MOV C, B
MOV C, C
MOV C, D
MOV C, E
MOV C, H
MOV C, L
MOV C, mem
MOV C, A
MOV D, B
MOV D, C
MOV D, D
MOV D, E
MOV D, H
MOV D, L
MOV D, mem
MOV D, A
MOV E, B
MOV E, C
MOV E, D
MOV E, E
MOV E, H
MOV E, L
MOV E, mem
MOV E, A
MOV H, B
MOV H, C
MOV H, D
MOV H, E
MOV H, H
MOV H, L
MOV H, mem
MOV H, A
MOV L, B
MOV L, C
MOV L, D
MOV L, E
MOV L, H
MOV L, L
MOV L, mem
MOV L, A
MOV mem, B
MOV mem, C
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
MOV mem, D
MOV mem, E
MOV mem, H
MOV mem, L
MOV mem, A
MOV A, B
MOV A, C
MOV A, D
MOV A, E
MOV A, H
MOV A, L
MOV A, mem
MOV A, A
MVI B, d8
MVI C, d8
MVI D, d8
MVI E, d8
MVI H, d8
MVI L, d8
MVI mem, d8
MVI A, d8
NOP
ORA B
ORA C
ORA D
ORA E
ORA H
ORA L
ORA mem
ORA A
ORI d8
OUT a8
PCHL
POP B
POP D
POP H
POP psw
PUSH B
PUSH D
PUSH H
PUSH psw
RAL
RAR
RLC
RRC
RET
RC
RNC
RP
OP
MNE
OP
72
73
74
75
77
78
79
7A
7B
7C
7D
7E
7F
06
0E
16
1E
26
2E
36
3E
00
B0
B1
B2
B3
B4
B5
B6
B7
F6
D3
E9
C1
D1
E1
F1
C5
D5
E5
F5
17
1F
07
0F
C9
D8
D0
F0
RM
RPE
RPO
RZ
RNZ
RIM
RST0
RST1
RST2
RST3
RST4
RST5
RST6
RST7
SBB B
SBB C
SBB D
SBB E
SBB H
SBB L
SBB mem
SBB A
SBI d8
SHLD a16
SIM
SPHL
STA a16
STAX B
STAX D
STC
SUB B
SUB C
SUB D
SUB E
SUB H
SUB L
SUB mem
SUB A
SUI d8
XCHG
XRA B
XRA C
XRA D
XRA E
XRA H
XRA L
XRA mem
XRA A
XRI d8
F8
E8
E0
C8
C0
20
C7
CF
D7
DF
E7
EF
F7
FF
98
99
9A
9B
9C
9D
9E
9F
DE
22
30
F9
32
02
12
37
90
91
92
93
94
95
96
97
D6
EB
A8
A9
AA
AB
AC
AD
AE
AF
EE
XTHL
E3
Procedure to write a program in the PROGRAM SHEET:

Writing instructions:
1. Write each instruction of your program in the order in which the
program should be executed.
2. (i) If an instruction requires one byte alone, write the next
instruction in the next line. (ii) If an instruction requires two bytes,
leave an extra line for that two-byte instruction and write the next
instruction. (iii) If an instruction requires three bytes, leave two extra
lines for that three-byte instruction and write the next instruction.
Writing MACHINE CODE s:
1. While writing the MACHINE CODE, write the Hex code for the
MNEMONIC as the first byte of the MACHINE CODE for any
instruction referring to the OP-CODE SHEET.
2. For the two-byte instruction, write the 8-bit data or the 8-bit
address (which must be in the Hex representation) specified (by you)
in the instruction as the second byte of the MACHINE CODE.
3. For the three-byte instruction, write the low-order byte of the 16bit data or address (which must be in the Hex representation)
specified (by you) in the instruction as the second byte of the
MACHINE CODE, and the high-order byte of the same 16-bit data
or address as third byte of the MACHINE CODE.
Specifying memory locations:
1. While writing the addresses, calculate the number of memory
locations required for your program. This is equal to the number of
bytes in the MACHINE CODE column.
2. Choose the starting address for your program. The starting address
can be any one of the addresses of the user memory locations
available on the P trainer board you have.
Specify, in the ADDRESS column, the starting address you have
chosen as the storage location for the first byte in the MACHINE
CODE column, the next address as that for the second byte in the
MACHINE CODE column and so on. You should specify consecutive
memory locations as the storage locations for consecutive bytes in the
MACHINE CODE column.
PROGRAM:
ADDRESS
OP-CODE
INSTRUCTION
COMMENTS
Procedure to write a program in the PROGRAM SHEET:

Writing instructions:
1. Write each instruction of your program in the order in which the program
should be executed.
2. (i) If an instruction requires one byte alone, write the next instruction in
the next line. (ii) If an instruction requires two bytes, leave an extra line for
that two-byte instruction and write the next instruction. (iii) If an instruction
requires three bytes, leave two extra lines for that three-byte instruction and
write the next instruction.
Writing MACHINE CODE s:
1. While writing the MACHINE CODE, write the Hex code for the
MNEMONIC as the first byte of the MACHINE CODE for any instruction
referring to the OP-CODE SHEET.
2. For the two-byte instruction, write the 8-bit data or the 8-bit address
(which must be in the Hex representation) specified (by you) in the
instruction as the second byte of the MACHINE CODE.
3. For the three-byte instruction, write the low-order byte of the 16-bit data or
address (which must be in the Hex representation) specified (by you) in the
instruction as the second byte of the MACHINE CODE, and the high-order
byte of the same 16-bit data or address as third byte of the MACHINE
CODE.
Specifying memory locations:
1. While writing the addresses, calculate the number of memory locations
required for your program. This is equal to the number of bytes in the
MACHINE CODE column.
2. Choose the starting address for your program. The starting address can be
any one of the addresses of the user memory locations available on the P
trainer board you have.
3. Specify, in the ADDRESS column, the starting address you have chosen as
the storage location for the first byte in the MACHINE CODE column, the
next address as that for the second byte in the MACHINE CODE column and
so on. You should specify consecutive memory locations as the storage
locations for consecutive bytes in the MACHINE CODE column.
PROGRAM SHEET
PROGRAM:
ADDRESS
OP-CODE
INSTRUCTION
COMMENTS
Opcodes for 8085 Instruction Set

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
MNE
ACI d8
ADC B
ADC C
ADC D
ADC E
ADC H
ADC L
ADC mem
ADC A
ADD B
ADD C
ADD D
ADD E
ADD H
ADD L
ADD mem
ADD A
ADI d8
ANA B
ANA C
ANA D
ANA E
ANA H
ANA L
ANA mem
ANA A
ANI d8
CALL a16
CC a16
CNC a16
CP a16
CM a16
CPE a16
CPO a16
CZ a16
CNZ a16
CMA
CMC
CMP B
CMP C
CMP D
CMP E
CMP H
CMP L
CMP mem
CMP A
CPI d8
DAA
DAD B
OP
CE
88
89
8A
8B
8C
8D
8E
8F
80
81
82
83
84
85
86
87
C6
A0
A1
A2
A3
A4
A5
A6
A7
E6
CD
DC
D4
F4
FC
EC
E4
CC
C4
2F
3F
B8
B9
BA
BB
BC
BD
BE
BF
FE
27
09
MNE
DAD D
DAD H
DAD SP
DCR B
DCR C
DCR D
DCR E
DCR H
DCR L
DCR mem
DCR A
DCX B
DCX D
DCX H
DCX SP
DI
EI
HLT
IN a8
INR B
INR C
INR D
INR E
INR H
INR L
INR mem
INR A
INX B
INX D
INX H
INX SP
JMP a16
JC a16
JNC a16
JP a16
JM a16
JPE a16
JPO a16
JZ a16
JNZ a16
LDA a16
LDAX B
LDAX D
LHLD a16
LXI B, d16
LXI D, d16
LXI H, d16
LXI SP, d16
MOV B, B
OP
19
29
39
05
0D
15
1D
25
2D
35
3D
0B
1B
2B
3B
F3
FB
76
DB
04
0C
14
1C
24
2C
34
3C
03
13
23
33
C3
DA
D2
F2
FA
EA
E2
CA
C2
3A
OA
1A
2A
01
11
21
31
40
MNE
MOV B, C
MOV B, D
MOV B, E
MOV B, H
MOV B, L
MOV B, mem
MOV B, A
MOV C, B
MOV C, C
MOV C, D
MOV C, E
MOV C, H
MOV C, L
MOV C, mem
MOV C, A
MOV D, B
MOV D, C
MOV D, D
MOV D, E
MOV D, H
MOV D, L
MOV D, mem
MOV D, A
MOV E, B
MOV E, C
MOV E, D
MOV E, E
MOV E, H
MOV E, L
MOV E, mem
MOV E, A
MOV H, B
MOV H, C
MOV H, D
MOV H, E
MOV H, H
MOV H, L
MOV H, mem
MOV H, A
MOV L, B
MOV L, C
MOV L, D
MOV L, E
MOV L, H
MOV L, L
MOV L, mem
MOV L, A
MOV mem, B
MOV mem, C
OP
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
MNE
MOV mem, D
MOV mem, E
MOV mem, H
MOV mem, L
MOV mem, A
MOV A, B
MOV A, C
MOV A, D
MOV A, E
MOV A, H
MOV A, L
MOV A, mem
MOV A, A
MVI B, d8
MVI C, d8
MVI D, d8
MVI E, d8
MVI H, d8
MVI L, d8
MVI mem, d8
MVI A, d8
NOP
ORA B
ORA C
ORA D
ORA E
ORA H
ORA L
ORA mem
ORA A
ORI d8
OUT a8
PCHL
POP B
POP D
POP H
POP psw
PUSH B
PUSH D
PUSH H
PUSH psw
RAL
RAR
RLC
RRC
RET
RC
RNC
RP
OP
72
73
74
75
77
78
79
7A
7B
7C
7D
7E
7F
06
0E
16
1E
26
2E
36
3E
00
B0
B1
B2
B3
B4
B5
B6
B7
F6
D3
E9
C1
D1
E1
F1
C5
D5
E5
F5
17
1F
07
0F
C9
D8
D0
F0
MNE
RM
RPE
RPO
RZ
RNZ
RIM
RST0
RST1
RST2
RST3
RST4
RST5
RST6
RST7
SBB B
SBB C
SBB D
SBB E
SBB H
SBB L
SBB mem
SBB A
SBI d8
SHLD a16
SIM
SPHL
STA a16
STAX B
STAX D
STC
SUB B
SUB C
SUB D
SUB E
SUB H
SUB L
SUB mem
SUB A
SUI d8
XCHG
XRA B
XRA C
XRA D
XRA E
XRA H
XRA L
XRA mem
XRA A
XRI d8
XTHL
OP
F8
E8
E0
C8
C0
20
C7
CF
D7
DF
E7
EF
F7
FF
98
99
9A
9B
9C
9D
9E
9F
DE
22
30
F9
32
02
12
37
90
91
92
93
94
95
96
97
D6
EB
A8
A9
AA
AB
AC
AD
AE
AF
EE
E3
Programmable Peripheral Interface-8255:
GROUP
A
CONTROL
DATA
BUS
BUFFER
D7-D0
GROUP
A
PORT A
(8)
PA7-PA0
GROUP
A
PORT CU
(4)
PC7-PC4
GROUP
B
PORT CL
(4)
PC3-PC0
GROUP
B
PORT B
(8)
PB7-PB0
RD
WR
A0
READ
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
A1
RESET
CS
8255-Programmable Peripheral Interface
Addresses of ports:
A1
0
0
1
1
A0
0
1
0
1
CS
0
0
0
0
Port selected
Port A
Port B
Port C
Control Register
The 8255 is a general-purpose programmable I/O interfacing device. It provides 24

I/O lines organized as three 8-bit I/O ports labeled A, B and C. All 8 bits of Port A and Port B
are programmed as one byte but Port C is programmed as two separate 4-bit ports as Port CU
and Port CL. These three ports are organized into two groups, Group A and Group B. Group
A consists Port A and Port CU and Group B consists of Port B and Port CL.
The ports can be programmed either in Bit Set/Reset (BSR) mode or in I/O mode,
Mode 0, Mode 1 and Mode 2. In I/O mode, Group A can be programmed in either of three
I/O modes, Mode 0, Mode 1 or Mode 2 and independently Group B can be programmed in
either of two I/O modes, Mode 0 or Mode 1.
Control word format: The following figure shows the control word format for various
modes of operation of 8255.
Control word for Bit Set/Reset (BSR) Mode

D7 D6 D5 D4 D3 D2 D1 D0
0
1 Bit set
0 Bit reset
Bit Select
D3 D2 D1
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7
Control word for I/O Mode

D7
D6
D5
D4
D3
D2
D1
D0
1
Group B
Port CL
1 input
0 output
Port B
1 input
0 output
Mode Selection
0 Mode 0
1 Mode 1
Group A
Port CU
1 input
0 output
Port A
1 input
0 output
Mode Selection
D6 D5
0 0 Mode 0
0 1 Mode 1
0 x Mode 2
Bit Set/Reset (BSR) mode: Each bit of Port C can be independently set (1) or reset (0) but
only one bit can be set or reset at a time.
I/O Modes:
Mode 0: Basic I/O mode: Any port (Port A, Port B, Port CU or Port CL) can be
independently configured as simple input port or simple output port.
Mode 1: Strobed I/O mode: Port A and Port B can be independently configured either as
strobed input port or as output port. Port C is used for handshaking.
Port A & Port B as input port: The following figure shows the two of four Mode 1
possible configurations of Port A and Port B. Here Port A and Port B are configured as input
ports with three handshaking signals namely STB, IBF and INTR.
PB7-PB0
PA7-PA0
INTE B
INTE A
PC4
STBA
PC2
STBB
PC5
IBFA
PC1
IBFB
PC3
INTRA
PC0
INTRB
RD
RD
2
PC6/PC7
I/O
Input port timing for Port A:

PC3, PC4 & PC5 are used for handshaking.
PC4 STBA: STroBe (active low input)
PC5 IBFA: Input Buffer Full (active high output)
PC3 INTRA: INTeRrupt (active high output)
INTE A is controlled by bit set/reset of PC4. IBFA is set by the falling edge of STBA
and is reset by the rising edge of RD. INTRA is set by the rising edge of STBA if IBFA is a 1
and INTE A is a 1, and is reset by the falling edge of RD.
Input port timing for Port B:
PC2 STBB: STroBe (active low input)
PC1 IBFB: Input Buffer Full (active high output)
PC0 INTRB: INTeRrupt (active high output)
INTE B is controlled by bit set/reset of PC2. IBFB is set by the falling edge of STBB
and is reset by the rising edge of RD. INTRB is set by the rising edge of STBB if IBFB is a 1
and INTE B is a 1, and is reset by the falling edge of RD.
Port A & Port B as output port: The following figure shows the two of four Mode 1
possible configurations of Port A and Port B. Here Port A and Port B are configured as output
ports with three handshaking signals namely ACK, OBF and INTR.
PB7-PB0
PA7-PA0
INTE B
INTE A
PC6
ACKA
PC2
ACKB
PC7
OBFA
PC1
OBFB
PC3
INTRA
PC0
INTRB
WR
WR
2
PC4/PC5
I/O
Output port timing for Port A:

PC6 ACKA: ACKnowledge (active low input)
PC7 OBFA: Output Buffer Full (active low output)
PC3 INTRA: INTeRrupt (active high output)
INTE A is controlled by bit set/reset of PC6. OBFA is set by the rising edge of ACKA
and is reset by the rising edge of WR. INTRA is set by the falling edge of ACKA if OBFA is a
0 and INTE A is a 1 and is reset by the falling edge of WR.
Output port timing for Port B:
PC2 ACKB: ACKnowledge (active low input)
PC1 OBFB: Output Buffer Full (active low output)
PC0 INTRB: INTeRrupt (active high output)
INTE B is controlled by bit set/reset of PC2. OBFB is set by the rising edge of ACKB
and is reset by the rising edge of WR. INTRB is set by the falling edge of ACKB if OBFB is a
0 and INTE B is a 1 and is reset by the falling edge of WR.
Polling & Interrupt: If Port A or Port B is programmed as input port (output) in Mode 1, the
processor becomes alert either by polling IBF (OBF) for a 1 (0) or by letting INTR to
interrupt that the input (output) buffer is full (empty). In the former case, the processor has to
read Port C for a Mode 1 Status Word and perform standard bit-testing techniques. The
format for Mode 1 Status Word has been shown below. If Port A is programmed as input port
and Port B as output port, then Group A bits will be set for input configuration and Group B,
bits for output configuration.
Mode 1 Status Word for Input Configuration

D7
D6
D5
D4
D3
D2
D1
D0
I/O
I/O
IBFA
INTEA
INTRA
INTEB
IBFB
INTRB
Group A bits
Group B bits
Mode 1 Status Word for Output Configuration

D7
D6
D5
D4
D3
D2
D1
D0
OBFA
INTEA
I/O
I/O
INTRA
INTEB
OBFB
INTRB
Group B bits
Group A bits
Mode 2: Bidirectional handshake mode: Port A is programmed as a bidirectional I/O port

and Port C is used for handshaking.
PC3
INTRA
PA7-PA0
INTE
1
PC7
OBFA
PC6
ACKA
PC4
STBA
PC5
IBFA
INTE
2
WR
PC2 PC0
RD
3
I/O
INTE 1 is controlled by bit set/reset of PC6 and INTE 2 is controlled by bit set/reset of
PC4.
Polling & Interrupt: For polling the processor has to read Port C for a Mode 2 Status Word
and perform standard bit-testing techniques. The format for Mode 2 Status Word has been
shown below.
Mode 2 Status Word for Output Configuration
D7
D6
D5
D4
D3
D2
D1
D0
OBFA
INTE 1
IBFA
INTE 2
INTRA
Group A bits
Group B bits
Programmable Keyboard/Display Interface-8279:

(I) To display a character:
Step 1: Select the desired (keyboard and) display mode using the following control word.
0
Display/Keyboard mode set control word

D D
Comments
0 0 8-digit, 8-bit character display---left entry
0 1 8-digit, 8-bit character display---right entry
K K K
Comments
0 0 0 encoded scan keyboard---two-key lockout
0 0 1 decoded scan keyboard---two-key lockout
0 1 0 encoded scan keyboard---N-key rollover
0 1 1 decoded scan keyboard---N-key rollover
The DD field selects the display length and the entry mode.
The 8279 has a 16-byte long display RAM. In the left entry mode, the characters in the
display RAM are displayed as shown below.
0000
(A)
0001
(b)
0010
(C)
0011
(d)
Display RAM
Display
In the right entry mode, the characters in the display RAM are displayed as shown below.
0000
(A)
0001
(b)
0010
(C)
0011
(d)
Display RAM
Display
Any new entry to the display RAM will shift the display to the left by one digit, displaying
the newly entered character on the rightmost digit.
Step 2: Select the blanking code using the following control word.
1
EN CD CD
CF
CA
Clear control word

ENwhen 1, clears the display RAM. During the time the display RAM is being cleared, it
may not be written. To know the end of this process, follow Step 3.
CDCDdetermines the blanking code as follows: This is dependent on the hardware.
CD CD
Comments
0 X All zeros; sends logic 0 to the deselected segments in the display
1
1 All ones; sends logic 1 to the deselected segments in the display
CFwhen 1, clears the FIFO status word and resets the interrupt line.
CAwhen 1, clears both the display RAM and the FIFO status word.
Step 3: Read and check the MSB of the FIFO status word, which is described below to
identify the end of the clear display RAM process.
DU
FIFO status word

DUwhen 1, the display RAM is being cleared and is not available.
when 0, the display RAM is available for writing.
Fwhen 1, the FIFO/sensor RAM is full. The FIFO/sensor RAM stores the code for the key
pressed.
N N Nnumber of characters (read from the keyboard) stored in the FIFO/sensor RAM.
Step 4: Select the write display RAM mode to write the code for the character to be
displayed into the display RAM using following control word.
1
AI
Write display RAM control word

AI (AutoIncrement)when 1, the row address is automatically incremented by one after
every write into the display RAM.
A A A Arow address field.
Step 5: Write the proper code for the character to be displayed into the display RAM using
the following format
a
f
b
g
dp
Character code format

for display
dp
Seven-segment display
Assign logic 1s to the selected segments and logic 0s to the other segments. The deselected
segments (those with logic 0s) will be blanked with the proper blanking code determined in
Step 2.
Final note:
Write the proper control words and send them to the control register.
Read the FIFO status word from the control register.
Write the proper character codes and send them to the display RAM.
(II) To read a character from keyboard:
Step 1: Select the desired keyboard (and display) mode using the following control word.
0
Display/Keyboard mode set control word

D D
Comments
0 0 8-digit, 8-bit character display---left entry
0 1 8-digit, 8-bit character display---right entry
K K K
Comments
0 0 0 encoded scan keyboard---two-key lockout
0 0 1 decoded scan keyboard---two-key lockout
0 1 0 encoded scan keyboard---N-key rollover
0 1 1 decoded scan keyboard---N-key rollover
Step 2: Read the FIFO status word and check the three LSBs for the new occurrence of
character or characters in the FIFO/sensor RAM. If yes, proceed to Step 3.
Step 3: Select the read FIFO/sensor RAM mode using the following control word.
0
AI
Read FIFO/sensor RAM control word
AI (AutoIncrement)when 1, the row address is automatically incremented by one after

every write into the display RAM.
A A A Arow address field.
Step 4: Read the codes for the characters depressed from the FIFO/sensor RAM and decode
them (i.e., find the corresponding display codes for the key codes from the FIFO/sensor
RAM) as shown below.
CNTR SHFT
SC
SC
SC
RL
RL
RL
Character code format for depressed key

CNTR, SHFTstatus of the control and shift lines.
SC, RCSC & RC fields indicate the position of the depressed switch i.e., the SC field is the
binary equivalent of the scan line, which is active during the keypress and the RC
field is the binary equivalent of the return line, which is sampled during the
keypress. This is dependent on the hardware.
Field
SC0
SC1
RL0
0
8
RL1
1
9
RL2
2
A
RL3
3
B
RL4
4
C
RL5
5
D
RL6
6
E
RL7
7
F
For decoding in case of kit, create a lookup table that contains the display code for each key
code using the above table.
Step 5: Store the display codes and send them to the display RAM through the steps 2 to 4 in
(I).
PROGRAM SHEET
PROGRAM 1: 8-BIT ADDITION
ADDRESS
OP-CODE
INSTRUCTION
4100
3A
LDA 4201h
4101
01
4102
42
4103
47
MOV B, A
4104
3A
LDA 4200h
4105
00
4106
42
4107
0E
4108
00
4109
80
ADD B
410A
D2
JNC END (410Eh)
410B
0E
410C
41
410D
0C
INR C
410E
32
END: STA 4202h
410F
02
4110
42
4111
79
MOV A, C
4112
32
STA 4203h
4113
03
4114
42
4115
76
MVI C, 00h
HLT
RESULT:
WITHOUT CARRY:
4200: AUGEND
4202: LB OF SUM
4201: ADDEND
WITH CARRY:
4200: AUGEND
4203: HB OF SUM
4201: ADDEND
4203: HB OF SUM
4202: LB OF SUM
COMMENTS
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
4100
3A
LDA 4200h
4101
00
4102
42
4103
FE
4104
01
4105
42
4106
86
ADD mem
4107
0E
MVI C, 00h
4108
00
4109
D2
410A
0D
410B
41
410C
0C
INR C
410D
32
END: STA 4202h
410E
02
410F
42
4110
79
MOV A, C
4111
32
STA 4203h
4112
03
4113
42
4114
76
RESULT: (SAME AS BEFORE)
LXI H, 4201h
JNC END (410Dh)
HLT
COMMENTS
PROGRAM SHEET
PROGRAM 2: 8-BIT SUBTRACTION
ADDRESS
OP-CODE
INSTRUCTION
4100
3A
LDA 4201h
4101
01
4102
42
4103
47
MOV B, A
4104
3A
LDA 4200h
4105
00
4106
42
4107
0E
4108
00
4109
90
SUB B
410A
D2
JNC END (4111h)
410B
11
410C
41
410D
2F
CMA
410E
C6
ADI 01h
410F
01
4110
0C
INR C
4111
32
END: STA 4202h
4112
02
4113
42
4114
79
MOV A, C
4115
32
STA 4203h
4116
03
4117
42
4118
76
RESULT:
WITHOUT CARRY:
4200: MINUEND
MVI C, 00h
HLT
4202: DIFFERENCE
4201: SUBTRAHEND
WITH CARRY:
4200: MINUEND
4203: CARRY
4201: SUBTRAHEND
4203: CARRY
4202: DIFFERENCE
COMMENTS
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
4100
3A
LDA 4200h
4101
00
4102
42
4103
21
4104
01
4105
42
4106
0E
4107
00
4108
96
SUB mem
4109
D2
JNC END (4110h)
410A
10
410B
41
410C
0C
INR C
410D
2F
CMA
410E
C6
ADI 01h
410F
01
4110
32
4111
02
4112
42
4113
79
MOV A, C
4114
32
STA 4203h
4115
03
4116
42
4117
76
LXI H, 4201h
MVI C, 00h
END: STA 4202h
HLT
COMMENTS
PROGRAM SHEET
PROGRAM 3: 8-BIT MULTIPLICATION
ADDRESS
OP-CODE
INSTRUCTION
4100
3A
LDA 4200h
4101
00
4102
42
4103
5F
MOV E, A
4104
16
MVI D, 00h
4105
00
4106
3A
4107
01
4108
42
4109
21
410A
00
410B
00
410C
19
LOOP: DAD D
410D
3D
DCR A
410E
C2
JNZ LOOP (410Ch)
410F
0C
4110
41
4111
22
4112
02
4113
42
4114
76
RESULT:
WITHOUT CARRY:
4200: MULTIPLICANT
LDA 4201h
LXI H, 0000h
SHLD 4202
HLT
4202: LB OF PRODUCT
4201: MULTIPLIER
WITH CARRY:
4200: MULTIPLICANT
4203: HB OF PRODUCT
4202: LB OF PRODUCT
4201: MULTIPLIER
4203: HB OF PRODUCT
COMMENTS
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
4100
3A
LDA 4200h
4101
00
4102
42
4103
5F
MOV E, A
4104
3A
LDA 4201h
4105
01
4106
42
4107
16
4108
00
4109
21
410A
00
410B
00
410C
0E
410D
08
410E
1F
LOOP: RAR
410F
D2
JNC SKP (4113)
4110
13
4111
41
4112
19
DAD D
4113
EB
SKP: XCHG
4114
29
DAD H
4115
EB
XCHG
4116
0D
DCR C
4117
C2
JNZ LOOP (410E)
4118
0E
4119
41
411A
22
411B
02
411C
42
411D
76
MVI D, 00h
LXI H, 0000h
MVI C, 08h
SHLD 4202h
HLT
COMMENTS
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
4100
3A
LDA 4200h
4101
00
4102
42
4103
4F
MOV C, A
4104
3A
LDA 4201h
4105
01
4106
42
4107
47
MOV B, A
4108
AF
XRA A
4109
16
MVI D, 00h
410A
00
410B
80
LOOP: ADD B
410C
D2
JNC CKCT (4110h)
410D
10
410E
41
410F
14
INR D
4110
0D
CKCT: DCR C
4111
C2
JNZ LOOP (410B)
4112
0B
4113
41
4114
32
4115
02
4116
42
4117
7A
MOV A, D
4118
32
STA 4203h
4119
03
411A
42
411B
76
STA 4202h
HLT
COMMENTS
PROGRAM SHEET
PROGRAM 4: 8-BIT DIVISION
ADDRESS
OP-CODE
INSTRUCTION
4100
3A
LDA 4201h
4101
01
4102
42
4103
47
MOV B, A
4104
3A
LDA 4200h
4105
00
4106
42
4107
0E
4108
00
4109
B8
LOOP: CMP B
410A
DA
JC END (4112h)
410B
12
410C
41
410D
90
SUB B
410E
0C
INR C
410F
C3
JMP LOOP (4109h)
4110
09
4111
41
4112
32
4113
02
4114
42
4115
79
MOV A, C
4116
32
STA 4203h
4117
03
4118
42
4119
76
MVI C, 00h
END: STA 4202h
HLT
RESULT:
4200: DIVIDEND
4202: QUOTIENT
4201: DIVISOR
4203: REMINDER
COMMENTS
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
4100
0E
MVI C, 00h
4101
00
4102
2A
4103
02
4104
42
4105
EB
XCHG
4106
2A
LHLD 4200h
4107
00
4108
42
4109
19
DAD D
410A
D2
JNC END (410Eh)
410B
0E
410C
41
410D
0C
INR C
410E
22
END: SHLD 4204h
410F
04
4110
42
4111
79
MOV A, C
4112
32
STA 4206h
4113
06
4114
42
4115
76
RESULT:
WITHOUT CARRY:
4200: LB OF AUGEND
4201: HB OF AUGEND
4202: LB OF ADDEND
4203: HB OF ADDEND
WITH CARRY:
4200: LB OF AUGEND
4201: HB OF AUGEND
4202: LB OF ADDEND
4203: HB OF ADDEND
COMMENTS
LHLD 4202h
HLT
SUM:
4206
4205
4204
SUM:
4206
4205
4204
10
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
4100
0E
MVI C, 00h
4101
00
4102
2A
4103
00
4104
42
4105
EB
XCHG
4106
2A
LHLD 4202h
4107
02
4108
42
4109
7D
LBADD: MOV A, L
410A
83
ADD E
410B
6F
MOV L, A
410C
7C
HBADD: MOV A, H
410D
8A
ADC D
410E
67
MOV H, A
410F
D2
JNC END (4113h)
4110
13
4111
41
4112
0C
INR C
4113
22
END: SHLD 4204
4114
04
4115
42
4116
79
MOV A, C
4117
32
STA 4206
4118
06
4119
42
411A
76
LHLD 4200h
HLT
COMMENTS
11
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
4100
0E
MVI C, 00h
4101
00
4102
21
4103
00
4104
42
4105
3A
4106
02
4107
42
4108
86
ADD mem
4109
5F
MOV E, A
410A
23
HBADD: INX H
410B
3A
LDA 4203h
410C
03
410D
42
410E
8E
ADC mem
410F
57
MOV D, A
4110
D2
JNC END
4113
0C
INR C
4114
EB
END: XCHG
4115
22
SHLD 4204h
4116
04
4117
42
4118
79
MOV A, C
4119
32
STA 4206h
411A
06
411B
42
411C
76
LXI H, 4200h
LBADD: LDA 4202h
4111
4112
HLT
COMMENTS
12
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
4100
0E
MVI C, 00h
4101
00
4102
06
4103
00
4104
2A
4105
00
4106
42
4107
EB
XCHG
4108
2A
LHLD 4202h
4109
02
410A
42
410B
7B
SULB: MOV A, E
410C
95
SUB L
410D
5F
MOV E, A
410E
D2
JNC SUHB (4112h)
410F
12
4110
41
4111
0C
INR C
4112
7A
SUHB: MOV A, D
4113
94
SUB H
4114
57
MOV D, A
4115
D2
JNC CCHK (4122h)
4116
22
4117
41
4118
0C
INR C
4119
04
INR B
411A
7A
MOV A, D
411B
2F
CMA
411C
80
ADD B
411D
57
MOV D, A
MVI B, 00h
LHLD 4200h
COMMENTS
13
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
411E
7B
MOV A, E
411F
2F
CMA
4120
80
ADD B
4121
5F
MOV E, A
4122
0D
CCHK: DCR C
4123
D2
JNZ END (4127h)
4124
27
4125
41
4126
15
DCR D
4127
EB
END: XCHG
4128
22
SHLD 4204h
4129
04
412A
42
412B
78
MOV A, B
412C
32
STA 4206h
412D
06
412E
42
412F
76
RESULT:
WITHOUT CARRY:
4200: LB OF MINUEND
4201: HB OF MINUEND
4202: LB OF SUBTRAHEND
4203: HB OF SUBTRAHEND
WITH CARRY:
4200: LB OF MINUEND
4201: HB OF MINUEND
4202: LB OF SUBTRAHEND
4203: HB OF SUBTRAHEND
HLT
4204: LB OF DIFFERENCE
4205: HB OF DIFFERENCE
4206: CARRY
4204: LB OF DIFFERENCE
4205: HB OF DIFFERENCE
4206: CARRY
COMMENTS
14
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
4100
0E
MVI C, 00h
4101
00
4102
2A
4103
00
4104
42
4105
EB
XCHG
4106
2A
LHLD 4202h
4107
02
4108
42
4109
7D
MOV A, L
410A
2F
CMA
410B
6F
MOV L, A
410C
7C
MOV A, H
410D
2F
CMA
410E
67
MOV H, A
410F
23
INX H
4110
19
DAD D
4111
3F
CMC
4112
D2
JNC END (411Dh)
4113
1D
4114
41
4115
0C
INR C
4116
7D
MOV A, L
4117
2F
CMA
4118
6F
MOV L, A
4119
7C
MOV A, H
411A
2F
CMA
411B
67
MOV H, A
411C
23
INX H
411D
22
END: SHLD 4204h
411E
04
411F
42
LHLD 4200h
COMMENTS
15
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
4120
79
MOV A, C
4121
32
STA 4206h
4122
06
4123
42
4124
76
HLT
COMMENTS
16
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
LHLD 4200h
SPHL
LHLD 4202h
XCHG
LXI H, 0000h
LXI B, 0000h
RADD: DAD SP
JNC CNT
INX B
CNT: DCX D
MOV A, E
ORA D
JNZ RADD
SHLD 4204h
MOV L, C
MOV H, B
COMMENTS
17
PROGRAM SHEET
ADDRESS
OP-CODE
INSTRUCTION
SHLD 4206h
HLT
COMMENTS
Microprocessor and Applications

Q-Bank
UNIT I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
Name any four manufacturers of P.

Name any four 8-bit Ps.
Name the three units of a microcomputer.
What is a CPU?
What is meant by processor memory?
What is meant by primary memory?
What is meant by secondary memory?
Name the three buses of a microcomputer.
What is an address bus?
What is a data bus?
What is a control bus?
What is an ALU?
What are the general-purpose registers available in 8085?
What is an accumulator?
What is a stack pointer?
What is a LIFO memory?
What is a program counter?
Name the five flags of 8085.
Give the flag register format for 8085.
Name the five hardware-interrupts of 8085. Give their priorities and vector
locations.
Name the software-interrupts of 8085. Give their vector locations.
How is the priority among the eight software interrupts resolved?
What is the purpose of the ALE pin in 8085?
What are the purposes of the S0, S1 and IO/M pins in 8085?
What is the purpose of the READY pin in 8085?
What is the purpose of the HOLD pin in 8085?
What is the purpose of the RESETOUT pin in 8085?
What happens during the reset mode of 8085?
What happens during the hold mode of 8085?
What happens during the halt mode of 8085?
What happens during the interrupt (INTR) mode of 8085?
Give any four differences between 8080 and 8085.
Give any four differences between 8085 and Z 80.
Give any four differences between 8085 and MC 6800.
The architectures of Intel 8085 and Zilog 80 are _______ intensive whereas that
of MC 6800 is ________ intensive.
Intel 8085, Z 80 and MC 6800 are capable of addressing _______ bytes of
memory.
Name any four 16-bit Ps.
Intel 8086 uses a _______ bit address and is capable of addressing _______ bytes
of memory.
Name the four segment registers of 8086.
Give the default segment: offset combinations of 8086.
2
41. What is meant by pipelining?
42. What is meant by FIFO? Give an example.
43. When a segment and offset combination is given as 480B:007A, what is the actual
physical address generated?
44. What is meant by effective address?
45. The operating mode of Intel 8086 is often termed as ___________ in the PC
world.
46. What is meant by page limit?
47. If a segment register contains 680A, what is the starting address of the segment?
48. Name the flags of 8086.
49. Give any four differences between 8085 and 8086.
50. What is meant by postman clock?
UNIT I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Explain the architecture of a microcomputer.

Compare micro, mini and large computers.
Explain the architecture of Intel 8085.
Explain the architecture of Z 80.
Explain the architecture of MC 6800.
Explain the differences between the architectures of Intel 8085 and Z 80.
Explain the differences between the instruction sets of Intel 8085 and Z80.
Explain the differences between the architectures of Intel 8085 and MC 6800.
Explain the architecture of Intel 8086.
Explain the differences between Intel 8085 and Intel 8086.
UNIT II
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Name the five instruction groups of 8085.

Name the five addressing modes of 8085.
Name the five machine cycles of 8085.
What is the meaning of the following instruction?
What are the flags affected by the execution of the following instruction?
What is (or are) addressing mode (or modes) used in the following instruction?
What is meant by an instruction cycle?
What is meant by a machine cycle?
What is meant by an execution cycle?
Distinguish between a machine cycle and a T-state.
What is meant by a fetch-execute overlap cycle?
What are the machine cycles required by the following instruction?
How many T-states are required by the following instruction?
How many bytes are required by the following instruction?
Which group does the following instruction belong to?
Compute the time required by the following instruction.
3
UNIT II
1.
2.
3.
4.
5.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
Explain the five instruction groups of 8085 with examples.

Explain the five addressing modes of 8085 with examples.
Explain the various machine cycles of 8085.
Explain the basic timing diagram of 8085.
Draw the timing diagram of the following instruction and explain the microoperations carried out in each T-state.
UNIT III
What is a ROM?
What are the different types of ROM?
What is a PROM?
What is an EPROM?
What is an E2PROM?
What is a RAM?
What is a static RAM?
What is a dynamic RAM?
Draw a basic ROM cell.
Draw a basic static RAM cell.
Draw a basic dynamic RAM cell.
Draw a basic/typical ROM module.
Draw a basic/typical RAM module.
What is meant by NV (Non-Volatile) RAM or shadow RAM?
Differentiate between a static RAM and a dynamic RAM.
Name the minimum control signals required for ROM and RAM.
How can bus contention be avoided while interfacing a ROM chip with CS (Chip
Select) pin alone for control?
Draw the diagram for Q17.
How can bus contention be avoided while reading a RAM chip with WE (Write
Enable) pin alone for control?
Draw the diagram for Q19.
Name the types of addressing using in memory interfacing.
What is meant by linearly decoding?
What is meant by fully decoding?
What is meant by bus contention?
What is meant by DMA?
Name the five types of I/O operations.
What is meant by programmed I/O?
What is meant by I/O mapped IO?
What is meant by memory mapped IO?
What is meant by interrupt driven I/O?
What is meant by polling?
What is meant by hand-shaking?
How does a shower peripheral communicate with the P?
4
UNIT III
1.
2.
3.
4.
5.
6.
Explain the various memory addressing schemes.

Explain the read cycle timings of a (typical) ROM/RAM chip.
Explain the write cycle timings of a (typical) RAM chip.
Interface four 2K8 ROM chips to 8085.
Interface four 4K8 RAM chips to 8085.
Interface the following memory chips to 8085.
(i)
one 2Kx8 ROM chip
(ii)
four 4Kx8 RAM chips
7. Interface the following memory chips to 8085 with the address space specified.
(i)
2Kx8 ROM 0000 07FF
(ii)
4Kx8 RAM 4000 4FFF
8. Explain the DMA data transfer.
9. Explain the HOLD timings of 8085.
10. Explain the various IO structures or various data transfer schemes (i.e., about the
programmed IO and the DMA).
11. Explain the various programmed IO or programmed data transfer schemes (i.e.,
about the synchronous data transfer scheme, the asynchronous data transfer
scheme and the interrupt-driven data transfer scheme).
12. Explain the IO structure/data transfer modes (i.e., about the serial data transfer,
the programmed data transfer and the DMA) of 8085.
UNIT IV
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
Why is an interrupt structure needed?

What happens during an interrupt (INTR) mode?
Name the hardware interrupts of 8085.
Name the software interrupts of 8085.
Name the hardware interrupts of Z80.
Name the software interrupts of Z80.
What is the purpose of SIM instruction?
Give the format of SIM instruction.
What is the purpose of RIM instruction?
Give the format of RIM instruction.
What are the purposes of EI and DI instructions?
What is meant by vectored interrupt? Give examples.
What is meant by direct interrupt? Give examples.
When should you go for a non-maskable interrupt?
How is a multiple-interrupt avoided?
Why are the other maskable interrupts disabled when the microprocessor
recognizes a maskable interrupt?
What is an interrupt mode 0 of Z80?
What are the equivalents of 8085 to those three interrupt modes of Z80?
5
21. What is 8259?
22. The maximum number of interrupts resolved by 8259 is _________ without
cascading and __________ with cascading.
23. Name the five arbitration modes of 8259.
24. What is meant by fully nested priority mode of 8259?
25. What is meant by rotating equal priority mode of 8259?
26. What is meant by rotating specific priority mode of 8259?
27. What is meant by basic mask mode of 8259?
28. What is meant by special mask mode of 8259?
29. What is meant by polled mode of 8259?
30. When do you require interrupt-driven IO and when DMA?
UNIT IV
1.
2.
3.
4.
5.
Explain the interrupt structure of 8085.

Explain the advantages of interrupt-driven IO over the other methods of data
transfer.
Explain the function of the PIC 8259 with relevant diagram.
Differentiate between software interrupts and hardware interrupts.
Explain the interrupt acknowledge cycle of 8085.
UNIT V
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
What is an assembler?
Give any four advantages of using an assembler.
What is a pseudoinstruction? Give an example.
What is the purpose of the directive, ORIGIN (ORG)?
What is the purpose of the directive, EQUATE (EQU)?
What is the purpose of the directive, DEFINE BYTE (DB)?
What is the purpose of the directive, DEFINE WORD (DW)?
What is the purpose of the directive, TITLE?
What is the purpose of the directive, PAGE or EJECT?
What is the purpose of the directive, SPACE?
What is the purpose of the directive, END?
What is the purpose of the directive, LIST?
What is a one-pass assembler?
What is a two-pass assembler?
What is a macro assembler?
What is a cross assembler?
What is a resident assembler?
What is a meta assembler?
What is meant by debugging?
Give the three popular types of debugging methods.
What is meant by single-stepping a microprocessor?
What is meant by breakpoint facility?
What is meant by a simulator?
6
24. Debug the following program.
MOV B, 02H
L1: LXI D, FFFFH
L2: DCX D
JNZ L2
DCR B
JNZ L1
RET
25. What happens when the following program is assembled using a one-pass
assembler?
IN portA
L1: CPI set_pt
JC L2
SUI set_pt
JMP L1
L2: HLT
26. What is a subroutine?
27. Differentiate between a subroutine and an interrupt.
28. What is an algorithm?
29. What is a flow chart?
30. Differentiate between an algorithm and a flow chart.
UNIT V
1.
2.
3.
4.
5.
6.
7.
8.
9.
Write an assembly language program to add two 8-bit numbers and store the sum
in the memory location 4500H. Draw the flow chart.
Write an assembly language program to subtract an 8-bit number from another
and store the difference in the memory location 4500H and the sign bit i.e., the
carry bit in 4501H. Draw the flow chart.
Write an assembly language program to multiply two 8-bit numbers and store the
product in the memory location 4500H. Draw the flow chart.
Write an assembly language program to multiply two 8-bit numbers through
direct binary multiplication method and store the product in the memory location
4500H. Draw the flow chart.
Write an assembly language program to divide an 8-bit number by another and
store the quotient in the memory location 4500H and the remainder in 4501H.
Draw the flow chart.
Write an assembly language program to add two 16-bit numbers and store the
sum in the memory location 4500H. Draw the flow chart.
Write an assembly language program to subtract a 16-bit number from another
and store the difference in the memory location 4500H and the sign bit i.e., the
carry bit in 4502H. Draw the flow chart.
Write an assembly language program to multiply two 16-bit numbers and store
the product in the memory location 4500H. Draw the flow chart.
Write an assembly language program to find the largest number from a given set
of 8-bit numbers and store the result in 4500H. Draw the flow chart.
7
10. Write an assembly language program to find the smallest number from a given set
of 8-bit numbers and store the result in 4500H. Draw the flow chart.
11. Write an assembly language program to arrange a set of 8-bit numbers in
ascending order. Draw the flow chart.
12. Write an assembly language program to arrange a given set of 8-bit numbers in
descending order. Draw the flow chart.
13. Write an assembly language program to convert a given 8-bit hexadecimal
number to decimal number. Draw the flow chart.
14. Write an assembly language program to convert a given 8-bit decimal number to
hexadecimal number. Draw the flow chart.
15. Write an assembly language program to convert a given BCD number to binary
number. Draw the flow chart.
16. Write an assembly language program to convert a given binary number to BCD
number. Draw the flow chart.
17. Write an assembly language program to add two BCD numbers. Draw the flow
chart.
18. Explain the microprocessor-based temperature control system with relevant
flowchart.
19. Explain the microprocessor-based speed control system with relevant flow chart.
20. Explain the microprocessor-based traffic control system with relevant flow chart.
1.
It is desired that two 8-bit numbers are read from the hex keyboard on your trainer
kit and added and the sum is displayed in the 7-segment display on your kit. Write
an assembly language program to accomplish this task. Assume that the hex
keyboard and the 7-segment display are interfaced to 8085 with an 8279. The hex
key matrix and the display section have been shown below. The code for the key
pressed is stored in FIFO RAM of 8279 according to
X X SC SC SC RL RL RL
where the SC field represents the binary equivalent of the scan line active during the
key press and the RL field represents the binary equivalent of the return line pulled
during the key press. The 7 display segments are activated according to the code
written into the display RAM of 8279. The display code is of the form
d c b a dp e g f
where a, b, c, d, dp, e, f & g are the display segments.
Assume (i) 00H as control word for selecting desired keyboard and display modes,
(ii) 40H as control word for selecting read FIFO RAM mode to read key code from
FIFO RAM, (iii) 90H as control word for selecting write display RAM mode to
write display code into display RAM, (iv) CCH as control word for blanking the
selected segments, (v) 01H as port address to control register of 8279 and (vi) 00H
as port address to either FIFO RAM or display RAM.
2.
kit and subtracted from one another and the difference is displayed in the 7-segment
display on your kit. Write an assembly language program to accomplish this task.
Assume that the hex keyboard and the 7-segment display are interfaced to 8085 with
an 8279. The hex key matrix and the display section have been shown below. The
code for the key pressed is stored in FIFO RAM of 8279 according to
d c b a dp e g f
3.
kit and multiplied by one another and the product is displayed in the 7-segment
d c b a dp e g f
4.
kit and divided by one another and the quotient is displayed in the 7-segment
d c b a dp e g f
5.
It is desired that a set of 8-bit numbers is read from the hex keyboard on your trainer
kit and the largest number among them is found and displayed in the 7-segment
d c b a dp e g f
6.
It is desired that a set of 8-bit numbers is read from the hex keyboard on your trainer
kit and they are arranged in ascending order and the first number in the ordered
array is displayed in the 7-segment display on your kit. Write an assembly language
program to accomplish this task. Assume that the hex keyboard and the 7-segment
display are interfaced to 8085 with an 8279. The hex key matrix and the display
section have been shown below. The code for the key pressed is stored in FIFO
RAM of 8279 according to
d c b a dp e g f
7.
It is desired that a 3-letter word is read from the hex keyboard on your trainer kit
and displayed in the 7-segment display on your kit and made to blink every second.
Write an assembly language program to accomplish this task. Assume that the hex
keyboard and the 7-segment display are interfaced to 8085 with an 8279. The hex
key matrix and the display section have been shown below. The code for the key
pressed is stored in FIFO RAM of 8279 according to
d c b a dp e g f
8.
It is desired that a 3-letter word is read from the hex keyboard on your trainer kit
and rolled through the 7-segment display on your kit. Write an assembly language
program to accomplish this task. Assume that the hex keyboard and the 7-segment
display are interfaced to 8085 with an 8279. The hex key matrix and the display
section have been shown below. The code for the key pressed is stored in FIFO
RAM of 8279 according to
d c b a dp e g f
9.
Consider the following traffic diagram. An operator is supposed to control both the
left-right and up-down traffic manually using the keys in front of him. The functions
of the keys are as follows:
(i) The LR key allows the left-right traffic to begin with G2 & G4 ON, R1 & R3
ON, PS2 & PS4 OFF (RED) and PS1 & PS3 ON (GREEN),
(ii) The Y key allows the yellow lights alone to be ON and
(iii) The UD key allows the up-down traffic to begin with G1 & G3 ON, R2 & R4
ON, PS1 & PS3 OFF and PS2 & PS4 ON.
Simulate this situation through an assembly language program with the hex keys A,
B & C on your trainer kit in the place of the traffic control keys LR, Y & UD
respectively. Assume that the traffic lights have been connected to the pins of port A
and B of the PPI 8255 as shown in the table below
G1 G2 G3 G4 R1 R2 R3 R4 Y1 Y2 Y3 Y4 PS1 PS2 PS3 PS4
Also assume (i) 80H as control word for selecting port A and B of 8255 as output
ports, (ii) 0FH as port address to control register of 8255, (iii) 0CH as port address
to port A of 8255 and (iv) 0DH as port address to port B of 8255.
10.
A stepper motor has been interfaced to 8085 with a buffer cum driver as shown
below. An operator is supposed to control the stepping speed of the motor manually
using the keys in front of him. The functions of the keys are as follows: (i) The key
L allows the motor to advance one step every second. (ii) The key M allows the
motor to advance one step every half a second. (iii) The key H allows the motor to
advance one step every quarter a second. Simulate this situation through an
assembly language program with the hex keys A, B & C on your trainer kit in place
of the speed control keys L, M & H respectively. Assume C8H as port address to
buffer cum driver.
D7 (d)
D6 (c)
D5 (b)
D4 (a)
D3 (dp)
D2 (e)
D1 (g)
D0 (f)
dp
Display section
RL0
RL1
RL2
RL3
RL4
RL5
RL6
RL7
SC0
SC1
Hex key matrix
PS1
PS1
G1
PS4
G2
Y2
Y1
R2
PS2
R1
R3
PS4
R2
Y3
Y2 G2
G3
PS3
PS3
Traffic diagram
PS2
D3
D1
D0 - D3
B1
A1
Buffer
cum
driver
D2
A2
D0
A1, A2, B1 & B2 are

stator magnets.
Stepper motor interface
B2

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6EC: MICROPROCESSOR AND APPLICATIONS

Comparison of large, mini and microcomputers.

30. The interrupt structure of Intel 8085.

6E1 MICROPROCESSOR LAB - I

Architecture of the 8-bit microprocessor, 8085:

Serial I/O Control

Stack Pointer (16)

Timing and Control

HI= Hig h Im ped anc e sta te; X= unsp ecified.

< --- 8 b its --->< --- 8 b its --->

< --- 16 b its --->

Instruction format for 8085:

I. Data transfer instructions:

MVI mem, data8

LXI rp, data16

( mem ) AND ( A ) ( A ) or (( HL )) AND ( A ) ( A )

Jump on carry. The program sequence is transferred to the

Jump on plus. The program sequence is transferred to the

Return on parity even.

(addr8) is specified in the instruction, is transferred to the

The 8085 interrupt system:

has the highest priority. In order for the

8085 instructions that affect status flags:

+ indicates that the particular flag is affected;

Instruction timings of 8085

Memory read cycle timings of 8085

Memory write cycle timings of 8085

Hinds to determine the number of clock cycles (T-states) required by an instruction:

Opcodes for 8085 Instruction Set

Procedure to write a program in the PROGRAM SHEET:

Procedure to write a program in the PROGRAM SHEET:

Opcodes for 8085 Instruction Set

Programmable Peripheral Interface-8255:

8255-Programmable Peripheral Interface

The 8255 is a general-purpose programmable I/O interfacing device. It provides 24

Control word for Bit Set/Reset (BSR) Mode

Control word for I/O Mode

Input port timing for Port A:

Output port timing for Port A:

Mode 1 Status Word for Input Configuration

Mode 1 Status Word for Output Configuration

Mode 2: Bidirectional handshake mode: Port A is programmed as a bidirectional I/O port

Programmable Keyboard/Display Interface-8279:

Display/Keyboard mode set control word

Clear control word

FIFO status word

Write display RAM control word

Character code format

Display/Keyboard mode set control word

Read FIFO/sensor RAM control word

AI (AutoIncrement)when 1, the row address is automatically incremented by one after

Character code format for depressed key

JNC END (410Eh)

END: STA 4202h

END: STA 4202h

RESULT: (SAME AS BEFORE)

JNC END (410Dh)

JNC END (4111h)

END: STA 4202h

JNC END (4110h)

RESULT: (SAME AS BEFORE)

END: STA 4202h

JNZ LOOP (410Ch)