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Interconnects
(1)
Preface
This chapter covers the essentials of the design of on-chip and
on-board interconnects. An emphasis is given to the transmission
line effect of interconnects, termination schemes, and impedance
matching networks.
The materials covered in this chapter are an essential part of the
4th-year elective course ELE-863 VLSI Circuits and Systems for
Data Communications offered by the Department of Electrical and
Computer Engineering at Ryerson University, Toronto, Ontario,
Canada. The materials of this chapter are drawn from various
published texts and research papers. Some of the major references
are listed at the end of the chapter. Students are strongly
encouraged to read the cited references in the chapter to gain
further knowledge of the subjects covered in this chapter.
The materials of this chapter can be freely distributed for
educational purposes only. Please report any error of this lecture
note to Professor Fei Yuan via email at fyuan@ryerson.ca.
(2)
Chapter Outline
Introduction
Thickness of Interconnects
Minimum Width of Interconnects
Resistance of Interconnects
Capacitance of Interconnects
Inductance of Interconnects
Modeling of Interconnects
Transmission Line Effect
Termination Schemes
Impedance-Matching Networks
References
(3)
Introduction
Interconnects in ICs
Typical interconnects encountered in ICs include metal layers,
silicidated poly layers, silicided n+ and p+ diffusion layers, vias
connecting different metal layers, contacts connecting metal layers
and diffusion regions, and contacts connecting metal and poly
layers.
The scaling of MOS devices has been more aggressive than the
scaling of the height of interconnects the performance of ICs, in
particular, the propagation delay, is largely affected by
interconnects.
Table 1: Scaling of interconnects.
Parameters
VDD
CMOS-0.35
3.3V
Lmin
0.35m
Min. width
of metal-1
Min. width
of poly
VIA12
0.5m
Contact
0.4m
Min. height
of metal-1
Number of
metal layers
6700A
0.35m
0.5m
3 metal
layers
CMOS-0.25
2.5V
(24% drop)
0.25m
(29% drop)
0.32m
(36% drop)
0.25m
(29% drop)
0.36m
(28% drop)
0.3m
(25% drop)
5700A
(15% drop)
5 metal
layers
CMOS-0.18
1.8V
(28% drop)
0.18m
(28% drop)
0.23m
(28% drop)
0.22m
(12% drop)
0.26m
(28% drop)
0.22m
(27% drop)
5300A
(7% drop)
6 metal
layers
CMOS-0.13
1.2V
(33% drop)
0.13m
(38% drop)
0.16m
(30% drop)
0.12m
(45% drop)
0.20m
(23% drop)
0.16m
(27% drop)
8 metal
layers
(4)
Introduction (contd)
The number of metal layers has been increased significantly to
combat the increased complexity of systems interconnects
constitute a very significant portion of ICs placement and
routing of interconnects that minimize the propagation delay of and
interference among interconnects have become a major research
area in design of VLSI systems.
(5)
Thickness of Interconnects
The thickness (height) of interconnects is set by process technology
and can not be changed by designers.
Thickness of interconnects has been scaled down moderately, mainly
due to the resultant increase in the resistance of interconnects,
especially global interconnects.
The top metal layer has the largest thickness. It has the highest
current rating per unit width and the lowest capacitance per unit
area to the substrate. This layer should only be used for global
signals (VDD , VSS , and clock), spiral inductors, and bonding pads.
All other metal layers typically have the same thickness. They are
usually used for local wiring, stacked spiral inductors, and
multi-layer bonding pads.
(6)
(7)
Resistance of Interconnects
Sheet Resistance
Definition of sheet resistance
R=
L
L
L
=
= R2 ,
WH
HW
W
(1)
where R2 =
is the sheet resistance with unit , L=interconnect
H
length, W =interconnect width, H=interconnect height, and
=resistivity of interconnects. Note that sheet resistance is a
process-dependent parameter and can not be changed by designers.
n-well layers have a large sheet resistance (approximately
500-1k). It is normally used as resistors and should not be used
for interconnects.
n+ layers without silicidation has a moderate sheet resistance
(approximately 50 100). It should not be used for
interconnects.
n+ and p+ layers with silicidation have a low sheet resistance
(typically less than 10). It can be used for local interconnects. For
digitally oriented CMOS technologies, often only n+ /p+-layers with
silicidation are available. Note that the sheet resistances of n+ and
p+ layers with silicidation are comparable as they are largely
determined by the resistance of the silicide layer.
Poly layers in standard digital CMOS processes are silicided.
Typical sheet resistance of silicided poly layers is R2 8. They can
be used for local interconnects.
Copyright (c) F. Yuan
(8)
(9)
1
,
f
(2)
I
H
vn
Lorezen force
(3)
(10)
(4)
we have
R(f ) = Rdc
r
L q
=
f.
2
2r
(5)
Resistivity
(109 m)
16.3
17.3
22.7
27.3
100-300
(11)
S2
SL
R = pW W =
R,
S
L
S H
(6)
(12)
(7)
(8)
(13)
6700A
Height reduction 7%
Width reduction 28%
5700A
0.5u
5300A
0.23u
0.32u
SW = SL = S, SH 1.
L
= S = SR.
R
WS
(9)
S 1
= SR.
For local interconnects : R
= SR.
For global interconnects : R
The resistance of interconnects, both local and global, increases
linearly with the scaling factor.
Selective scaling scheme has been adopted in VLSI scaling.
(14)
Capacitance of Interconnects
Area Capacitances
Ca
Substrate
(15)
Cf
Cf
Substrate
(16)
m3
T2
m2
T1
H3
m1
T1
H2
H1
Substrate
(17)
I
metal-2
I
metal-1
(18)
Inductance of Interconnects
Self-inductance of a round bond wire
2H
L0.2ln
where R=radius and H distance from the conductive
R
substrate.
1.6 H
H
, where Kf 0.72( W
) + 1 (fringe factor), W =width of the
L
Kf W
trace and H=distance from the trace to the conductive substrate.
(19)
2H 2
L0.1ln 1 + (
) .
d
(20)
Modeling of Interconnects
This section deals with the modeling of interconnects. Depending
upon the frequency of signals traveling through the interconnects
and the physical dimensions, in particular, the length of the
interconnects, the behavior of the interconnects can be
characterized at various levels of abstraction, from the simplest
lumped RC model to full transmission-line models.
(21)
(22)
Vout
H
R
V
in
Vin
V out
Substrate
(10)
1
RC .
(11)
we arrive at tp = 0.69 .
Copyright (c) F. Yuan
(23)
Vout
DL
i-1
R (DL)
Vin
V
in
i+1
R(DL)
R(DL)
C(DL)
C(DL)
Vout
R(DL)
C(DL)
C(DL)
Substrate
DL
DL
DL
DL
KCL at node i
vi vi1 vi vi+1
dvi
+
+ C(L)
= 0,
R(L)
R(L)
dt
(12)
RC
(13)
(24)
(14)
(25)
i
R i-1
V
in
i+1
Ri
C1
C i-1
Vout
RN
CN
Ci
DL
DL
DL
DL
i-1
V
in
VDD
0
V
out
VDD
0.5VDD
0
tN
N 1
(26)
i+1
R (DL)
R (DL)
R (DL)
V
in
C (DL)
C (DL)
DL
DL
DL
i+1
Vout
R (DL)
C (DL)
C (DL)
DL
N
N = R1(C
+ C2 +
... + CN}) + R2 (C
+ ...
+ CN}) + . . . + RN CN
| 1
| 2
{z
{z
N
N 1
{z
N
{z
N 1
= RC(L)2(1 + 2 + ... + N )
N (N + 1)
.
= RC(L)2
2
Because L =
L
N,
(16)
we have
1
1
N = RCL2(1 + ).
2
N
(17)
1
N = RCL2.
2
(18)
In the limit N ,
(27)
Lumped RC model
0.5Vm
0.1Vm
0.35RC
0.69RC
0.9RC
2.2RC
(19)
(20)
Copyright (c) F. Yuan
(28)
(29)
L=1mm
Vout
W=1u
Vin
Ca
Cf
Substrate
Figure 15: Example.
Consider the interconnect shown. Let the area capacitance per unit
are and the fringe capacitance per unit length be
Ca = 0.058f F/m2 and Cf = 0.043f F/m, respectively. Let the
sheet resistance R2 = 10. Estimate the propagation delay.
L
Total resistance R = R2 W
= 10k.
(30)
(31)
z+D z
Dz
V(z,t)
Substrate
I(z)
R(D z)
V(z)
L(D z)
I(z+ D z)
G (D z)
C (D z)
V(z+ D z)
(21)
(22)
(32)
(23)
(24)
(25)
(33)
(26)
(27)
(28)
(34)
(29)
and
V ez = V e(+j)z
= V ez [cos(z) + jsin(z)]
= V e(z) {cos[(z)] jsin((z)]}.
(30)
(35)
I(z) =
(31)
where
v
u R + jL
R + jL u
=t
Zo =
G + jC
(32)
Zo =
v
u
uL
t
(33)
(36)
(34)
V + = Zo I + ,
V = Zo I
(35)
we have
(37)
Reflection Coefficient
IL
V
VL
ZL
z=0
Figure 17: Terminated lines.
ZL =
VL (0)
=
IL (0)
V++V
.
1
+ V )
(V
Zo
(36)
"
ZL Zo +
V .
=
ZL + Zo
(37)
(38)
(38)
(39)
(39)
(40)
Input Impedance
I(z)
Zo
IL
V
V(z)
Z in (z)
V(0)
ZL
z=0
Zin (z) =
=
=
=
=
V (z)
I(z)
V + ez + V ez
I + ez + I ez
" z
#
e
+ VV + ez
Zo z V z
e
V+e
#
" z
e
+ V (0)ez
Zo z
e
V (0)ez
"
#
1 + V (0)e2z
Zo
.
1 V (0)e2z
(40)
(41)
V (0) =
ZL Zo
,
ZL + Zo
(41)
we have
"
ZL + jZo tan(z)
Zin (z) = Zo
.
Zo + jZL tan(z)
(42)
(42)
(43)
Zo
.
jtan(z)
(44)
Stub
Stub
(45)
VIA12
Stub
Stub
m1
(46)
(47)
Zo
V(0)
Z in(z)
ZL
z=0
"
ZL + jZo tan(z)
) = Zo
Zin (
4
ZL + jZL tan(z)
Zo2
.
=
ZL
z=
4
(43)
Zo =
v
u
u
t
ZLZin ( ).
4
(44)
(48)
Strong reflection
Zo
ZL
l/4
Zero reflection
Zo
Zo
Zo
ZL
Impedance matching
network
(49)
(50)
Zo
ZL= infinity
5V
Z1
Z1 =
Zo
.
jtan(z)
(45)
When the wave arrives at node 1 for the very first time, the voltage
and current at node 1 are computed from
V1 =
Zo
V
Zo +5Zo s
= 56 5 = 0.83V,
I1 =
Vs
Zo +5Zo
5
6Zo .
(46)
(51)
V 2 =
ZL Zo
ZL +Zo
= 1,
(47)
ZL =
I2 = V 2 = 1,
from which we obtain the voltage and current of the reflected wave
at node 2
+
V2,1
= V 2 V2,1
= 0.83V,
(48)
I2,1
+
I2 I2,1
6Z5 o .
The total voltage and current at nod 2, after the first reflection, are
obtained from
+
V2,1 = V2,1
+ V2,1
= 0.83V + 0.83V = 1.66V,
(49)
I2,1 =
+
I2,1
I2,1
5
6Zo
5
6Zo
= 0.
(52)
V 1 =
ZL Zo
ZL +Zo
ZL =5Zo
= 23 .
(50)
I1 = V 1 = 32 .
The voltage and current of the reflected wave at node 1 are
computed from
+
V1,1
= V 1V1,1
= 32 0.83V = 0.5533V,
I1,1
+
I1 I1,1
( 23 )( 6Z5 o )
(51)
5
9Zo .
The total voltage and current at node 1, after the first reflection,
are given by
+
V1,1 = V1,1
+ V1,1
+ 0.83V = 0.83V + 0.5533V + 0.83V = 2.2133V,
(52)
+
5
5
5
5
5
I1,1 = I1,1 + I1,1 + 6Zo = 6Zo + 9Zo + 6Zo = 9Zo .
(53)
+
V2,2 = V 2V2,2
= 0.5533V.
+
I2,2
I2,2
(53)
5
9Zo
=
+
= I2 I2,2
= 9Z5 o .
V2,2 = V2,2
+ V2,2
= 0.5533 + 0.5533 = 1.12V,
(54)
I2,2 =
+
I2,2
I2,2
9Z5 o
5
9Zo
= 0.
When the reflected wave arrives at node 1 for the second time
+
V1,2
= 0.5533V,
+
V1,2 = V 1V1,2
= 32 0.5533V = 0.3687V,
+
V1,2 = V1,2
+ V1,2
= 0.5533 + 0.3687 = 0.93V,
+
I1,2
= 9Z5 o ,
+
I1,2
= I1 I1,2
= ( 23 )( 9Z5 o ) =
10
27Zo .I1,2
(55)
= I1,2
+ I1,2
= 9Z5 o +
(54)
10
27Zo
10
= 27Z
.
o
(56)
+
V2,3 = V 2 V2,3
= 0.3687V.
+
(57)
+
I2,3
I2,3
I2,3
=
=
=
10
27Zo ,
+
10
I2I2,3
= 27Z
.
o
+
I2,3 + I2,3 = 0.
+
V1,3 = V 1 V1,3
= 32 0.3687V = 0.2458V.
+
V1,3 = V1,3
+ V1,3
= 0.3687 + 0.2458 = 0.6145V,
+
I1,3
I1,3
I1,3
=
=
=
(58)
10
,
27Z
o
+
10
10
) = 81Z
,
I1 I1,3
= 32 ( 27Z
o
o
+
10
10
20
I1,3 + I1,3 = 27Zo + 81Zo = 81Z
.
o
(55)
(59)
+
V2,4 = V 2V2,4
= 0.2458V.
(60)
+
V1,4 = V 1 V1,4
= 32 0.2458V = 0.1639V.
(61)
(56)
Current
5/6Zo
6
5/9Zo
5/27Zo
3.52V
4.36V
3.77V
4.02V
4.19V
3.15V
2.78V
5/81Zo
Current
2.22V
V2
0.83V
1.66V
V1
0
2t
3t
4t
5t
6t
7t
8t
9t
10t
Time
Ringing exists due to the multiple reflection at both the near and
far ends of the transmission line, arising from impedance mismatch
at both the near and far ends of the line.
The duration of the ringing depends upon the delay of the line.
The smaller the , the shorter the ringing the fast the
voltage at the far end of the transmission line reaches its
steady-state value (5V).
(57)
Zo
ZL= infty
5V
Z1
V1
0.83V
V2
0.83V
0.83V
1.66V
1.66V
0.83V
2.22V
1.39V
0.56V
1.12V
2.78V
0.74V
3.52V
0.56V
3.15V
0.93V
0.37V
0.37V
3.77V
0.62V
0.25V
4.02V
(58)
Zero reflection
Zo
Long interconnect
Zo
Zout Zo
Zo
Zo
Zo Zin
Zo
Impedance matching
network
Impedance matching
network
(59)
Zo
ZL= infinity
5V
Z1
V1 =
Zo
1
Vs = 5 = 2.5V
Zo + Zo
2
(62)
(60)
V 2
ZL Zo
=
= 1,
ZL + Zo ZL=
(63)
+
V2,1
= V 2 V2,1
= 2.5V
(64)
V2,1 = V2,1
+ V2,1
= 5V
(65)
(61)
V 1
ZL Zo
= 0.
=
ZL + Zo ZL =Zo
(66)
+
V1,1
= V 1 V1,1
= 0.
(67)
V1,1 = V1,1
+ V1,1
= 2.5V.
(68)
(69)
(62)
Zo
5V
Zo
Z1
Zo
V
Zo +Zo s
I1 =
52.5
Zo Vs
= 21 5 = 2.5V,
(70)
2.5
Zo .
(63)
V 2 =
ZL Zo
ZL +Zo
= 0,
(71)
ZL =
I2 = V 2 = 0.
from which we obtain the voltage and current of the reflected wave
+
V2,1
= V 2 V2,1
= 0,
+
I2,1 = I2 I2,1 = 0.
(72)
No reflection at node 2.
The voltage and current at nod 2 are obtained from
+
+ V2,1
= 2.5V,
V2,1 = V2,1
+
(73)
(64)
(65)
Termination Schemes
This section deals with termination schemes of interconnects. The
pros and cons of various termination schemes, namely series
termination, parallel termination, AC parallel termination, and
Thevenin termination, are investigated in detail.
(66)
(67)
No Termination
Vin
Zo=50 Ohms
Z L1
Z L,2
ZL2 Zo
1. Strong reflection at
ZL2 + Zo
the far end of the line. Voltage doubles at node 2.
ZL1 =
Rn ,
when Vout is low
Rp ,
when Vout is high
Ro,n ||Ro,p , when Vout is in transition
(74)
(68)
No Termination (contd)
Also note reflection also exists even if the signal is of low
frequencies. Sharp transitions contain high-frequency components.
These high-frequency components are subject to transmission line
effect because their wave length is comparable to the length of the
line.
Time Domain
Frequency Domain
T/2
2w
s
3w
s
4w
s
x(t) =
n=
1
2
and Cn =
where s =
T
T
Z T
0
Cn ejns t ,
(75)
x(t)ejnst dt.
(69)
Series Termination
Rs
Vin
Zo=50 Ohms
Z L1
Z L2
ZL2 Zo
1. Strong reflection at
ZL2 + Zo
the far end of the transmission line The voltage at the far end
equals to the applied voltage.
(70)
Parallel Termination
Vin
Zo=50 Ohms
Zo
Z L1
Z L2
(71)
AC Parallel Termination
Vin
Zo=50 Ohms
CT
Z L1
Z L2
RT
(72)
Thevenin Termination
Vin
Zo=50 Ohms
R1
R2
Z L1
Z L2
(73)
Impedance-Matching Networks
This section investigates the pros and cons of off-chip and on-chip
passive impedance-matching networks. In addition, it examines the
design of on-chip active impedance-matching networks. The
difficulties encountered in realization of off-chip and on-chip
termination resistors are studied. Various on-chip active
impedance-matching networks are investigated.
(74)
Metal-1
W
Poly
Contact
R=
RC RC
L
L
+
+ R2
= 8+8 .
2
2
W
W
(76)
(75)
VIA hole
Figure 36: Passive resistor termination.
The leads of passive resistors, the PCB trances and vias (if not
surface-mounted resistors) introduce unwanted parasitic
capacitances and inductances that drive the impedance of the
resistors away from 50 a perfect impedance matching using
passive resistors is difficult to achieve.
(76)
Vc
Vc
Vc
Vc
I
I
I
Triode
Symmetrical load
DN
D2
D1
M2
MN
D0
M1
V
M0
I
Digital trimming
(77)
Vc
V
I
Better linearity
in this region
called
deep triode
Vdd-Vc
Triode
V
The slope (conductance) varies with Vc
Figure 38: Termination network realized using pMOS biased in deep triode.
(78)
I
Vdd
Pich-off
M2
Vc
M1
DI
V
M1
I
M2
Symmetric load
DI
Vsat Vt
(79)
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
Width
0
1Wref
2Wref
3Wref
4Wref
5Wref
6Wref
7Wref
Resistance
Rref
Rref /2
Rref /3
Rref /4
Rref /5
Rref /6
Rref /7
(80)
Zo
Both nMOS and pMOS are sized such that they provide 50
resistance when biased in deep triode.
When V2 = VDD , pMOS is ON (triode) and nMOS is OFF. No DC
current flows through pMOS.
When V2 = 0, nMOS is ON (triode) and pMOS is OFF. No DC
current flows through nMOS.
Design difficulties : the propagation delay of the inverter must be
sufficiently small, as compared with the propagation delay of the
transmission line.
(81)
Vc1
1
Zo
Vc2
(82)
VC
Comparator
VRef
VDD
Vin
(83)
References
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Copyright (c) F. Yuan
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