p-n junctions

Intuitive description.
What are p-n junctions?
p-n junctions are formed by starting with a Si wafer (or substrate) of a given type (say: B-doped p-type,
to x the ideas) and diusing or implanting impurities of opposite type (say: n-type, as from a gas source
of P such as phosphine or implanting As ions) in a region of the wafer. At the edge of the diused (or
implanted) area there will be a junction in which the p-type and the n-type semiconductor will be in direct
contact. Refer to the Streetman-Banerjee text, section 5.1, for a description of semiconductor processing.
We will review this topic later on, before dealing with metal-oxide-semiconducor (MOS) ed-eect transisitors
(FET).
What happens to the junction at equilibrium?
Consider the idealized situation in which we take an n-type Si crystal and a p-type Si crystal and bring
them together, while keeping them grounded, that is, attached to contacts at zero voltage. At rst, the
conduction and valence band edges will line up, while the Fermi level will exhibit a discontinuity at the junction.
But now electrons are free to diuse from the n-region to the p-region, pushed by the diusion term Dn n
in the DDE. Similarly, holes will be free to diuse to the n region. As these diusion processes happen, the
concentration of extra electrons in the p-region will build up, as well as the density of extra holes in the n
region. These charges will grow until they will build an electric eld which will balance and stop the diusive
ow of carriers. Statistical mechanics demands that at equilibrium the Fermi level of the system is unique and
constant. Therefore, the band-edges will bend acquiring a spatial dependence. This is illustrated in the left
frame of the gure on page 97. Note:
1. Deep in the n-type region to the right and in the p-type region to the left the semiconductor remains
almost neutral: The contacts have provided the carriers lost during the diusion mentioned above, so that
n = ND in the quasi-neutral n region and p = NA in the quasi-neutral p region.
2. There is a central region which is depleted of carriers: Electrons have left the region 0 x xn0 , holes
have left the region xp0 x < 0, so that for xp0 x xn0 we have np < n2i . This is called the
transition region or, more often, the depletion region of the junction. Its total width is W = xn0 + xp0 .

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3. The voltage barrier built by the difusion of carriers upon putting the n and p regions in contact with
each other is called the built-in potential, Vbi (denoted by eV0 in the textbook). Streetman and Banerjee
present one possible way to calculate it. But an alternative, easier approach is based on the observation that
Vbi will be given by the dierence between the equilibrium Fermi levels in the the two regions:








ND
NA
ND NA
.
Vbi = EF n0 EF p0 = Ei + kB T ln
Ei + kB T ln
= kB T ln
ni
ni
n2i
(123)
Note that since the hole concentration in the p region, pp , is equal to NA , and the hole concentration in
the n region, pn is equal to n2i /ND , the equation above can be rewritten as:

Vbi = kB T ln
or

pp
pn


,

(124)

pp
nn
eV /(k T )
= e bi B
=
,
pn
np

(125)

where the last step is based on the fact that at equilibrium pp np = pn nn . Note: Vbi dened above is a
potential energy, measured in joules. If measured in eV, its expression will be (kB T /e) ln(ND NA /n2i ),
which is V0 in the text.

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 What happens to a biased junction?

Lets now apply a bias Va to the junction. We consider Va positive when positive bias is applied to the
p-region, as illustrated in the gure. If Va > 0 (forward bias), the eld in the depletion region will be
reduced, so that it will not balance anymore the diusion current of electrons owing to the left. Thus, electron
supplied from the contact at the extreme right will replenish those electrons entering the p-type region. This
will result in a current density J3 . Having entered the p region, electrons will eventually recombine with holes.
The contact at left will provide the holes necessary for this recombination process, giving rise to a component
J4 of the total current density. A similar sequence of events will happen to holes: Some will diuse to the
n region (yielding the component J1 of the current density) recombining there with electrons provided by a
current density J2 from the right-contact.
If, instead, we apply a negative Va (reverse bias), the eld in the depletion region will increase and the
associated drift current will be larger than the diusion current. However, the ow of electrons from the p
region will be negligibly small, since there are very few electrons in p-doped Si. Similarly for holes in the n
region. Therefore, the reverse current will be very small. This shows that p-n junctions behave like diodes,
rectifying the current ow.
Lets now get back to the equilibrium condition and start to analyze the junction quantitatively.

Equilibrium.
Lets consider the band-bending and carrier densities at equilibrium.
Poisson equation. First, the Poisson equation describing the band bending in the depletion region is:

d2 (x)
e
=

(p n + ND NA ) .
dx2
s

(126)

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This is a nonlinear equation since the carrier densities, p and n, depend on the potential (x) itself:


n(x) = ni exp

p(x) = ni exp

EF,n0 Ei,n0+e(x)
kB T

Ei,p0 EF,n0 e(x)

kB T

= nn ee(x)/(kB T )
,

(127)

= pp ee(x)/(kB T )

where nn and pp are the electron and hole densities in the quasi-neutral n and p regions, respectively.
Depletion approximation. We can simplify Poisson equation, Eq. (126), by employing the depletion
approximation: Lets assume that the electric eld vanishes outside the depletion region and lets also ignore
+
the charge due to free carriers in the depletion region xp0 x xn0 (indeed we will have ND
>> n for

0 x xn0 and NA
>> p for xp0 x < 0, since we have depletion of free carriers in these regions),
so that:
d2 (x)
eND
=

for 0 x xn0 ,
(128)
dx2
s

d2 (x)
=
dx2
so that, using the boundary conditions

eNA
s


d 
dx  x=x

p0

for xp0 x < 0 ,


d 
=
dx  x=x

(129)

= 0,

n0

(expressing the fact that the electric eld vanishes at the edges of the depletion region) and (xp0 ) = p0 ,
(x = xn0 ) = n0 , expressing the fact that at the edges of the depletion region the carrier concentration

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approaches the concentration in the quasi-neutral regions, we have:

(x) =

eND
2

2s (x xn0 ) + n0

(0 x xn0 )
(130)

eNA
2
2s (x + xp0 ) + p0

(xp0 x 0) .

Note that the maximum electric eld occurs at x = 0:

Fmax =

eNA
eND
xp0 =
xn0 ,
s
s

(131)

where the last equality follows from charge neutrality which requires

NA xp0 = ND xn0 .

(132)

Depletion width. To calculate the width of the depletion region, note that

Vbi = en0 ep0 .

(133)

Moreover, the continuity of the potential at x = 0 implies, from Eq. (130):

0 = (0 ) (0 ) = p0 n0 +

eNA 2
eND 2
xp0 +
x .
2s
2s n0

(134)

Using now the charge-neutrality condition, Eq. (132), this becomes

2
eNA ND
eND 2
2
0 = p0 n0 +
x
+
x .
n0
2
2s NA
2s n0

(135)

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Inserting into this equation the expression for p0 n0 from Eq. (133) and using Vbi from Eq. (123), we
have:


e2 ND
NA ND
2
=
Vbi = kB T ln
(N
+
N
)
x
(136)
A
D
n0 ,
2s NA
n2i
so that:


 1/2
2s NA Vbi
xn0 =
.
(137)
e2 ND (NA + ND )
Similarly:


 1/2
2s ND Vbi
xp0 =
.
(138)
e2 NA (NA + ND )

Asymmetric junction. In the simpler case of a very highly asymmetric junction (for example: NA = 1015
cm3 and ND = 1019 cm3 , we can ignore NA with respect to ND in Eqns. (137) and (138) above, so
that:
 1/2




2s Vbi 1/2
2s NA Vbi
xp0
,
xn0
<< xp0 .
(139)
2
e2 NA
e2 ND
So, the heavily-doped n-region exhibits essentially no depletion. This is a general property: The larger the
concentration of free carriers, the smaller the voltage which can drop in the region. In the limit of a metal, we
know that no electric eld can be sustained, because any voltage drop will be eectively screened by the large
concentration of free carriers.

O equilibrium: The Shockleys diode equation.

Lets apply a bias Va to the junction. We shall rst consider the ideal case of no generation/recombination in
the depletion region (ideal diode). We shall later consider deviations from this ideal condition.
Note: Since the applied bias Va is almost exclusively measured in Volt, it is convenient to indicate by Vbi the
built-in voltage, also measured in V, so that the built-in potential and the external bias can be simply added.
Thus, in the following Vbi indicates the built-in voltage, measured in V.

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 Ideal diode: Lets rst consider the ideal diode; that is: An ideal junction in which there are no generationrecombination processes in depletion region. In addition, lets make the following simplifying assumptions:
1. The concentrations of free carriers injected into the quasi-neutral regions are small enough so that we can
neglect their charge compared to the charge of the majority carriers when solving Poisson equation (low-level
injection).
2. The concentration of free carriers everywhere is small enough so that we can use Maxwell-Boltzmann
statistics (that is, the high-T limit) instead of the full Fermi-Dirac statistics.
3. The quasi-neutral regions are innitely long.
4. Finally, theres no electric eld in the quasi-neutral regions, so that only diusion controls the current-ow
in these regions.
Also, the calculation of all of the components of the current density J1 through J4 in the gure (right frame
at page 97) is dicult. However, we know that J2 = J1 and J3 = J4 , so we need to calculate only the
diusion currents in the quasi-neutral regions J1 and J3 . Moreover, it will be convenient to compute J1 (that
is, the hole current Jp before it starts decreasing (due to recombination with electrons in the n region) at
x = xn0 and J3 = Jn at x = xp0 (for the same reason).
First of all, we can follow again the same procedure we have followed above to obtain the width of the
depletion region simply replacing the built-in potential Vbi with its value modied by the applied bias,
Vbi Va , obtaining:


2s NA (Vbi Va ) 1/2
xn0 =
.
(140)
e2 ND (NA + ND )
Similarly:


xp0 =


2s ND (Vbi Va ) 1/2
,
e2 NA (NA + ND )

(141)

Thus, the depletion region shrinks under forward bias (Va > 0) but grows under reverse bias (Va < 0).
From Eq. (127) and from the right frame of the gure at page 97 we see that for the concentrations of the
free minority carriers which spill-over (electrons spilling over into the p regions and holes spilling over into the

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n region) we have (using assumption 2 above):

e(Vbi Va )/(kB T )

= np0 eeVa /(kB T )

n(x = xp0 ) = nn0 e

(142)

p(x = xn0 ) = pn0 eeVa /(kB T ) ,

so that the excess carriers at the edges of the depletion region are:



eVa /(kB T )

n(xp0 ) = np0 e

p(xn0 ) = pn0 eeVa /(kB T ) 1

(143)

Using now assumption 4, the current in the quasi-neutral regions will be:

dp

Jp = eDp dx

J = eD dn
n
n dx

(x > xn0 )
(144)

(x < xp0 ) .

The continuity equations for the hole current in the quasi-neutral n region (the component J1 in the gure
for x > xn0 ) and for the electron current in the quasi-neutral p region will be:

pn
1 Jp pn pn0

t
e x
p

np = 1 Jn np np0
e x
n
t

(x > xn0 )
(145)

(x < xp0 ) ,

where p and n are the (recombination) lifetimes of the minority holes and electrons in the quasi-neutral

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regions. Combining Eq. (144) and Eq. (145) we get:

p p

2 pn
pn

=
D
n p n0

p
2
t
x

np = Dn np np np0
n
t
x2

(x > xn0 )
(146)

(x < xp0 ) .

At steady state, the general solutions are:

x/Lp

+ B ex/Lp
pn(x) = pn0 + A e

n (x) = n
x/Ln
+ D ex/Ln
p
p0 + C e

(x > xn0 )
(147)

(x < xp0 ) ,

where Lp = (Dp p )1/2 and Ln = (Dn n )1/2 are the hole and electron diusion lengths in the quasineutral regions and A, B , C , and D are integration constants to be determined by the boundary conditions.
The rst of these boundary conditions is determined by the concentrations of the minority carriers far away in
the quasi-neutral regions: pn (x ) = pn0 and np (x ) = np0 , which implies B = C = 0.
Another boundary condition results from the requirement that values of pn and np at the edges of the
depletion region match the values pn (x = xn0 ) and np (x = xp0 ) given by Eq. (143) above, so that:



eVa /(kB T )

1 e(xxn0 )/Lp

pn (x) = pn0 + pn0 e



np (x) = np0 + np0 eeVa /(kB T ) 1 e(x+xp0 )/Ln

(x > xn0 )
(148)

(x < xp0 ) .

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Finally, by Eq. (144):

eDp pn0
eV
/(k
T
)
a
B

e
1 e(xxn0 )/Lp

Lp
Jp (x) =


J (x) = eDn np0 eeVa /(kB T ) 1 e(x+xp0 )/Ln

n
L
n

(x > xn0 )
(149)

(x < xp0 ) .

It is important to note that these current densities vary with x because, for example, as Jp (x) decreases as
x increases, the hole current it represents (J1 in the gure at page 97) is transformed via recombination
processes into an electron current (J2 in that gure). So, the total current will be independent of x. This
constant value can be obtained thanks to our assumption that theres no generation/recombination in the
depletion region. In this case we can evaluate the currents in Eq. (149) at a position in which they have not
yet started to decay due to recombination, so Jp at x = xn0 and Jn at x = xp0 . Therefore the total
current will be:





eDn np0  eVa /(k T )
eDp pn0
eVa /(kB T )
B
e
Jtotal = Jp (xn0 ) + Jn (xp0 ) =
+
1 = Js e
1
Lp
Ln
(150)
where Js is the saturation current density (the maximum current density we have under reverse bias, that
is, for Va ). Equation (150) is known as Shockley (or diode) equation. The gure in the next
page illustrates the qualitative behavior of Jtotal as a function of applied bias Va .

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Va

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A few considerations about Shockleys equation:

1. Under very large reverse bias (Va ) we see that Jtotal Js , the saturated reverse current.
This current is due only to the drift of those few minority carriers (holes in the n-region, electrons in the
p-region) which are thermally generated. We can increase the reverse current by increasing the density of
minority carriers by for example iluminating the sample. This is a photo-diode.
2. Under forward bias the current is dominated by the diusion component. Its easy to see: The drift
component does not change much with bias. This is because this component is limited by how many
minority carriers (pn0 and np0 ) are available to drift and these do not depend on bias. On the contrary,
the diusion current is limited by how many majority carriers (pp0 and nn0 ) can surmount the barriers of
heighth e(Vbi Va ). And this depends exponentially on the applied bias.
3. In an asymmetric junction the total current is dominated by the most heavily-doped side of the junction. For
example, in a junction with NA >> ND , we will have np0 << pn0 , so that

eDp pn0  eVa /(k T )
B
e
Jtotal Jp (xn0 ) =
1 .
Lp

(151)

4. There is an equivalent way to calculate the current.

Consider the hole current at the edge of the n depletion region, Jp (x = xn0 ). This current must be large
enough to maintain a steady-state hole population in the quasi-neutral n-region as holes recombine. From
the rst of equations (148) we have that the total hole charge in the n-region is

eVa /(kB T )

Qp = eApn0 e

 
xn0

(xxn0 )/Lp
dxe
= eALp pn0

eVa /(kB T )


.

(152)
Since holes disappear via recombination every p seconds, the rate at which the hole charge disappear will
be:




Qp
Lp
Dp
eVa /(kB T )
eVa /(kB T )
= eA pn0 e
1 = eA
pn0 e
1 ,
(153)
p
p
Lp

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having used the fact that Lp /p = Dp p /p = Dp /p = Dp / Dp p = Dp /Lp . Therefore, in
order to replenish this charge, we must have:


Qp
Dp
eVa /(kB T )
Jp (xn0 ) =
= e
pn0 e
1 ,
(154)
Ap
Lp
which is the same result we have obtained before (the rst of Eqns. (149)) from the diusion current. This
method of calculating the current is called charge control method.
Junction breakdown.
From what we have seen so far we may conclude that under reverse bias the current will approach asymptotically
the value Js as we apply an ever increasing voltage. However, this is not what happens: The Shockley
equation (150) describes correctly the behavior of the diode only as far as Va > VBD , some critical
breakdown voltage VBD . As soon as the reverse bias exceeds this value the current increases dramatically.
This is due to eects which we have not yet considered and which go beyond the simple assumptions we have
made so far:
1. Avalanche Breakdown.
We have assumed that electrons and holes can be described by the DDEs, so that they always remain at
(or near) thermal equilibrium. But we have seen before (pages 75-77 of the Lecture Notes, Part 1) that
under a high electric eld charge carriers can gain kinetic energy in excess of the thermal value (3/2)kB T .
Whenever carriers gain from the eld an amount of kinetic energy exceeding the vaue of the gap of the
semiconductor, Eg , impact ionization can occur: This is a process by which a conduction carrier (say, an
electron in the CB, just to x the ideas) hits (via the Coulomb force) another electron in the valence band.
In this collision process energy is transfered from the conduction electron to the valence electron. The latter
is excited into the CB, leaving a hole in the VB. The net eect is that the original electron loses an amount
Eg of kinetic energy generating an electron-hole pair. Actually, for such a process to occur, it is not
enough to have an intial electron with energy equal to Eg , since momentum conservation also holds and this
implies that for each semiconductor there exists a minumum threshold kinetic energy Eth > Eg below
which impact ionization cannot occur.

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The top frames of the gure on the previous page show the inization rate (that is, the number of ionizations
per unit time) obtained by various quantum-mechanical calculations for electrons and holes in Si. A common
approximation made for the ionization rate, 1/ii , as a function of electron or hole kinetic energy, E , in the
CB and VB, repectively, is the so-called Keldysh formula:

1
B
=
ii (E)
I (Eth )


E Eth p
,
Eth

(155)

for E > Eth , vanishing otherwise. The constant B is a dimensionless parameter and 1/ (Eth ) is the
scattering rate at the threshold energy. The energy Eth is the minimum energy (dictated by energy and
momentum conservation) a carrier must have in order to be able to generate electron-hole pairs. Clearly,
Eth > Eg by energy conservation. But, as we said above, momentum conservation may require that
Eth be much higher, since the recoil carriers and the generated carriers will have to share the available
momentum and so cannot in general have vanishing energy. The coecient p at the exponent takes the
value of 2 for semiconductors with direct gap. In general, it takes values as high as 6 (as determined
by complicated calculations). Lower values for p imply a soft threshold (carriers will ionize with slowly
increasing probability as E grows beyond Eth ). Large values of p imply a hard threshold: Ionization
will occur almost immediately as the energy of the carrier crosses the threshold energy. Phonon-assisted
processes (in which one or more phonons are emitted or absorbed during the ionization process) can soften
the threshold, relaxing the restrictions posed by momentum conservation... As you see, the situation is
particularly complicated...
The bottom frame of the gures on page 109, instead, show the ionization coecient as a function of
the electric eld in a homogeneous situation (that is: innitely long crystal with position-independent electric
eld). This parameter is most often of interest in the breakdown of p-n junctions. It is dened as the
number of pairs generated per unit length, so that it also represents the rate at which the current density
increases (per unit length): Considering for now only electrons:

dJn
= n Jn .
dx

(156)

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Since each electron at energy E generates electron-hole pairs at a rate 1/ii (E), if f (E) is the electron
distribution function, then:

f (E)
1
dE (E)
n =
(157)
,
nvd
ii (E)
where n is the electron density and vd is the drift velocity. It can be seen (perhaps not too trivially) that
the functional dependence of ii as given by Eq. (155) does not aect n too much. On the contrary, the
shape of the distribution function f (E) as a function of the eld dramatically aects n . Therefore, the
whole game consists in estimating how f changes with F .
Shockley had the basic idea that only those electrons which manage to be accelerated to Eth without
losing energy to phonons will contribute to the ionization process. Lets dene by Pph (E , E)dE the
probability per unit time that an electron of kinetic energy E will scatter (via phonon collisions) into a state
at energy E . Then, the probability that an electron scatters (into any other energy state) per unit time is
1/ph (E) =
dE Pph (E , E). If Pnoph (t) is the probability that the electrons has not scattered up
to time t, the probability that it will not have scattered up to t + dt will be:


Pnoph(t + dt) = Pnoph(t)


1 dt

dE Pph (E , E)


.

(158)

Solving this equation for a time interval [t1 , t2 ], we get


Pnoph = exp

 t
2
t1


dt

dE Pph (E , E)


= exp

 t
2
t1

dt
ph (E)


.

(159)

(Note that E and E are functions of time due to their acceleration in the eld, so the integration is not
trivial). Now, the probability that an electron will not scatter with phonons while being accelerated from
energy E = 0 to E = Eth can be obtained from Eq. (159) by using the chain-rule (lets consider only the
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1D case for simplicity):

dE
dE dk
dE eF
=
=
= eF v
dt
dk dt
dk h

dE
,
eF v

dt =

since v = (dE/dk)/
h. Then:


Pnoph = exp

1
eF

 E
th
0

dE
ph (E)v(E)


F0 /F

= e

(160)

E
where F0 = 0 th dE/[eph (E)v(E)] is a constant (that is, independent of the eld), so that:
(F ) = 0 eF0 /F .

(161)

Clearly, one can argue about the assumption that after every collision the electrons must start from zero
energy. Nevertheless, this lucky electron model captures the basic feature of the ionization coecient at
small elds F , exp(constant/F ).
Avalanche. As soon as impact ionization begins to take place in a p-n junction under reverse bias, the
current begins to increase. This is obvious from the denition of the ionization coecient, Eq. (156). But
a run-away phenomenon can actually occur: If the electric eld in the depletion region of the reversed-bias
junction is suciently large, one electron may impact-ionize, creating an electron-hole pair. The generated
electron and hole may now be strongly accelerated by the eld, thus gaining kinetic energy above the
ionization threshold and, in turn, impact-ionize themselves. Clearly, this process resembles a chain reaction
and it can lead to a fast and dramatic increase of the current. For obvious reasons it is called avalanche
breakdown.
[Ultimately, as more and more carriers are generated, we reach whats called a high-level injection situation in which the depletion
region ceases to be depleted. Under these conditions the resistivity of the depletion region drops, and so the potential drop across
it and, nally, the electric eld. This will put a limit to the run-away phenomenon.]

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In order to see under which conditions avalanche can be triggered, lets generalize Eq. (156) to the case of a
p-n junction under strong reverse bias. Lets refer to the gure on page 116. As we saw above, the current
is due to the drift of those few minority carriers which enter the depletion region. Consider now the initial
minority-electron current injected from the left. This will grow as:

or

dJn
= p Jp + n Jn ,
dx

(162)

dJn
(n p ) Jn = p J ,
dx

(163)

where J = Jn + Jp is the total electron and hole current, constant at steady-state. To determine the
breakdown condition, lets denote with Jn (xp0 ) the electron current density incident from the left-edge
of the depletion region (at x = xp0 ) and lets assume that the electron current exiting the high-eld
depletion region (at x = xn0 ) is a multiple Mn of Jn (xp0 ). Since most of the current at x = xn0 will
be carried by electrons, we can assume Jn (xn0 ) = Mn Jn (xp0 ) J . With this boundary condition the
solution of Eq. (163) can be written as:


 
 

 x
x
x
1
Jn (x) = J
+
dx p exp
dx (n p )
exp
dx (n p )
Mn
xp0
xp0
xp0
(164)
(Note: This comes from the fact that the general solution of the rst-order linear dierential equation

dy(x)
+ a(x)y(x) = b(x)
dx
is

y(x) = C eA(x) + eA(x)

dx b(x) eA(x) ,

where C is an integration constant determined by the boundary condition and A(x) = x dx a(x )).

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Evaluating Jn (x) at x = xp0 yields Jn (xp0 ) = J/Mn , which is our boundary condition. We
must also require Jn (xn0 ) = J . With some algebra this implies:

1
=
Mn

 x
n0
xp0


dx n exp

 x
xp0


dx (n p )

(165)

The avalanche breakdown voltage is dened as the voltage at which Mn . Thus, at breakdown the
integral above called ionization integral approaches unity:

 x
n0
xp0


dx n exp

 x
xp0


dx (n p )

= 1.

(166)

= 1.

(167)

For a hole-initiated avalanche we get a symmetrical result:

 x
n0
xp0


dx p exp

 x
n0
x

dx (p n )

Equations (166) and (167) are equivalent: The condition determining the onset of breakdown depends only
on what happens inside the depletion region, not on which type of carrier initiates the ionization process.
Note that for semiconductors for which n p (as in GaP, for example), the breakdown condition
becomes simply

xn0

xp0

dx = 1 ,

(168)

with obvious meaning: If the probability of ionizing over the depletion region reaches unity, avalanche will
occur.
Since we have dened the breakdown voltage VBD as the voltage at which the multiplication coecient
Mn calculated above diverges to innity, an empirical expression for Mn capturing this asymptotic behavior

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is the following:

1
,
(169)
1 (V /VBD )n
where n is a suitable exponent which usually varies from3 to 6, depending on the type of junction and
semiconductor. The breakdown voltage can be calculated from known doping prole, ionization rates, etc.
from the equations above. In the case of an abrupt junction we have:
Mn

VBD =

Fmax (xn0 + xp0 )

2

(170)

where the maximum eld in the depletion region is given by Eq. (131). For linearly graded junctions
(junctions with a doping prole varying linearly, rather than abruptly), the formula above must be corrected
by a factor 2/3.

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ECE344 Fall 2009

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2. Zener breakdown.
Another cause of breakdown is related to the quantum mechanical process of tunneling (see Lecture Notes,
Part 1, page 10). At a very large electric eld in a reverse-biased p-n junction, electrons in the valence
band may tunnel across the band gap of the semiconductor, thus creating an electron-hole pair. The process
may lead to breakdown either directly (so many pairs will be crated that the leakage current will grow) or
indirectly: The electrons and holes generated by the tunneling process will impact-ionize and an avalanche
process will begin. This breakdown mechanism is called Zener breakdown. It aects mostly heavily-doped
junctions in which the built-in voltage and the applied (reverse) bias fall over a narrow depletion region, thus
giving rise to large electric elds.
A relatively simple estimate of the strength of the process may be obtained by assuming that the electrons
have to tunnel through a triangular barrier of height EG and length EG /(eF ) (see the gure in the previous
page). Using a suitable approximation, the tunneling probability can be calculated and one nds that it is
proportional to:

PZener (F ) exp

3/2

4(2m)1/2 EG
3e
hF

(171)

where m is the electron eective mass in the gap (usually approximated by the smaller between the electron
and hole eective masses). More rigorous calculation show that the current is given by:

JZener

(2m)1/2 e3 F Va
1/2
42h
2 EG

PZener (F ) .

(172)

This expression is independent of temperature and it is valid only for semiconductors with a direct gap (such
as most of the III-V compound semiconductors). On the contrary, for semiconductors with indirect gap (such
as Si and Ge), the calculations must take into account the fact that crystal momentum must be supplied
(mainly by phonons) in order to allow a transition from the top of the valence band at the symmetry point
to the bottom of the conduction band at other locations in the BZ (at the symmetry points L in Ge, near
the symmetry points X for Si). The role played by phonons in the process renders Zener breakdown quite

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strongly temperature-dependent.

Time-transients.
We have so far limited our attention to the steady-state behavior of the device. We have seen that when we
move from the equilibrium situation (Va = 0) to forward or reverse bias (Va = 0) we must move charges out
(reverse bias) or in (forward bias) the depletion region. In practical applications it is important to know how
quickly the device can adjust to a new bias condition.
Unfortunately a detailed analysis of time-transient behavior is complicated: We would have to solve selfconsistently the DDEs (including their full time-dependence) and Poisson equations. However, a couple of
examples can give an idea of how a diode will switch.
Decay of stored charge.
Consider a forward-biased p-n junction with a curent I = jA owing through it. Using the charge control
model discussed before, we may view the current at steady state as replenishing the charge of minority carriers
recombining. In formulae, using current continuity and assuming a one-sided p+ -n junction so that the total
current is almost completely due to the hole current:

jp (x, t)
p(x, t)
p(x, t)
.
= e
+ e
x
t
p

(173)

Integrating both sides over x from xn0 to at time t, since the current jp vanishes innitely deep into the
n region, we get:
dQp (t)
Qp (t)
jp (xn0 , t) = j(t) =
,
(174)
+
dt
p
x
where Qp (t) = e 0 p(x, t) is the total hole charge per unit area stored in the n-type side of the junction.
At steady state we recover the usual result j = Qp /p , which have we obtained before. But lets now assume
that at t = 0 we disconnect the current source so that j = 0 for t > 0. The sudden removal of the current
means that the hole charge Qp (t) will decay in time, since there will be no inux of holes from the p+ region
to replenish those which recombine in the n region. Indeed, we can solve Eq. (174) with the initial condition

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Qp (t = 0) = jp and setting j = 0 in that equation:

dQp (t)
Qp (t)
,
=
dt
p

(175)

or:

Qp (t) = jp et/p ,
(176)
showing that indeed the positive charge due to holes stored in the n side of the junction decays with a time
constant p .
Knowing how the hole charge decays with time, we can calculate how the voltage across the junction changes
with time: At steady state (for t < 0) the junction was forward biased, so that V (t < 0) = Va . But at
much later times, after the hole charge will have disappeared, we must have the junction at equilibrium so
that V (t ) = 0. We can calculate this time dependence by assuming that the spatial dependence of
the hole concentration is exponential during the entire transient (condition which, as explained in Sec. 5.5.1
of the text, is not fully satised). Then we know that the voltage drop is correlated to the excess hole density
at xn0 via





eV (t)
pn (t) = pn0 exp
(177)
1 .
kB T
Assuming now, as we said above, that hole density is exponentially decaying at all times, we have:
p(x, t) = pn (t) e(xxn0)/Lp ,
so that:

Qp (t) = e


xn0

(178)

dx p(x, t) = pn (t) Lp .

(179)

Using Eq. (176) and (177) we have, nally:

kB T
V (t) =
ln
e

jp
t/p
e
+1
eLp pn0


.

(180)

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This shows that the voltage across the junction decays to zero at rst linearly but exponentially at large times
t.
Switching Diodes.
In most cases, a diode is supposed to switch from the conducting (forward-bias) to the non conducting (reverse
bias) state. The speed at which the switching can occur is limited by the time it takes to remove or add
charge to/from the depletion region. This depends on two parameters: the lifetime of the carriers, n and p ,
and on the capacitance of the junction.
The importance of these parameters is illustrated by considering a sudden forward-to-reverse bias transition.
Consider a diode in series with a resistor R. Assume initially the p-n junction in forward bias with current
If owing in the circuit. Since only a small voltage will drop across the junction under these conditions,
most of the voltage, V = RIf , will drop across the external resistor. Assume now that we switch suddenly
the polarity of the external bias. In order for the junction to go under reverse bias, a large amount of
charge has to be removed from the junction in order to form the large depletion region. This process and
the speed at which happens is controlled by the depletion capacitance which we shall discuss below: A
larger capacitance requires more charge in order to establish a given potential drop. But even before this
can happen, the excess minority carriers (holes in the n region and electrons in the p region) which existed
under forward bias must recombine away. The speed of this process is controlled by the carrier lifetime.
Thus, often impurities (Au, for example) are intentionally added to the junction in order to speed up the process.

Junction capacitance.
Capacitance is a measure of the charge stored per unit change of voltage. A larger capacitance means that more
charge must be moved in or out, so that for a xed current more time is needed to complete the process.
Thus, this translates into a longer delay in responding to the new bias condition.
In a p-n junction two major capacitances are at play: 1. The capacitance associated with the charge which
must be moved in or out of the depletion region. This is called the depletion capacitance. 2. The capacitance
present under forward bias due to charges spilling over into the quasi-neutral regions. This is called diusion
capacitance. Lets now consider these two components separately.

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 Depletion capacitance.
When the bias Va applied to the junction is varied, the width of the depletion region changes according to
Eqns. (140) and (141). The charge present in each depletion region due to the ionized dopants will be:

Qdepl = eAND xn0 = eANA xp0 ,

(181)

where A is the cross-sectional area of the junction. There will also be a component of charge due to the
motion of majority carriers. But this happens very quickly (in the time scale of picoseconds or less), so we can
ignore this delay. Thus, by denition of capacitance,



 dQdepl 
 = eAND
Cdepl = 
dVa 




 1/2
 dxn0 
e
N
1
N
s
A
D

 = A
,
 dV 
2 (NA + ND )
(Vbi VA )1/2
a

(182)

or, noticing that from Eqns. (140) and (141)


W = xp0 + xn0 =


2s (Vbi Va )(NA + ND ) 1/2
,
e
NA ND

(183)

we can rewrite Eq. (182) as:

s A
s A
=
(184)
,
xn0 + xp0
W
which is just the capacitance of a parallel-plate capacitor with a dielectric of permittivity s , with plates of
area A separated by a distance W = xn0 + xp0 .
Cdepl =

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 Diusion capacitance.
The concentration of excess carriers diusing in the quasi-neutral regions can be obtained from Eq. (148):



eVa /(kB T )

1 e(xxn0 )/Lp

pn (x) = pn (x) pn0 = pn0 e

(x > xn0 )

np (x) = np (x) np0 = np0 eeVa /(kB T ) 1 e(x+xp0 )/Ln

(x < xp0 ) .
(185)

The charge per unit area will be (considering only holes, a similar expression will hold for electrons):

Qdif f,p = e

xn0

eVa /(kB T )

pn (x) dx = eLp pn0 e

(186)

Under strong forward bias, eeVa /(kB T ) >> 1, so:

Cdif f,p

dQdif f,p
dVa

2
e2 Lp pn0 eVa /(k T )
e Lp
e
B
=

Jp (xn0 ) =
e
p Jp (xn0 ) , (187)
kB T
kB T Dp
kB T

where we have used Eq. (150) in the last step. Accounting now for the charge of the minority electrons
diusing into the p quasi-neutral region:

Cdif f

dQdif f,p
dVa

dQdif f,n
dVa

e
kB T

[p Jp (xn0 ) + n Jn (xp0 )] .

(188)

Note: This is the equation found in most textbooks. However, in a text by Karl Hess (and in a brief comment
on the lastest edition of the Streetman-Banerjees book) one nds instead:

Cdif f

e
[p Jp (xn0 ) + n Jn (xp0 )] ,
2kB T

(189)

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where the additional factor of 1/2 is explicitly commented and the claim is made that Eq. (188) is in error.
This factor can be justied in hand-waving fashion by noting that the charges Qdif f,p and Qdif f,n are like
the charges in the two opposite plates of a capacitor, so that the capacitance should be given by the change
w.r.t. the applied bias of the average of the electron and hole charges. A more sophisticated and rigorous
explanation is given by S. E. Laux and K. Hess, IEEE Trans. Electron. Device vol. 46, no. 2 (February 1999),
p. 396. Their argument is based on the observation that rigorously speaking the diusion charge extends
also inside the depletion region, so that the integration in Eq. (186) should extend from 0 to , not from
xn0 (and similarly for the expression for Qdif f,n ). Since as Va changes charges will leave the depletion
region, we will obtain a lower estimate for the charge, and so for the capacitance. In a way, this argument
is equivalent to our hand-waving argument since both reduce to accounting for the charges throughout the
entire junction, not just in the quasi-neutral regions.

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Other diodes: Heterojunctions,

Metal-Semiconductor junctions (Schottky contacts), MOS capacitors
p-n junctions are ubiquitous in semiconductor devices: We had to analyze their characteristics in some detail
because this understanding is required to analyze, in turn, the characteristics of many types of devices (bipolar
junction transistors BJTs in particular). However, other types of junctions play a major role in several types of
transistors: Heterojunctions (that is, the junction between two dierent semiconductors) make up heterojunction
bipolar transistors (HBTs), high electron-mobility transistors (HEMTs, also known as modulation-doped eld-eect
transistors, MODFETs), and injection lasers; Schottky contacts (that is, the junction between a semiconductor
and a metal) enter heavily in the operation of metal-semiconductor FETs (MESFETs), among other devices;
MOS - metal-oxide-semiconductor- capacitors are at the heart of what is arguably the most important type of
transistor in VLSI technology, the metal-oxide-semiconductor eld-eect transistor (MOSFET).
We shall now discuss in turn each of these junctions (or diodes, as they broadly fall into the category of
two-terminal devices). We shall not go into too much detail as far as heterojunction and Shottttky contacts are
concerned, but we shall analyze carefully MOS diodes (or capacitors), since the operation of MOSFETs requires
some basic understanding of the accumulation, depletion, and inversion of the surface of semiconductors in contact
with an insulating layer.
Heterojunctions.
Band-alignment.
As we have seen in the midterm exam 1, the workfunction of a solid is the energy required to excite
an electron from the bottom of the conduction band and bring it to the energy of the vacuum, so that
the electron becomes free from the attractive potential of the crystal. Therefore, if we consider two
semiconductors, simply labeled 1 and 2 in the gure below, each isolated from the other, they will have a
band alignment as shown in the gure below (left), since the energy level of free electrons (the vacuum level)
is the same for both materials. The edges of the conduction and valence bands will exhibit discontinuities
EC and EV respectively, as indicated in the gure. Figure on page 29 of the Notes, Part 1, shown
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how the valence and conduction of several semiconductors (characterized by their lattice constants) bands align.

Evac
e2
e1

EC2
EF2

EC

EC1
EF1
EV1

EC1
EF1
EV1

EC

EV

EC2
EF2

EV

EV2
EV2

As we bring the two semiconductors in electrical contact, we know that their Fermi levels must line-up under
equilibrium conditions. On the other hand, the discontinuities EC and EV (which depend on the presence
of microscopic dipoles at the interface) must be present in order to account for the dierence of the bandgaps.
In order to accommodate these two requirements, upon bringing the materials in contact, electrons ow from
one material to the other (from 2 to 1 in the gure) and holes in the opposite direction (1 to 2 in the gure),
much as it happens in a conventional junction (homojunction, same junction, from Greek). As electrons
deplete region 2, positive charge is formed, thus forming a depletion layer with the potential energy showing
positive second-derivative (upwards curvature). Simililarly, hole leave behind negative charge, resulting in the
diagram shown above (right). This is the equilibrium, zero-bias band-diagram of a heterojunction (that is, a
junction made up of two dierent materials).

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 Thermionic emission.
In the gure below we use the example of GaAs and the alloy Alx Ga1x As (where x, known as the mole
fraction, is the molar fraction of Al ions to Ga ions). This type of heterojunction can be obtained by starting
from a GaAs substrate and growing successive layers of AlxGa1x As via Molecular Beam Epitaxy, in which
beams of Ga, Al, and As ions (beams whose intensities are in carefully monitored proportions) are shot on
the GaAs surface. If the correct ratio of beam intensties is used, the process will result in the deposition of
the alloy Al0.3 Ga0.7 As on GaAs. As seen from the gure on page 29, at this mole fraction Al0.3 Ga0.7 As has
the same lattice constant of GaAs, so that we will end up with a crystallographically perfect heterojunction. A
slight mismatch of lattice constants can be tolerated for thin lms. The top layer will be under compressive or
tensile biaxial strain (depending on whether its lattic constant is larger or smaller that that of the substrate).
If the lm thickness is small enough, the energetic cost of mainting the strain will be smaller than that
of creating crystal defects (broken arrays of ions, known as stacking faults, crystal planes misaligned with
one-another, known as dislocations etc.). But is the lm is too thick, these kind of defects will be eventually
energetically favorable and the crystal structure of the top layer will shown a non-ideal (and usually unwanted)
crystalline structure.
Coming back to our example, GaAs has a smaller band gap ( 1.51 eV) than AlxGa1x As ( 1.72 eV for x
= 0.3, for example). Experimentally it is found that most of the discontinuity of the energy gap falls in the
conduction band. Therefore, as soon as the two materials are brought together, the conduction bands will
line-up as shown in the left frame of the gure.
The resulting structure behaves like a diode, but in order to evaluate the magnitude of the current owing
across the heterointerface, we must modify the analysis we have done in the context of p-n homojunctions,
since the presence of the band discontinuity presents some new physical aspects.

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In principle, the qualitative aspects of the junction are similar. We saw that one possible way to look at
the electron ux from the n side of a p-n junction to the p side consisted in looking at all electrons which
have sucient kinetic energy to overcome the barrier of height eVbi eVa . Their number is exactly
np0 [exp(eVa /(kB T ) 1], the very factor which controls the electron diode current, since it xes the
gradient of the electron concentration, and so the diusion current. At zero bias, the drift term opposes exactly
this ow, thus yielding zero current. But under forward bias, exponentially more electrons can overcome the
barrier, the drift term remaining essentially unchanged, and a large current would result. The same happens in
a heterojunction. There are two main dierences. First, since the band discontinuitues EC and EV are
in general very dierent, unlike what happens in homojunctions, the type of carriers facing the smaller barrier
will usually dominate. Lets assume that in our example EC < EV (unlike what shown in the gure), so
that we can deal only with electrons. The second dierence lies in the fact that the barrier is now caused not
by the built-in potential, but by the conduction-band discontinuity EC . Only electrons which are thermally
excited to energies above the barrier can make it across. This is called thermionic current, in analogy with
the electron current emitted by a heated lament (as the W lament in an incandescent light bulb).
The derivation of an accurate formula describing the current through the heterojunction is somewhat

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complicated. An approximate expression is given by:

jhet (Va ) = A B T

|Ec |)/(kB T )
e

eVa /(nkB T )

(190)

2
where A = em kB
/(22 h
3 ) is the so-called Richardson constant, B a slowly-varying function of the bias,
depending on the nature of the junction, and n an ideality index varying between 1 and 2. Note the similarity
of this equation with the diode equation, Eq. (150).

Schottky contacts. Schottky contacts are ideal junctions between semiconductors and metals. In theiry and
in their ideal songuration, they should be rectifying contacts. In practice, whenever we need to make good
contact to a semiconductor (meaning: we need a perfect ohmic contact, not rectifying), we resort to metals,
typically Al. The nature of ohmic contacts and why systems which should behave like rectifying contacts in
practice end up showing ohmic behavior is still relatively poorly understood. So, we start by discussing the ideal

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rectifying Schottky contacts. But at some point we shall stop and discuss briey how one can obtain ohmic
behavior from these structures.
Metal-semiconductor junction.
When we bring a metal and a semiconductor together, as shown in the gure in the next page, we have a
situation not too dissimilar from what we have seen regarding heterojunctions: If the semicondutor (assumed
to be n-type) Fermi level is larger than Fermi level in the metal (as shown in the gure), electrons will ow
from the semiconductor untill a new equilibrium will be reached. This will result in the creation of a depletion
region in the semiconductor side of the contact. Similarly to what we have sen in the case of heterojunctions,
there will be an energy barrier of height eB between the bottom of the CB of the semiconductor and the
metal Fermi level. Denoting by eM the metal workfunction (that is, the energy required to excite an electron
at the metal Fermi level to the level of the vacuum) and by e the electron anity of the semiconductor, the
Schottky barrier height will be (looking at the gure):

eBn = e (M ) ,

(191)

where the subscript n reminds us that we have considered an n-type semiconductor.

semiconductor, instead, we would have obtained

For a p-type

eBp = EG e (M ) .

(192)

The thickness of the depletion region can be obtained as we did before for p-n-junctions and we obtain


W =


2s (eVbi Va ) 1/2
,
eND

(193)

where the built-in potential Vbi is (see the gure) eB (Ec EF ).

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METAL

SEMICONDUCTOR

eB

Vbi = e(BEC+EF)
EC
EF

EV
Non-ideal junctions.
This is what we expect in an ideal case. In practice, it often happens that the Fermi level of the semiconductor
is pinned at some particular energy in the gap due to the presence of electron traps at the interface (interface
states). Years ago J. Bardeen had suggested that electronic states associated to unterminated bonds present
at the semiconductor interface may be an intrinsic cause of this pinning. Now it seems that things are more
complicated: For example, bare surfaces may reconstruct and, when exposed to metals, may deconstruct in
complicated ways, leading to amorphization, interdiusion and clustering in the interfacial region. It is fair to
say that we do not know exactly what pins the Fermi level, so that in many cases the Schottky barrier height
should be regarded as an experimentally measured quantity.
Thermionic and tunneling current.
The current owing through the Schottky diode is due two major processes: The thermionic ow of electrons

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over the barrier, and quantum-mechanical tunneling of electrons from the metal into the semiconductor. The
thermionic component can be calculated in a way very similar to the one described dealing with heterojunctions.
The net result is:


2 eB /(kB T )
eVa /(kB T )
e
j = A T e
1 .
(194)
Note, once more, the similarity with the Shockley equation, Eq. (150), for the current in p-n-junctions.

The second component of the current we must consider is of quantum-mechanical origin. It is the tunneling
current illustrated in the gure above.
In the example illustrated in the gure, electrons in the metal can tunnel across the Schottky barrier and enter
the semiconductor. Similarly, electrons can tunnel from the semiconductor into the metal.
Such a current can be calculated using the WKB approximation we have seen when dealing with Zener
breakdown. We can approximate the shape of the potential barrier by assuming a constant eld in the

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depletion layer, so that we must deal with a simple triangular barrier of the type:

(z) = B Fz z ,

(195)

where Fz may be chosen as the interfacial eld, 2 B /W , or some suitable average of the eld over
the depletion region. The quantity B is the total voltage drop in the semiconductor (see the gure),
B = Vbi Va = B Va EC + EF,S . In this case we get:


PM S = exp

4(2mS )1/2
3e
hFz


(e B E)3/2

(196)

and so the tunneling current will be proportional to this expression integrated over the electron energy
distribution M (E)fM (E) in the metal. Given the complexity of these calculation, one may wonder how
ohmic contacts could ever be realized. One possible explanation consists in assuming that height of the
Schottky barrier, eB , may be zero. This may happen in a few cases. But more likely is the scenario in
which heavy amorphization of the interface may result in a very heavily doped almost metallic thin layer
of semiconductor. The very high doping will result in such a thin depletion layer, that tunneling across this
barrier may be a dominant process, almost killing the resistance of the contact. This can be seen easily from
Eq. (196), noticing that the eld Fz is inversely proportional to the width of the depletion layer, W .

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 MOS capacitors.
The Metal-Oxide-Semiconductor (MOS) or Metal-Insulator-Semiconductor (MIS) diode is arguably the
most used and useful device in VLSI technlogy. Its ideal structure is shown in the gures below.

METAL

eM

EF,M

INSULATOR

eB

eVFB < 0

METAL

SEMICONDUCTOR

INSULATOR

SEMICONDUCTOR

eB

FLAT BANDS

EC
Ei
EF,S
EV

EC
Ei
EF,S
EV

EF,M

ZERO BIAS

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METAL

INSULATOR

SEMICONDUCTOR

METAL

INSULATOR

SEMICONDUCTOR

EC
Ei
EF,S
EV

EF,M

eVG > 0
eVG < 0

EC
Ei
EF,S
EV

EF,M

ACCUMULATION

INVERSION

Starting from a semiconducting substrate (assumed to be p-type in the gures), an insulator is grown or
deposited on the substrate. Typically, the natural oxide of Si, SiO2 , is thermally grown by heating the Si wafer
to temperatures in the range 850-1000oC in oxygen-rich ambient. The relative simplicity of this process (which,
however, must be extremely clean) and the unsurpassed electronic properties of SiO2 are probably the reasons
why Si has been the dominant material in microelectronics. After the growth or deposition of the insulator a
metal (or highly-doped polycrystalline Si) is deposited over it. In the gures a metal is considered.
At at band the alignement of the bands is illustrated in the rst gure. In the ideal case, charge would ow
across the insulator, so that the Fermi levels in the metal, EF,M , and in the semiconductor, EF,S , would
line-up and the dierence, M S , between the metal and the semiconductor work-functions would vanish:

M S = M

EG
+
+ B
2e


= 0

for p type semiconductor ,

ECE344 Fall 2009

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134

and

M S = M

EG
+
B
2e


for n type semiconductor .

= 0

(198)

In practice, the time required for the Fermi level to line-up is extremely long and this ideal situation is never
achieved. The gure shows that the application of a small bias, the at-band voltage VF B , is required to
line-up the Fermi levels. Its value will be given by the nonvanishing M S of Eq. (197) or (198) above.
The application of a negative bias, VG , to the metal (usually called the gate) drives the MOS diode into
accumulation: As seen in the gure, the bias causes an accumulation of holes at the Si-SiO2 interface. The
application of a positive gate bias, instead, results in the inversion of the semiconductor surface, electrons now
piling up at the interface. Lets now consider these processes in some detail.
Interface space-charge region.

SiO2

Semiconductor
EC

e
es

eB

Ei
EF

EV

The gure above shows in more detail the band-diagram near the semiconductor-SiO2 interface. Let z be the
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coordinate along the normal to the interace, z = 0 be the location of the interftace, and lets dene by (z)
the potential, taken as zero in the bulk and measured from the intrinsic Fermi level Ei . Then, assuming the
non-degenerate limit, the electron and hole concentrations will be:


e(z)
np (z) = np0 exp
(199)
= np0 exp() ,
kB T

pp (z) = pp0 exp() ,

(200)

where is positive downward (as in the gure), = e/(kB T ), and np0 and pp0 are the equilibrium
electron and hole concentrations in the bulk.
Let s be the surface potential so that

ns = np0 exp(s )

, ps = pp0 exp(s )

(201)

are the surface concentrations of the carriers.

We can deal with the exact Poisson equation as follows, extracting some information before embracing the
usual depletion approximation. We have:

2
e
+

[ND
+ p(z) NA
n(z)] ,
2
z
s

(202)

where s is the (static) dielectric constant of the semiconductor. From Eqns. (199) and (200) we have:

pp np = pp0 e np0 e ,

(203)

so that, since by charge neutrality in the bulk ND

NA
= np0 pp0 , we have

2
e

[p
(e

1)

n
(e
1)] .
p0
p0
z 2
s

(204)

ECE344 Fall 2009

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Lets now multiply Eq. (204) by /z and integrate Eq. (204) from an arbitray location z towards the
bulk (z ). The left-hand-side becomes:





 2


1
1
2
(z) 2

dz =
,
dz =
z 2 z
2 z
z z
2
z
z

(205)

having used the fact that the eld vanishes as z . For the right-hand-side we get:

 0
e

[pp0 (e
1) np0 (e 1)]
[pp0 (e
1) np0 (e
1)] d =
dz =
s z
z
s

e
[pp0 (e + 1) np0 (e 1)].
s
Therefore we have the following relationship between eld and potential at any location z :



 
2k
T
p
n
p0
p0
B
(e + 1) +
F2 =
(e 1) .
s
pp0
=

(206)

(207)

Introducing the Debye length, LD = [s kB T /(e2 pp0 )]1/2 (the dielectric screening length in the p-type
non-degenerate bulk Si), and denoting as G(, np0 /pp0 )2 the term in square brackets in Eq. (207), we
have:


np0

21/2 kB T
,
F =
G ,
(208)
=
z
eLD
pp0
the plus (minus) sign valid for > 0 ( < 0).
The charge at the interface can now be expressed using Gauss law and the value of the eld at the interface
(obtained by setting = s in Eq. (208)):


np0
21/2s kB T
.
Qs = s Fs =
G s ,
(209)
eLD
pp0

ECE344 Fall 2009

137

This represents the total charge per unit area, shown in the gure below. For negative s the charge is
positive (holes), corresponding to accumulation. At at band the total charge is obviously zero. In depletion
1/2

and weak inversion the term in the function G dominates, so that he charge grows as s . Finally,
in strong inversion the charge is negative, the term (np0 /pp0 )es being the dominant one. By denition,
strong inversion begins at s = 2B , the value of the surface potential at which the electron concentration
at the interface equals the hole concentration in the bulk.

1015
ptype Si 300K
NA = 4x1015 cm3

Qs (cm2)

1014

1013

1012

~ exp(s/2)
strong inversion

~ exp(s/2)
accumulation
flat
band
depletion

1011

10

~ s1/2
B

10

0.4

weak
inversion

0.0

EC

0.4
s (Volt)

0.8

ECE344 Fall 2009

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In order to obtain separately the electron and hole charges, n and p, we must integrate p(z) and n(z)
from the surface to the bulk:

p = pp0
and

n = np0


0

(e


0

(e

1) dz =

1) dz =

epp0 LD
21/2 kB T
epp0 LD
21/2 kB T

 0

e 1
d ,
s G(, np0 /pp0 )

(210)

 0

e 1
d .
G(,
n
/p
)
s
p0 p0

(211)

The dierential capacitance of the semiconductor depletion layer is given by:

1 es + (np0 /pp0 )(es 1)

Qs
s
CD =
=
.
s
G(s , np0 /pp0 )
21/2 LD
At at-band condition, s = 0, so:

CD,F B =

s
.
LD

(212)

(213)

Ideal capacitance-voltage characteristics.

It is very important to understand the capacitance-voltage characteristics of an MOS diode (or capacitor),
in view of their relevance to the operation of an MOS eld-eect transistor. Lets recall that we are now
interested in the dierential capacitance. That is, we apply a dc (or slowly-varying) gate bias to the diode,
but, in addition, we apply a small (of the order of kB T /e or less) ac bias at a given frequency.
If we apply a gate bias VG to the gate (while keeping the semiconductor substrate grounded), part of the
voltage, s , drops in the semiconductor and part, Vox , in the insulator. The latter will be given obviously by:

Vox = Fox tox =

Qs tox
,
ox

(214)

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having used the fact that s Fs = ox Fox , and having denoted with tox the thickness of the insulator. Thus,
the oxide capacitance will be
dQs
ox
Cox =
=
.
(215)
dVox
tox
But the total capacitance will also depend on the charge induced by the voltage drop in the semiconductor,
Eq. (212). Therefore the total capacitance will be the series-capacitance of the insulator, Cox and of the
depletion region, CD :
CoxCD
Ctot =
.
(216)
Cox + CD
For a given insulator thickness, the oxide capacitance is thus the maximum capacitance.

GATE CAPACITANCE

Cox

Cox

CFB

low
frequency

highfrequency
GATE VOLTAGE
Looking at the gure above, in accumulation (VG < 0) holes pile-up very close to the semiconductorECE344 Fall 2009

140

insulator interface. As the gate bias is reduced, the depletion capacitance begins to matter, depressing the
total capacitance. To estimate its value, in the depletion approximation we can write the potential in the
semiconductor as:



z 2
(z) s 1
,
(217)
W
where the depletion width W can be obtained in the usual way (see the rst of the Eqns. (139) above):

W


2s s 1/2
.
eNA

(218)

Thus, the depletion capacitance will be the result of charges responding to the ac-bias at the edge of the
depletion region, so that
s
CD =
(219)
,
W
and
ox
Ctot =
(220)
.
tox + (ox /s )W
At at band we should replace W with LD , while the onset of strong inversion (also called the turn-on
voltage or, more commonly, the threshold voltage, as this marks the onset of strong conduction in MOS
eld-eect transistors), we have

W = Wmax




2s 2B 1/2
4s kB T ln(NA /ni ) 1/2
=
.
eNA
eNA

(221)

When the surface potential reaches the strong-inversion value, s = 2B , the electron concentration at the
insulator-semiconductor interface is so large (provided enough time is given to the minority carriers so that
an inversion layer is indeed formed, as we shall see below) that it will screen the eld and it will prevent any
further widening of the depletion region. Indeed, as we can see in the plot Qs vs. s at page 138, a small
increment of surface potential will result in a huge increase of the electron charge. Thus, one can assume

ECE344 Fall 2009

141

that in strong inversion most of the additional VG will drop in the insulator and no signicant increase of
s will occur. Therefore, Eq. (221) gives the maximum width of the depletion region. The only exception
to this is given by the application of a very quickly-varying dc bias: If the gate bias VG is increased very
quickly to positive values, there will be little or no time for generation/recombination processes in the bulk
to provide/absorb enough minority carriers (electrons) to feed the inversion layer. In this case will exceed
2B , W will grow beyond Wmax and the capacitance will drop below its minimum value Cmin given below
by E. (222).
As the gate bias becomes even more positive, we must distinguish two dierent situations. If the applied bias
is varied slowly and the applied ac bias is of low frequency, generation and recombination processes in the
bulk may be able to follow the ac signal. Thus, electrons in the inversion layer will respond, the response of
the depletion layer will be screened by the ac-varying inversion charge and the dierential capacitance will rise
back to the value given by Cox. If, on the contrary, the frequency of the ac signal is large, than the inversion
charge will not be able to follow the signal. The depletion capacitance will be clamped at the minimum value
s /Wmax , and so the total capacitance will remain at the minimum value

Cmin =

ox
,
tox + (ox /s )Wmax

(222)

independent of gate bias.

Experimentally the transition between the low-frequency and the high-frequency behavior happens around
1-50 Hz. However, MOS diodes built on substrates of excellent quality (small density of SRH centers) may
exhibit the low-frequency behavior only when there is no applied ac signal and the dc gate bias is varied
suciently slowly (even a fast varying dc VG say, a C-V sweep in a few seconds, may push the diode into
its high-frequency response).
Deviations from ideality: Oxide charges and interface traps.
So far we have considered an ideal MOS structure in which both the insulator and the interfaces are free from
defects and impurities. This was not the case early on when MOS devices were rst fabricated. Even today,
after decades of research and development has enabled the realization of almost-ideal structures, during the
operation of a device defects may be created by energetic carriers hitting the interface or being injected into

ECE344 Fall 2009

142

the insulator. These defects may be broadly classied into two categories: Fixed charges in the oxide and
electrically-active interface states. (The word xed labelling the charges in the oxide refers to the fact that
their charge-state or electronic population does not depend on the applied bias, while their location as
in the case of mobile Na or K ions may depend on the bias and thermal history of the device.)
Insulator charges are typicaly either impurities (historically mobile Na and K ions were the subject of many
eorts), or defects, such as dangling bonds, local stress in the SiO2 ionic network, oxygen vacancies induced
by growth, processing such as irradiation. Such charges have the main eect of shifting the threshold voltage

VT = Vox,si + 2B =

Qs (2B )
+ 2B ,
Cox

(223)

or the at-band voltage. In order to derive a general expression for the at-band voltage shift due to
an arbitrary distribution of charges (z) inside the insulator (where z now denotes the distance from the
gate-insulator interface) lets consider rst an ideal (free of charge) MOS capacitor originally at at-band
condition and now add a sheet of charge (charge per unit area) at z . This charge will induce polarization
(image) charges both in the metal and in the semiconductor. The latter charge will bend the bands and so
modify the gate bias we must apply to recover at-band. Lets now apply an additional bias to the metal, so
to bring the semiconductor at at band. In this situation there will be no eld in the metal (by denition),
no eld in the semiconductor (as we are at at band). There will only be a constant electric eld /ox for
tox < z < 0. Thus, the metal potential will have moved by an amount (tox + z)/ox with respect to
the initial situation. This will be the shift of the at-band voltage caused by the sheet of charge. Therefore,
for a distribution (z) of charges inside the insulator, the at-band shift will be given by:

VF B =

 tox
0

(z)
1
(tox + z)
dz =
ox
Cox

 tox

0

1+

z
tox


(z) dz .

(224)

Note that charges close to the gate-insulator interface, z = tox , have no eect on VF B (the polarization
charges at the metal surface screen completely the oxide charges), while charges near the semiconductorinsulator interface have maximum eect.

ECE344 Fall 2009

143

Interface traps (or states) are defects typically Si dangling bonds whose occupation depends on the
position of the Fermi level at the insulator-semiconductor interface. They have a twofold eect: Depending
on their occupation, they shift the at-band voltage, as in Eq. (224). Since for these states z = tox , their
electrostatic eect is strong. More importantly, becaue of the intrinsic delay in responding to an ac signal (the
time constants for emission and capture are those of SRH centers), they store charge, thus contributing to the
total capacitance of the MOS diode. Their capacitance, Cit , is in series with Cox and in parallel to CD , so
that


 1
1
1
Cox(CD + Cit )
Ctot =
+
=
.
(225)
Cox
CD + Cit
Cox + CD + Cit
Several methods have been devised to measure the density, Dit , of the interface traps. They all rely on a
measurement of their capacitance. Ideally, if one knew very accurately the theoretical C-V characteristics of
the diode, a comparison of the theoretically computed and experimentally measured characteristics will yield
the desired capacitance, Cit, and so the density Dit , since the density of the interface-trap charge at energy
E in the gap (the position of the Fermi level in the gap at a surface potential s ) will be Cit (s ): Having
obtained Cit from the total capacitance via Eq. (225), at a given gate bias we have:

Cit =

dQit
dNit
= e
= e Dit ,
ds
dE

(226)

where Nit is the total number of traps up to energy E in the gap and Dit is the trap density per unit
area and energy in the gap. Recalling that VG = Vox + s , we have dVG = ds + dVox . Since
dQ = Cox dVox = Ctot dVG , we have dVG = ds + (Ctot/Cox) dVG , and so we can obtain
ds /dVG from the relation
ds
Ctot
= 1
.
(227)
dVG
Cox
Thus, from Eqns. (220), (226), and (227) we can extract dQit /ds :



dQit
Ctot ds 1
C
Dit (E) =
=
d .
(228)
ds
e
dVG
e
ECE344 Fall 2009

144

This is the density of interface traps per unit energy in the gap at the energy E which, as we said above,
indicates the position of the Fermi level inside the semiconductor gap at the interface.
In practice, detailed theoretical curves C V are hard to compute. Therefore, typically one replaces the
theoretical curve with a C-V curve obtained under conditions such that the interface traps do not respond.
Since the characteristic time of the response of the trap is of the order of


1
e(B s )
=
exp
(229)
,
vth ni
kB T
(for a p-type substrate), either a low-temperature measurement (so that at a given ac frequency the response
time becomes so long that the trap occupation does not vary) or a high-frequency measurement will provide
almost ideal C-V characteristics. A comparison between high-frequency and low-frequency measurements (or
high-T and low-T measurements) will provide Cit .
There are two major corrections we should make to the analysis followed so far: We have used the non-degenerate
limit (using Maxwell-Boltzmann instead of Fermi-Dirac statistics in relating carrier density to (quasi)Fermi levels)
and we have ignored completely all quantum mechanical properties of the electrons.
The rst correction important at large densities such as strong inversion and accumulation complicates the
mathematical analysis so that it becomes impossible to derive analytically even the relations eld/potential or
surface-eld/total-charge given by Eqns. (208) and (209). Only numerical work can give us reliable answers.
Yet, the analysis followed so far is qualitatively correct and gives a quantitatively correct picture in the important
region covering weak-accumulation to weak inversion.
Quantum mechanical properties are usualy important in transport. So far, we have limited our attention to
electrostatics. Yet, even the electrostatic poperties can be aected by quantum mechanics when the charge
carriers are conned within regions of size comparable to (or, a fortiori, smaller than) the thermal wavelength
of the electrons. Accumulation and inversion layers are such reasons and they do present this problem. Indeed,
the wavelength of an electron at equilibrium (called its thermal wavelength) is given by the de Broglie relation
th = h/pth = 2/kth , where pth = h
kth is the average momentum of electrons at thermal equilibrium.
2
2 kth
/(2m ), so that,
For the average carrier energy at thermal equilibrium we have Eth = (3/2)kB T = h
ECE344 Fall 2009

145

at 300K,

th =

2
h
(3mkB T )1/2

6.2


m0 1/2
nm
m

(230)

Consider the Si-SiO2 interface in inversion/strong-inversion. The electron density ns (the sheet density per
unit area, see the gure at page 138) is of the order of 1011-to-1013 cm2 , corresponding to an interfacial
eld Fs = ens /s of the order of 104-to-106 V/cm. Thus, an electron of thermal energy ((3/2)kB T 40
meV) will be squeezed by the eld against the interface over a conning distance z 3kB T /(2Fs ), very
much like a particle in a box considered at the beginning of the course. This distance is of the order of 40-to-0.4
nm, comparable or even smaller than the electron thermal wavelength. We are not allowed to ignore the
wave-like nature of electrons when we conne them so tightly: We expect that discrete energy levels will emerge
from the connement. If we conne a particle in a region of width z , by Heisenbergs principle the particle
momentum will suer an uncertainty k 1/z , so that the conned particle will have a minimum energy
E0 h
2 k2 /(2m) h
2 /(2z 2m ), called the zero-point energy. In strong inversion this energy may
be comparable to (or even larger than) the thermal energy, and quantum eects due to the connement should
not be ignored. The major changes to the classical picture that these quantum-mechanical correction provides
are:
1. The electron charge in inversion layeres is removed somewhat (typically by a length t of the order of 1.0
nm) from the interface. This causes a reduction of the gate capacitance in accumulation, Cox, since the
eective thinckness of the oxide is increased by the amount ox /Si t.
2. The threshold voltage shifts to higher values, since we must move the Fermi level in the inversion layer to an
energy higher by an amount E0 (the zero-point energy mentioned above.
3. The properties of electron transport (and so, in particular, the electron mobility) are modied, since both the
shape of the wavefunctions and the density of states are modied.
Detailed calculations of electron transport in these subbands (as they are called) is beyond the scope of this
course. We simply show in the gure below a typical example of energy levels, wavefunctions, and charge
distribution in a Si inversion layer.

ECE344 Fall 2009

146

1.5

electron density (1020 cm3)

0.60
0.50
0.40

potential (V)

potential (V)

1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1

0.30
0.20
0.10
0.00
0.10
0.20

20

40
z (nm)

60

80

1.2
quantum
classical

0.9
0.6
0.3
0.0

10

15

z (nm)

3
4
z (nm)

A nal phenomenon we must mention is the possibility of quantum-mechanical tunneling of electrons in the
inversion layer across the gate insulator. This becomes important for thin oxides and/or at very large elds. The
rst situation (illustrated by the left frame of the gure below) is called direct tunneling, the second situation
Fowler-Nordheim tunneling. Using the usual WKB approximation, the tunneling probabilities in the two cases
are: For direct tunneling:


Pd exp

4(2emox)
3
hFox

1/2


3/2

[1 (1 tox Fox / B )]3/2


exp

2(2moxe B )1/2

tox

= e2 tox ,

(231)

where Fox is the eld in the insulator, mox the eective mass in the gap of the insulator, B = B E0 is
the eective barrier height, reduced by the energy E0 of the bottom subband in the inversion layer, tox is the
insulator thickness, the last step has been made assuming a thin insulator (tox << B /Fox ), and we have
ECE344 Fall 2009

147

dened an average decay constant = (2moxe B )1/2 /

h. For FN-tunneling, instead:


PF N exp

4(2emox)1/2 3/2

B
3
hFox


(4/3) zt
,

== e

(232)

where zt = B /Fox is the tunneling distance across the triangular barrier. As device scaling progresses, thinner
and thinner insulators are used, together with a reduced applied bias. When insulators were 10 nm thick and
the applied bias was of the order of 5 V, FN tunneling was the only concern. This possibly caused only minor
leakage when the devices were turned-on very strongly, so only during the on state. Today, instead, insulators
are as thin as 2 nm (or even less). Even if the applied bias has been reduced to less than 1 V, from Eq. (231) it
is clear that direct tunneling is becoming increasingly important. The major cause of concern is its independence
of bias: Electrons can tunnel across the trapezoidal (or almost rectangular barrier) under any bias condition.
This leakage in the o-state causes unwanted power dissipation and it constitutes one of the problems (if not
the problem) we must face attempting to scale devices to even smaller dimensions.

ECE344 Fall 2009

148

3.5

3.0

3.0

2.5

2.5

2.0

2.0

potential (V)

potential (V)

3.5

eB E0

1.5
1.0

1.0

0.5

0.5

0.0

0.0

0.5
1.0
20

0.5

direct tunneling
0

20

40
z (nm)

eB E0

1.5

60

80

1.0
80

FowlerNordheim tunneling
60

40

20

0
20
z (nm)

40

ECE344 Fall 2009

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80

149