CURRICULUM VITAE

SATHEESH SADANAND
Flat No. 605, Shriram Shankari,
Ittamadu,
Banashankari III Stage, Bangalore 560 085
India.
Ph - +919845172062 (Mob), +91-80-26728492.
Email satheesh_s73@yahoo.com
Objective:

To become a world class professional in Digital systems design

Professional
Experience:

2002 October Till date

Ittiam Systems Private Limited (http://www.ittiam.com/),
Bangalore, India.
Current Designation Lead Engineer
Experience in DSP based multimedia products like Portable Media
Players, Wireless Projectors and MPEG-4 Players
1996 March 2002 September
Centre for Development of Telematics (C-DOT),
(http://www.cdot.com/)
(Telecom Technology Development Centre of Govt. of India)
Bangalore, India.
Designation Co-ordinating Engineer.
Experience in telecom products like Value Engineered Base Module
(VEBM) for C-DOTs Main Automatic Exchange and C-DOTs GSM
Transcoder and Rate Adaptation Unit (TRAU).

Skill Set:

My experience covers different aspects such as:

Generation of Technical Proposal for prospective customers
Study of ITU-T, ETSI and customer specifications
Generation of system specifications and architecture
Hardware design partitioning
Circuit Design and Review
PCB Placement and Routing
EPLD and FPGA logic design
Implementation of GSM-FR Speech Encoder and Decoder
Integration Testing and Validation
Interaction with customers based in USA, Europe and the Far
East.
Recruitment and Training of Engineering graduates
Programming in MATLAB, C
Altera Max + Plus II and Quartus Tool for VHDL coding and
simulation

Testing Tools:
Academic
Record:

Awards and
Distinctions:

Publications:

Assembly language programming of TMS32054x DSPs and

MC68302.
Mentor Graphics & Cadence CAD Tools for schematic capture,
placement and routing
Code Composer Studio and DSP/BIOS
Emulators for TMS320 DSPs and MC68302.
Logic Analyzer, PCM Analyzer
M.Sc (Engg), 1998-2001, from Dept. of Electrical Communication
Engineering, Indian Institute of Science, Bangalore.
(http://www.iisc.ernet.in/)
CGPA 6.5 out of 8
Title of Thesis: Adaptive Sub-band coding of audio signals using
spectral and temporal masking properties.
B. Tech, 1991-1995 in Electronics and Communication Engineering
from T. K. M. College of Engineering, Kollam. (University of Kerala)
Percentage 87%. III Rank holder in the University.
i.
C-DOT Divisional Award for best performance in 2000-01 for
contributions to DSP Software development of GSM-FR and
support of VEBM.
ii.
C-DOT Divisional Award for best performance in 1999-2000
for contributions in TRAU product design.
iii.
Winner of best student paper award from IEEE Kerala Section,
1995.
Satheesh. S and T. V. Sreenivas, A switched DPCM/Adaptive
Subband coder for pre-echo reduction, Seventh International
Conference on Speech Communication and Technology (Eurospeech)
at Denmark, September 2001.
Satheesh S, Portable Media Player based on TMS320DM320, Texas
Instruments Developers Conference, February 2005

Personal
Information:

References:

Date of Birth: 29 December 1973.

Sex: Male
Nationality: Indian
Fathers Name: R. K. Sadanand
Mothers Name: Sunanda Sadanand
Can be provided on request

Key Project Details

Portable Media Player and Recorder
This is a near production ready reference design of a battery operated Portable Media
Player based on TIs TMS320DM320 (ARM9 + DSP Processor).
Responsibility
Design of system specifications
Circuit Design
Review of PCB design
Review of Enclosure Design
Duration
August 2004 to Present
Details
http://www.ittiam.com/pages/products/pmpr.htm
Digital Video Recorder
This system is based on TIs TMS320DMxxx (ARM7 + DSP Processor) platform. The
system is used to record and playback video captured by a car surveillance system.
Responsibility
Design of system specifications
Circuit Design
Review of PCB design
Duration
March 2004 to August 2004
Wireless Projector
This system is based on TIs TMS320DMxxx (ARM7 + DSP Processor) platform. The
content of a PC screen (XVGA) is captured, encoded and transmitted over Wireless LAN.
The DSP in the receive unit connects to the WLAN via its CompactFlash interface. The
DSP decodes and displays the image on to a projector.
Responsibility
Design of system architecture and Video Output Card
Design of architecture for FPGA on Video Output Card (Patent Pending)
Testing and Validation.
Led a team of 3 Engineers
Duration
May 2003 to Feb 2004
MPEG-4 Video Demonstration Platform
This system is designed to demonstrate the MPEG-4 Video decode capabilities of a
customer DSP core.
Responsibility
Design of system architecture along with customer
Design of LCD driver board for driving a 3.5 LCD.
Design of architecture for video output logic implemented in Altera FPGA.

 Review of logic design

Testing and Validation
Led a team of 3 Engineers
Duration
May 2003 September 2003
Digital Media Album
This system is based on TIs TMS320DMxxx (ARM7 + DSP Processor) platform. The
system performs audio/video capture, encode, decode, playback and storage. The
interfaces include CompactFlash, Hard Disk Drive, LCD, Composite Video Out, S-video
input, CMOS Camera etc.
Responsibility
Generation of Functional Specifications
Circuit Design
Review of Placement and Routing
EPLD Design
Testing, Validation and support for Software partitioning
Led a team of 2 Engineers in this development.
Duration
April 2003 to August 2003
Detils
http://www.ittiam.com/pages/products/dma.htm
In-Flight Entertainment Unit
This system is based on TIs TMS320DSCxxx and TMS320C54x platform. The system
performs decode and playback of MP4 video and MP3 audio files stored in a Hard Disk
Drive. The unit has a small form factor suited for handheld applications.
Responsibility
Design of system architecture along with customer
Review of circuit schematics with significant contributions in LCD interface.
Testing and Validation
Duration
October 2003 April 2003
SLIC based subscriber interface card
This card provides a fully semiconductor based interface between the PSTN subscriber
and the central office and supports 16 subscribers per card.
Responsibility
Selection of SLIC and Codec chips.
Enhancements to Circuit Design and FPGA design
Functional, Parametric and High Voltage testing
Development of tester software for card and component testing
Led a team of 2 engineers in this project
Duration
July 2001 to September 2002

May 1996 to December 1997

GSM FR Codec implementation

This is a multi-channel implementation of the GSM FR standard on the TMS32054x
platform
Responsibility
Generation of software architecture
Coding of FR encoder and decoder
Design and coding of In band signaling module
Design and coding of McBSP, Timer and HPI drivers
Review of design and coding of data rate adaptation module
Integration Testing
Led a team of 3 engineers in this development
Duration
January 2000 to June 2001
Echo Canceller
This is an implementation of ITU-T G.168 Network Echo canceller on the TMS32054x
platform
Responsibility
Design and coding of the echo canceller algorithm in MATLAB and fixed point C
Led a team of 3 engineers in this development
Duration
February 2001 to April 2001
Value Engineered Base Module
This system forms the building block of C-DOTs Main Automatic Exchanges.
Responsibility
Support for software porting on the Terminal unit controller card
Design of Terminal Unit Integration testing software
System Integration testing and validation
Duration
July 1999 to December 1999
Transcoder and Rate Adaptation card design
This card forms the core of the TRAU system. The card is a 10 layer PCB with 16 DSPs,
one host processor, two E1 interfaces, EPLD, FPGA and power modules
Responsibility
Generation of Functional Specifications
Selection of DSP and host processor
Circuit Design, Placement and Routing
EPLD and FPGA design
Testing and validation
Support for Software porting

Duration
May 1998 to July 1999
Transcoder and Rate Adaptation Unit System design
The TRAU performs transcoding from GSM-FR to PCM A-law and vice versa and rate
adaptation from 8/16 Kbps to 64 Kbps and vice versa.
Responsibility
Generation of product specifications
Design of product architecture
Duration
December 1997 to May 1998