MOS Field-Effect Transistor

MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor.

In the MOSFET, the current is controlled by an electric field applied

perpendicular to both the semiconductor surface and to the direction of

current.

MOS Field-Effect Transistor

(MOSFET)
nea80644_ch03_125-204.qxd

nea80644_ch03_125-204.qxd

Basic transistor principle: voltage between two terminals controls the

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08:36 PM

08:36 PM

current through the third terminal.

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127

Chapter 3 The Field-Effect Transistor

nea80644_ch03_125-204.qxd

Gate terminal
Metal
Insulator
(oxide)

MOSFET Structure

Gate
terminal
Semiconductor
substrate

Metal
Insulator
(oxide)

eox

tox

and body
MOSFET is a four-terminal device: gate (G), source (S), drain (D)Substrate
or

Chapter 3 The Field-Effect Transistor

Substrate
source.or
The device structure is basically symmetric in terms of drain and
body terminal
Source and drain terminals are specified by the operation voltage.

3.1
The

MOS
capacitor structure
Figure
basic

tox

Semiconductor
substrate

V
+

p-type

h+

V
+

V
+

E-field
+ + + +Substrate
+ + or
body terminal
p-type

E-field

Metal
Insulator
(oxide)

eox

Figure
MOS capacitor structure
3.1
The
basic

Accumulation

layer of holes E-field

+ + + + + +
MOS capacitor
with a negative
(b)
(c)

p-type

gate bias

E-field
V
dFiguree3.2 (a) E-field
V
A parallel-plate capacitor,
showing
charges,
p-type the
h+ electric field and conductor
+
e
d
E-field
+
Accumulation
and
+(b) a+ corresponding
+
+
+ MOS
+ capacitor with a negative gate bias, showing the electric field
+
+
+
+
layer of+holes
charge flow, and (c) the MOS capacitor with an accumulation layer of holes

E-field

(a)

Trng Cng Dung Nghi

(a)

127

Gate terminal

Metal-oxide-semiconductor capacitor:

ox : oxide permittivity.

Page 1

Two-Terminal MOS Structure

Semiconductor
(B).
heart of the MOSFET
body terminal
substrate
Two kinds of MOSFETs: n-channel (NMOS) and p-channel
(PMOS)
tox : thickness of the oxide
Figure
3.1 The basic MOS capacitor structure

devices

08:36 PM

Trng Cng Dung Nghi

eox

tox

06/08/2009

(b)

semiconductor, the holes in the p-type semiconductor will experience a force toward

(c) (a)

V
+

V
+

p-type

h+

Trng Cng Dung Nghi

Figure 3.2 (a) A parallel-plate capacitor, showing the

Figure 3.2 (a) A parallel-plate capacitor, showing the electric field and conductor charges,

the
fixed
acceptor
he
sameapplied
MOS capacitor,
withinthe
polarity
of An
theinterface,
applied a negative space-charge region is created, because
deposited
outside
the
area in which the metal interconnect lines are formed. The gate
basic of
transistor
characteristics.
ticular
voltage is but
shown
Figure
3.2(c).
accuimpurity
atoms.
The
negative
charge
in
the
induced
depletion
region
corresponds
to doped polysilicon. Even though the actual structure of a
ive
charge
now
exists
on
the
top
metal
plate
and
the
inmaterial
is
usually
heavily
ly charged holes at the oxide-semiconductor interface
negative charge on the bottom plate of the MOS capacitor.
Figure
shows
he opposite
as shown.
this case,
if thethe
electric
MOSFET
may3.3(b)
be Operation
fairly
complex, the simplified diagram may be used to develop the
Basic Transistor
charge
on thedirection,
bottom plate
of theInMOS
capacitor.
the
equilibrium
distribution
of
charge
in
the
MOS
capacitor
with
this
applied
voltage.
onductor,
holes
in the p-type
material
will experience
a force
basic
characteristics.
With transistor
zero bias applied
to the gate, the source and drain terminals are separated by the
same MOS
capacitor,
but with
the polarity
of the applied
conductor
interface.
As
the
holes
are
pushed
away
from
the
p-region,
as
shown
in
Figure
3.6(a). This is equivalent to two back-to-back diodes, as
e charge now exists on the top metal plate and the in+ + + + + +
+ + + + Basic
Transistor
Operation
shown
in
Figure
3.6(b).
The
current
in this case is essentially zero. If a large enough
ce-charge
region
is
created,
because
of
the
fixed
acceptor
e opposite direction, as shown. In this case, if the electric
+
+
With
zerobias
bias
applied
toisthe
and drain
terminals
by the
positive
gate
voltage
applied,
inversion
layerareisseparated
created at
tive charge
induced
depletion
region
corresponds
gate,
the
the
an
source
electron
ductor,
holesininthe
the
p-type
material
experience
a force to
Effect
of positive
gatewill
bias:
With
zero
applied
to
the
gate,
source
and
drain
terminals
are
x

V
dT
xd
V
+ + + +
p-region,
as
shown
in
Figure
3.6(a).
This
is
equivalent
to
two
back-to-back
diodes,
as
oxidesemiconductor
interface
and
this
layer
connects
the
n-source
to
the
n-drain
eonductor
bottom plate
of
the
MOS
capacitor.
Figure
3.3(b)
shows
separated by the p-region
Two pn junctions (S-B) and (D-B)
are

interface. As the holes are pushed away from the

p-type
p-type
+
shown
in
Figure
3.6(b).
The
current
in
this
case
is
essentially
zero.
If
a
large
enough
on
of charge
in the
MOS capacitor
thisfixed
applied
voltage.
connected as two back-to-back diodes
-charge
region
is created,
becausewith
of the
acceptor
Gate (G)
V
positive gate voltage
is negative
applied, an electron inversion layer is created at the
E-field
Induced
+
The
source
and
drain
terminals
are isolated by
two depletion regions
ve charge in the induced depletion region corresponds
to
Electron

Induced
negative
p-type
h

+ + + + + +
oxidesemiconductor
interface
and
layer
connects
space-charge
Source
(S)
(D) this
space-charge
S
+ + capacitor.
+ +
without
conducting
current
Drain
The current
isinversion
essentially
zero. the n-source to the n-drain
bottom plate of the MOS
Figure 3.3(b) shows
layer
region
region
+
+ voltage.
of charge in the MOS capacitor with this applied
Gate (G)

x
+
+

Two-Terminal MOS Structure

xd

+
V

+
V

p-type
+ +

+ +

Induced negative
xd
space-charge
p-type region

(a)

dT

Operation with zero gate voltage

(b)

n
Source (S)

p-type + + + +
Figure +3.3+ The
MOS capacitor with p-type substrate: (a) effect of positive gate bias,
p-type
showing
the
electric
field and charge+flow, (b) the MOS capacitor with an
induced spaceInduced
negative
Electron

n+
xdT
V
charge
region due to a moderate
an
space-charge
inversion positive gate bias, and (c) the MOS capacitor with L

layerand electron
induced
space-charge region
inversion layer due to a larger positive gate bias
region
p-type

+
V

(b)

Induced negative
Induced negative
space-charge
itor with p-type substrate:
(a) effect of positive gate bias,space-charge
region
region

d charge flow, (b) the MOS capacitor with an induced space(b)(c) the MOS capacitor with5 an
rate positive gate bias, and
and electron inversion layer due to a larger positive gate bias
r with p-type substrate: (a) effect of positive gate bias,
charge flow, (b) the MOS capacitor with an induced spacete positive gate bias, and (c) the MOS capacitor with an
nd electron inversion layer due to a larger positive gate bias

(c)

(c)

p-type

Electron
inversion
layer
Trng Cng Dung Nghi

(c)

n+

Drain (D)
n+

Substrate or body (B)

(a)

S
S

(b)

Figure 3.6 (a) Cross section of the n-channel MOSFET prior to the formation of an electron
inversion layer, (b) equivalent back-to-back diodes between source and drain when the
transistor is in cutoff, and (c) cross section after the formation of an electron inversion layer

Creating a channel for current flow

Large positive gate voltage is applied.

Positive charges accumulate in gate as a positive voltage applies to gate

Gate voltage exceeds a

The electric field forms

threshold voltage vGS > Vt:

electrons start to accumulate
on the substrate surface.

The positive vGS > Vt is

a depletion region by
pushing holes in p-type
substrate away from
the surface.

used to induce the channel

and it is called n-channel
enhancement-type
MOSFET.

The induced n region forms

a channel for current flow
from drain to source.

The channel is created by inverting the substrate surface from p-type to ntype -> inversion layer.

The field controls the amount of charge in the channel and determines the
7

Trng Cng Dung Nghi

Su

Figure 3.6 (a) Cross section of the n-channel MOSFET prior to the formation of an electron
Substrate or body (B)
Su
inversion layer, (b) equivalent back-to-back diodes between source and drain when the
Trng
Cng
Dung
Nghi
6
(a)
(b)
transistor is in cutoff,
and (c) cross section after the formation
of an electron inversion layer

Creating a channel for current flow

electrode.

n+

channel conductivity.

Trng Cng Dung Nghi

4.qxd
4.qxd

vGS1 > VTN

Channel
inversion
charge
iD

vGS1

Small drain voltage

Oxide

Increasing drain voltage

iD
Oxide
132
Part 1 Semiconductor Devices and Basic Applications
S
nea80644_ch03_125-204.qxd vDS
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vDS

nea80644_ch03_125-204.qxd

Depletion
p-type free electrons
Small vDS is applied:
region

p-type

travel from source to drain through

the induced n-channel.

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08:36 PM

Page 132 F506 Hard disk:Desktop Folder:MHDQ134-03:

vGS1 > VTNalong the channel increases from 0 to vDS ,

As vDS increases, the voltage

Channel
inversion
charge

Channel

vGS1
and the voltage between the gate andinversion
the points along the channel
decreases
from vGS at the source end to (vGS - charge
vDS) at the drain end.
iD

Oxide

S
L
vDS
resulting
flows
layer depends on the voltage
difference
The 08:36
Since the inversion
D
06/08/2009
08:36 PM
PMcurrent
Page i132
132
F506 Hard
Hard disk:Desktop
disk:Desktop Folder:MHDQ134-03:
Folder:MHDQ134-03:
S
06/08/2009
Page
F506
132
Part 1 Semiconductor Devices and
Basic Applications
from drain ito source (opposite
structure,
increasing
vDS
will
result
in
a
tapered
channel.
iD
D
Depletion
132
Part 1 Semiconductor Devices and Basic Applications
to the direction of the flow of
p-type

art 11 Semiconductor
Semiconductor Devices
Devices and
andBasic
BasicApplications
Applications
art
vDS

The current is proportional to the

vDS

vvGS1
GS1>>VVTN
TN
vGS1

Channel
Channel
inversion
inversion
charge
charge
iD
iD
iD
vvDS
DS

Oxide
Oxide
Oxide

effective voltage or overdrive

voltage: vOV = vGS - Vt

vDS (sat)

Oxide
iDiD i
Oxide
Oxide
vDS (sat) TrngDCng Dung Nghi
vDS
vDS
vDS > vDS (sat)
E-field depletion region
Channel
Channel
inversion
inversion
p-type
p-type
Channel
p-type
charge
charge
inversion
charge

SS S

Depletion
region
p-type

p-type

vGS1
vGS1
isvGS1
controlled by the
The channel

Depletion
Depletion
Channel
region
region
inversion
charge

p-type
p-type
p-type

continue as a straight line.

vGS1not
> VTN
vGS1 >Channel
VTN
L
inversion
Channel
charge
inversion
i
D
iD
Oxide
charge
Oxide vDS iD
S
S
vDS

number of carriers in (b)

the induced
channel.

(a)

iD

LL

iiDD

iD vDSsat = vGS - Vt , the channel is

At the point

Small vLDS value

(a)

Increasing vDS beyond this value has little effect

vvDS
DS
Triode region: vDS < vDSsat
(a)
(a) vDS (sat)
Saturation region: vDS vDSsat

(c)

Saturation
region

(b)
(b)

vDS
vGS1
vGS1

vDS (sat)

Channel
Channel
inversion
inversion
charge
charge

vDS

Channel
inversion
charge

p-type

(d)

vDS (sat)

p-type
charge

1 2
v
2 DS
v

Vt ) vDS
vGS1

iD

iD

> DS
vDS (sat)
E-field
E-fielddepletion
depletionregion
region

vDS

(b)

Trng Cng Dung Nghi

iD

vDS > vDS (sat)

E-field depletion region

vp-type
DS

(b)

Channel
inversion
charge

GS1

1
= kn Oxide
(vGS
2
v

iD

Vt )
Oxide iD
i
(sat)
Saturation
vDS (sat) v >Dv (sat)
S DS
DS
DS vDS > vDS (sat) region
1 E-field depletion
region
E-field
depletion region

S
vDS (sat)

inversion
charge

Channel
inversion
charge

Oxide
vDS (sat)

vDS

kn (vGS Vt )p-type
Channel
vDS (sat) p-typevDS
inversion

2):
(c)
Transconductance parameter (A/V
kn =

where

(b)

vDS

vGS1

iD

iD

p-type

(a)

Oxide

DS
vDS

p-type
p-type

iD

I-V relationship

Channel
rDS =
resistance:
Channel inversion
Channel

vDS

MOSFET when vG iS > VT N for (a) a small v DS

value, (b) a larger v DS value but for
Oxide
iD
D
Oxide
i
Oxide
Oxide
SS v DS < v DS (sat) , (c) v DS = v DS (sat), andS(d) v DS > vvDS
(sat) DiD
(sat)
vDS
vvDS (sat)
DS (sat)
S
(sat)
v > v (sat)
p-type
p-type

Large
10 vDS value

vDS (sat)

Saturation
iD region: i iDsat

Figure 3.9 Cross section and i D versus v DS curve for an n-channel enhancement-mode

DS

p-type

Oxide

vGS1

Oxide
S

vDS
vDS

vDS iD

Channel
inversion
p-type charge

vDS

vGS1

iD

Oxide

Triode region: iD = kn (vGS

vGS1

Triode
region

on the channel shape and iD saturates at this value.

iD

iD

Oxide

iD

vDS

iD

pinched off at the drain side.

vGS1

Depletion
region

iDiD

charge

vGS1

(a)

Increasing drain voltage

vvGS1
GS1

vDS

Channel
channel and the iD-vDSp-type
curve doesinversion
The resistance increases due to taperedregion

negative charge).

SS

iD
Oxidethe MOS
across

Channel
vDS (sat)
inversion
charge Wcharge 0 W (d)
n Cox
= kn

vDS

L
L
Figure 3.9 Cross section and i D versus v DS curve for an n-channel enhancement-mode
Cox : oxide
capacitance per unit area Cox = ox / tox
MOSFET when vG S > VT N for (a) a small v DS value, (b) a larger v DS value but for
i

(c) v DSD= v DS (sat),

(d) vthickness.
DS (sat) , permittivity
ox andv DStox<:voxide
andD and
oxide
DS > v DS (sat)

n : mobility of the electrons in the inversion

Saturation
Saturation layer.
region

W and L: channel width and channel length.

Channel
Channel
inversion
inversion
charge
charge

region

generate the family of curves for this n-channel enhancement mode MOSFET as

v
vDS
vDS
generate the family of curves for this n-channel enhancement mode MOSFET as
vDSv(sat)
vDS(sat)
vDS (sat)
vDS (sat)
DS
shown in DS
Figure 3.10.
Trng Cng Dung Nghi
Trng Cng Dung
11
12
(c)
(d)
shown in Figure 3.10.
Although the derivation of(d)
the currentvoltage characteristics
ofNghi
the MOSFET
(c)
is
beyond
the
scope
of
this
text,
we
can
define
the
relationships.
The region for
Although
the
derivation
of
the
currentvoltage
characteristics
of
the
MOSFET
iiD
iDi
i
v
Figure
3.9
Cross
section
and
versus
curve
for
an
n-channel
enhancement-mode
D curve for
DSan n-channel enhancement-mode
D
D
Figure 3.9 Cross section and i D which
versus vv DS
< av DS
(sat)
is known(b)asa the
nonsaturation
or triode region. The ideal
DS (a)
is beyond the scope of this text, we can define the relationships. The region for
> VaTsmall
v(b)
MOSFET
small
value but for
G S (a)
N for v
DSavalue,
DS for
V vfor
v >when
MOSFET when
value,
larger v larger
value vbut
GS

TN

DS

DS

nea80644_ch03_125-204.qxd

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08:37 PM

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p-channel enhancement-type MOSFET

Circuit Symbols and Conventions

Chapter 3 The Field-Effect Transistor

135

p-channel enhanced-type MOSFETs are

n-channel enhancement-mode MOSFET:

vSD
fabricated on n-type substrate with p+
+

iD
vSG
source and p+ drain.
Normally, source is connected to high
Source
Gate W
Drain
voltage and drain is connected to low
tox
voltage.
p+
p+
As a negative voltage applies to gate
L
electrode, negative charges accumulate
n-type
in gate and the resulting field pushes
p-channel enhancement-mode MOSFET:
Body
electrons in n-type substrate away from
the surface, leaving behind a carrier-depletion
Figureregion.
3.11 Cross section of p-channel enhancement-mode MOSFET. The device is cut off
= 0. TheV
dimension
extends
for v SG
As gate voltage exceeds a negative threshold
voltage
tointo the plane of the page.
t, holesWstart
accumulate on the substrate surface.
The induced p region (inversion layer) thusTransistor
forms aStructure
p-type channel for
Figure 3.11 shows a simplified cross section of the p-channel enhancementcurrent flow from source to drain.
mode transistor. The substrate is now n-type and the source and drain areas are
Negative gate voltage is required to inducep-type.
the channel
The channel length, channel width, and oxide thickness parameter definitions
are the same as those for the NMOS device shown in Figure 3.5(a).
enhancement-type MOSFET.
Trng Cng Dung Nghi
13
14

Basic Transistor Operation

The operation of the p-channel device is the same as that of the n-channel device,
except the hole is the charge carrier rather than the electron. A negative gate bias is
required to induce an inversion layer of holes in the channel region directly under the
oxide. The threshold voltage for the p-channel device is denoted as VT P .4 Since the
threshold voltage is defined as the gate voltage required to induce the inversion layer,
then VT P < 0 for the p-channel enhancement-mode device.
Once the inversion layer has been created, the p-type source region is the source
of the charge carrier so that holes flow from the source to the drain. A negative
drain
region (vGS Vt) : iD = 0
Cut-off
voltage is therefore required to induce an electric field in the channel forcing the
holes to move from the source to the drain. The conventional current direction,
then,
Triode region (vGS > Vt and vDS < vGS - Vt)

for the PMOS transistor is into the source and out of the drain. The conventional
W
current direction and voltage polarity for the PMOS device are reversed compared to
iD = n Cox
(vGS Vt ) vDS
the NMOS device.
L
Note in Figure 3.11 the reversal of the voltage subscripts. For v SG > 0, the
gate
Saturation (vGS > Vt and vDS vGS - Vt)
voltage is negative with respect to that at the source. Similarly, for v S D > 0, the
1
W
2
drain voltage is negative with respect to that at the source.

Current-voltage characteristics (n-channel MOSFET)

Trng Cng Dung Nghi

Current-voltage characteristics (n-channel MOSFET)

1 2
v
2 DS

iD =

3.1.5

Ideal MOSFET CurrentVoltage

CharacteristicsPMOS Device

n Cox
(vGS Vt )
2
L
Large-signal equivalent-circuit model operating in the saturation:

The ideal currentvoltage characteristics of the p-channel enhancement-mode device

are essentially the same as those shown in Figure 3.10, noting that the drain current
4

Using a different threshold voltage parameter for a PMOS device compared to the NMOS device is for
clarity only.

15

Trng Cng Dung Nghi

16

Trng Cng Dung Nghi

Current-voltage characteristics (p-channel MOSFET)

MOSFET Circuits at DC
DC analysis for MOSFET circuits:
Assume the operation mode and solve the dc bias utilizing the
corresponding current equation.

Verify the assumption with terminal voltages (cutoff, triode and saturation).
If the solution is invalid, change the assumption of operation mode and

Overdrive voltage:

analyze again.

vOV = vGS - Vt
vSG = |Vt| + |vOV|

Condition for operation in the triode region:

(1) vGS Vt vOV 0 vSG |Vt|

(2) vDG |Vt| vDS vGS - Vt vSD |vOV|

Condition for operation in the saturation region:

(1) vGS Vt vOV 0 vSG |Vt|

(2) vDG |Vt| vDS vGS - Vt vSD |vOV|
17

Trng Cng Dung Nghi

MOSFET Circuits at DC
Ex: The NMOS transistor in the following circuit has Vt = 0.7V, nCox =

100A/V2, L = 1m and W = 32m. Design the circuit so that the transistor

operates at ID = 0.4mA and VD = 0.5V.
VD = 0.5V > VG : NMOS transistor operates in the
saturation region.
1
W
2
) ID = n Cox
(VGS Vt )
2
L
) VGS = 1.2V
VSS
= 3.25k
ID
VDD VD
=
= 5k
ID

RS =
RD

VS

19

18

MOSFET Circuits at DC
Ex: The NMOS transistor in the following circuit has Vt = 0.6V, nCox =

200A/V2, L = 0.8m and W = 4m. Design the circuit so that the transistor
operates at ID = 80A. Find the dc voltage VD.
VDG = 0, VD = VG : NMOS transistor operates in the
saturation region.
1
W
2
) ID = n Cox
(VGS Vt )
2
L
) VGS = 1V
R=

Trng Cng Dung Nghi

Trng Cng Dung Nghi

VDD VD
= 25k
ID

20

Trng Cng Dung Nghi

MOSFET Circuits at DC
Ex: Design the circuit so that the transistor operates at VD = 0.1V. Let Vt =

1V, nCox(W/L) = 1mA/V2. Find the effective resistance between drain and
source at this operating point.
VDS < VGS and VGS > Vt : NMOS operates in the
triode region.

W
1 2
ID = n Cox
(VGS Vt ) VDS
V
L
2 DS
= 0.395mA
VDD VD
= 12.4k
ID
VDS
=
= 253
ID

RD =
rDS

21

Trng Cng Dung Nghi

Non-ideal current-voltage characteristics

iD

Finite output resistance:

Ideal case: the drain current iD is

Slope =

ro
independent of drain-to-source
voltage vDS in the saturation region.
Actual case: a nonzero slope
exists beyond the saturation
vDS
0
VA = 1
point in MOSFET iD versus

vDS characteristics.
1Figure
W3.20 Family of2i D versus v DS curves showing the effect of cha
iD versus vDS characteristic: iD = modulation
k0
(vGS
Vt ) a (1
+ vDS resistance
)
producing
finite output
2 nL
Finite output resistance:

1
@iD
ro
The parameters and V A are related. From Equati
@vDS vGS =const
(1 + v DS ) = 0 at the extrapolated point where i D = 0. At thi
0
1 which means that V = 1/.
A
kn W
2
=
(vGS Vt )
The output resistance due to the channel length modulation
1 L
#

1/ ID = VA /ID

22

ro =

i D
v DS

"1 #
#
#
#

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vG S =const.

From Equation (3.7), the output resistance, evaluated at the Q-p

Biasing in MOS amplifier

DC bias for MOSFET amplifier:
The amplifiers are operating at a proper dc bias point.
The DC bias circuit is to ensure the MOSFET in saturation with a proper

drain current ID.

Biasing by fixing gate-to-source voltage:
Fix the dc voltage VGS to specify the saturation current of the MOSFET:
1
1
2
2
ID = kn (VGS Vt ) = kn (VG Vt )
2
2
The bias current deviates from the desirable value due to variations in the
device parameters Vt and n.

ro = [K n (VG S Q VT N )2 ]1

Biasing in MOS amplifier

or

ro
= [ I D Q ]1 =

1
VA
=
IDQ
IDQ

Biasing by fixing gate voltage and connecting a source resistance:

The output resistance ro is also a factor in the small-signal equ
The bias condition is specified by: MOSFET, which is discussed in the next chapter.

1
2
VG = VGS + kn (VGS Vt ) RS
Body Effect
2
1
2
ID = kn (VGS Vt ) Up to this point, we have assumed that the substrate, or body
source. For this bias condition, the threshold voltage is a consta
2
in thecircuits,
device however,
parameters.
Drain current has better tolerance to variations
In integrated
the substrates of all n-cha

usually common and are tied to the most negative potential in t

ple of two n-channel MOSFETs in series is shown in Figu
S1

VI

VO

D1
n+

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24

S2

D2

n+
M1

23

VDD

n+
M2

p-substrate Trng Cng Dung Nghi

Figure 3.21 Two n-channel MOSFETs fabricated in series in the same

Biasing in MOS amplifier

Biasing using a drain-to-gate feedback resistor:
A single power supply is needed.
RG ensures the MOSFET in saturation (VGS = VDS)
MOSFET operating point:
VDD VGS
1
= kn (VGS
RD
2

Vt )

Biasing in MOS amplifier

Biasing using a constant-current source:
The MOSFET can be biased with a constant current
source I.

The resistor RD is chosen to operate the MOSFET

in active mode.

The current source is typically a current mirror.

Current mirror circuit:
MOSFETs Q1 and Q2 are in saturation.
The reference current IREF = I = ID
When applying to the amplifier circuit, the

The value of the feedback resistor RG affects the

small-signal gain.

voltage VD2 has to be high enough to ensure

Q2 in saturation.

25

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26

Small-signal operation and models

Small-signal operation and models

DC bias point:
MOSFET in saturation

Small-signal operation:
Small-signal drain current:

Drain current:

vGS = VGS + vgs

1
2
iD = kn (VGS + vgs Vt )
2
1
2
= kn (VGS Vt ) + kn (VGS
2
1
2
kn (VGS Vt ) + kn (VGS
2

1
1
2
2
ID = kn (VGS Vt ) = kn VOV
2
2
Drain voltage: VDS = VDD - IDRD > VOV

The small-signal circuit parameters are

determined by the bias point.

) id = kn (VGS

1
2
Vt ) vgs + kn vgs
2
Vt ) vgs = ID + id

Vt ) vgs

Transconductance gm: describes how id change with vgs.

gm =

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id
@iD
=
vgs
@vGS

= kn (VGS
vGS =VGS

28

Vt ) =

2kn ID

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Small-signal operation and models

Small-signal operation and models

Small-signal operation:
Small-signal voltage gain:

Hybrid- model:

vD = VDD

) vd =

iD RD = VDD

i d RD =

) Av =

vd
=
vgs

(ID + id ) RD = VD

i d Rd = VD + v d

kn VOV RD vgs

kn VOV RD

Output resistance (ro): describes how id change with vds

@iD
ro =
@vDS

1
vGS =const

Transconductance:

1
VA

=
ID
ID

29

W
gm = n Cox VOV =
L
Output resistance:
VA
1
ro =
=
ID
ID
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Small-signal operation and models

2n Cox

30

W
2ID
ID =
L
VOV

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Small-signal operation and models

Ex: Determine the small-signal voltage gain, and the input resistance of the
following MOSFET amplifier circuit. The transistor has Vt = 1.5V, kn =
0.25mA/V2 and VA = 50V.

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32

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Small-signal operation and models

Small-signal operation and models

T Equivalent-circuit model:

T Equivalent-circuit model:

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33

34

5.6 Basic MOSFET Amplifier Configuration

basic
configurations
5.6Three
Basic
MOSFET
Amplifier
Configuration
Basic
MOSFET
amplifier
configuration
Common-Source (CS)

Common-Gete (CG)

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Common-source amplifier

Common-Drain (CD)

nfigurations

mon-Source (CS)

Common-Gete (CG)

Common-Drain (CD)

5.6 Basic MOSFET Amplifier Configuration

urations
Common-Source
(CS)(CG)
Common-Gete

Source (CS)

Common-Drain (CD)

Characterizing amplifiers

The MOSFET circuits can be characterized

by a voltage
Common-Drain
(CD) amplifier model (unilateral model)
T circuits can be characterized
by properties
a voltage amplifier
model (unilateral
model) by Rin, Ro and Avo
The electrical
of the amplifier
is represented
properties of theThe
amplifier
is represented
by Rthe
in, R
o and Avo
analysis
is based on
small-signal
or linear equivalent circuit where dc components are not included
amplifiers

s based on the small-signal or linear equivalent

vo
RLcircuit where dc components are not included
Voltage gain: Common-Gate
Av
Avo
vo
RL
vi RL (CG)
Ro35
Av
Avo
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vi RL Ro
vo
Rin
Rin
RL
Overall
voltage
gain:
v
R
R
R
GL v A
Av
Avo
o
in
in
ge
gain: Gv
plifiers
Av
vo
Rin Rsig
Rin Rsig RL Rso
v
R R
R R R R vsig
sig

in

sig

in

sig

so

36

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CS with a source resistance

37

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Common-drain (CD) amplifier

39

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Common-gate (CG) amplifier

38

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